Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 70)
+++ trunk/MultiChannelUSB/Paella.v	(revision 72)
@@ -6,5 +6,5 @@
 		inout	wire	[3:0]	TRG,
 		inout	wire			I2C_SDA,
-		output	wire			I2C_SCL,
+		inout	wire			I2C_SCL,
 		inout	wire	[4:0]	CON_A,
 		inout	wire	[15:0]	CON_B,
@@ -43,4 +43,6 @@
 	);
 
+	localparam	N		=	3;
+
 	//	Turn output ports off
 /*
@@ -105,16 +107,38 @@
 	);
 	
-	reg 			ana_reset [3:0];
-	wire			ana_peak_ready [3:0];
-	wire	[11:0]	ana_peak [3:0];
-
-	reg 			osc_reset [3:0];
-	reg 	[9:0]	osc_addr [3:0];
-	wire	[9:0]	osc_start_addr [3:0];
-	wire	[15:0]	osc_q [3:0];
-
-	reg 			hst_reset [3:0];
-	reg 	[11:0]	hst_addr [3:0];
-	wire	[31:0]	hst_q [3:0];
+	reg 			bln_reset [N-1:0];
+	wire	[11:0]	baseline [N-1:0];
+	wire	[11:0]	bln_baseline [N-1:0];
+
+	reg 			ana_reset [N-1:0];
+	wire			ana_peak_ready [N-1:0];
+	wire	[11:0]	ana_peak [N-1:0];
+
+	reg				osc_reset [N-1:0];
+	reg 	[9:0]	osc_addr [N-1:0];
+	wire	[9:0]	osc_start_addr [N-1:0];
+	wire	[15:0]	osc_q [N-1:0];
+	wire			osc_trig [N-1:0];
+
+	wire	[3:0]	osc_mux_sel [N-1:0];
+	wire	[11:0]	osc_mux_data [N-1:0];
+
+	wire 			trg_reset [N-1:0];
+	wire	[3:0]	trg_mux_sel [N-1:0];
+	wire	[11:0]	trg_mux_data [N-1:0];
+	wire	[11:0]	trg_thrs [N-1:0];
+
+	reg 			hst_reset [N-1:0];
+	reg 	[11:0]	hst_addr [N-1:0];
+	wire			hst_data_ready [N-1:0];
+	wire	[11:0]	hst_data [N-1:0];
+	wire	[31:0]	hst_q [N-1:0];
+
+
+	wire	[3:0]	hst_mux_sel [N-1:0];
+	wire	[12:0]	hst_mux_data [N-1:0];
+
+	wire	[3:0]	bln_mux_sel [N-1:0];
+	wire	[11:0]	bln_mux_data [N-1:0];
 
 	wire 			mux_reset, mux_type;
@@ -126,30 +150,37 @@
 	reg 	[15:0]	mux_min_addr, mux_max_addr;
 
-	wire			adc_clk [3:0];
-	wire			adc_data_ready [3:0];
-	wire 	[11:0]	adc_data [3:0];
-
-    wire	[11:0]	raw_data [3:0];
-    wire	[11:0]	uwt_data [3:0];
-    wire	[1:0]	uwt_flag [3:0];
+	wire			adc_clk [N-1:0];
+	wire 	[11:0]	adc_data [N-1:0];
+
+	wire			data_ready [N-1:0];
+    wire	[11:0]	data [N-1:0];
+    wire	[11:0]	int_data [N-1:0];
     
-    wire	[16:0]	osc_thrs [3:0];
-    wire			adc_pola [3:0];
-
+/*
     assign	osc_thrs[0] = 16'd40;
     assign	osc_thrs[1] = 16'd60;
     assign	osc_thrs[2] = 16'd40;
     assign	osc_thrs[3] = 16'd1650;
-
-    assign	adc_pola[0] = 1'b1;
-    assign	adc_pola[1] = 1'b1;
-    assign	adc_pola[2] = 1'b1;
-    assign	adc_pola[3] = 1'b0;
+*/
+	wire 	[31:0]	uwt_d1 [N-1:0];
+	wire 	[31:0]	uwt_a1 [N-1:0];
+	wire 	[31:0]	uwt_peak1 [N-1:0];
+	wire 	[31:0]	uwt_d2 [N-1:0];
+	wire 	[31:0]	uwt_a2 [N-1:0];
+	wire 	[31:0]	uwt_peak2 [N-1:0];
+	wire 	[31:0]	uwt_d3 [N-1:0];
+	wire 	[31:0]	uwt_a3 [N-1:0];
+	wire 	[31:0]	uwt_peak3 [N-1:0];
+
+	wire 	[1:0]	uwt_flag1 [N-1:0];
+	wire 	[1:0]	uwt_flag2 [N-1:0];
+	wire 	[1:0]	uwt_flag3 [N-1:0];
 
     assign	adc_clk[0] = ADC_FCO;
     assign	adc_clk[1] = ADC_FCO;
 //    assign	adc_clk[2] = ADC_FCO;
-
+/*
     assign	adc_clk[3] = ADC_FCO;
+*/
 /*    
     assign	adc_clk[3] = CON_CCLK[0];
@@ -196,63 +227,182 @@
 		.sdoin());
 */
-/*
+
 	adc_lvds #(
-		.size(3),
+		.size(2),
 		.width(12)) adc_lvds_unit (
 		.lvds_dco(ADC_DCO),
 //		.lvds_dco(adc_pll_clk),
 		.lvds_fco(ADC_FCO),
-		.lvds_d(ADC_D),
-		.adc_data({ adc_data[0],
-					adc_data[1],
-					adc_data[2] }));
-*/ 
+		.lvds_d(ADC_D[1:0]),
+		.adc_data({	adc_data[1],
+					adc_data[0] }));
+
+
+	reg		[15:0]	cfg_memory [31:0];
+	wire	[15:0]	cfg_src_data;
+	wire	[15:0]	cfg_src_addr, cfg_dst_data, cfg_dst_addr;
+
+	wire			cfg_polarity [N-1:0];
+	wire	[11:0]	cfg_baseline [N-1:0];
+	wire	[11:0]	cfg_hst_threshold [N-1:0];
+	wire	[11:0]	cfg_trg_threshold [N-1:0];
+
+	wire 			cfg_reset;
+
+	integer j;
+
+	always @(posedge CLK_50MHz)
+	begin
+		if (cfg_reset)
+		begin
+			for(j = 0; j <= 31; j = j + 1)
+			begin
+				cfg_memory[j] <= 16'd0;
+			end
+		end
+		else
+		begin
+			cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
+		end
+	end
+
 	genvar i;
+
 	generate
-		for (i = 0; i < 3; i = i + 1)
+		for (i = 0; i < N; i = i + 1)
 		begin : MCA_CHAIN
+
+			assign cfg_polarity[i] = cfg_memory[10][4*i];
+			assign cfg_baseline[i] = cfg_memory[11+i][11:0];
+			assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
+			assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
+
+			assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
+			assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
+			assign hst_mux_sel[i] = cfg_memory[20+i][11:8];
+			assign bln_mux_sel[i] = cfg_memory[20+i][15:12];
+
 			adc_fifo adc_fifo_unit (
 				.adc_clk(adc_clk[i]),
 				.adc_data(adc_data[i]),
-				.polarity(adc_pola[i]),
-				.clk(CLK_50MHz),
-				.ready(adc_data_ready[i]),
-				.raw_data(raw_data[i]),
-				.uwt_data({uwt_flag[i], uwt_data[i]}));
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.data(int_data[i]));
+
+			assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
+
+			uwt_bior31 #(.L(1)) uwt_1_unit (
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.x({20'h00000, data[i]}),
+				.d(uwt_d1[i]),
+				.a(uwt_a1[i]),
+				.peak(uwt_peak1[i]),
+				.flag(uwt_flag1[i]));
+		
+			uwt_bior31 #(.L(2)) uwt_2_unit (
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.x(uwt_a1[i]),
+				.d(uwt_d2[i]),
+				.a(uwt_a2[i]),
+				.peak(uwt_peak2[i]),
+				.flag(uwt_flag2[i]));
+		
+			uwt_bior31 #(.L(3)) uwt_3_unit (
+				.clk(CLK_50MHz),
+				.data_ready(data_ready[i]),
+				.x(uwt_a2[i]),
+				.d(uwt_d3[i]),
+				.a(uwt_a3[i]),
+				.peak(uwt_peak3[i]),
+				.flag(uwt_flag3[i]));
+
+			lpm_mux #(
+				.lpm_size(4),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(12),
+				.lpm_widths(2)) osc_mux_unit (
+				.sel(osc_mux_sel[i][1:0]),
+				.data({	uwt_a3[i][20:9],
+						uwt_a2[i][17:6],
+						uwt_a1[i][14:3],
+						data[i] }),
+				.result(osc_mux_data[i]));
+
+			lpm_mux #(
+				.lpm_size(4),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(12),
+				.lpm_widths(2)) trg_mux_unit (
+				.sel(trg_mux_sel[i][1:0]),
+				.data({	uwt_a3[i][20:9],
+						uwt_a2[i][17:6],
+						uwt_a1[i][14:3],
+						data[i] }),
+				.result(trg_mux_data[i]));
+
+			lpm_mux #(
+				.lpm_size(2),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(13),
+				.lpm_widths(1)) hst_mux_unit (
+				.sel(hst_mux_sel[i][0]),
+				.data({	{ana_peak[i], ana_peak_ready[i]},
+						{data[i], data_ready[i]} }),
+				.result(hst_mux_data[i]));
 	
+			lpm_mux #(
+				.lpm_size(2),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(12),
+				.lpm_widths(1)) bln_mux_unit (
+				.sel(bln_mux_sel[i][0]),
+				.data({bln_baseline[i], cfg_baseline[i]}),
+				.result(bln_mux_data[i]));
+
+			baseline baseline_unit (
+				.clk(CLK_50MHz),
+				.reset(bln_reset[i]),
+				.data_ready(data_ready[i]),
+				.uwt_flag(uwt_flag3[i]),
+				.uwt_data(uwt_peak3[i]),
+				.baseline(bln_baseline[i]));
+
 			analyser analyser_unit (
 				.clk(CLK_50MHz),
 				.reset(ana_reset[i]),
-				.data_ready(adc_data_ready[i]),
-				.uwt_flag(uwt_flag[i]),
-				.uwt_data(uwt_data[i]),
-				.threshold(12'd10),
+				.data_ready(data_ready[i]),
+				.uwt_flag(uwt_flag3[i]),
+				.uwt_data(uwt_peak3[i]),
 				.peak_ready(ana_peak_ready[i]),
 				.peak(ana_peak[i]));
 
-			histogram histogram_unit (
+			assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0;
+			assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
+
+			histogram #(.W(32)) histogram_unit (
 				.clk(CLK_50MHz),
 				.reset(hst_reset[i]),
-				.data_ready(adc_data_ready[i]),
-				.data(raw_data[i]),
-//				.data(uwt_data[i]),
+				.data_ready(hst_data_ready[i]),
+				.data(hst_data[i]),
 				.address(hst_addr[i]),
 				.q(hst_q[i]));
-/*
-			histogram histogram_unit (
-				.clk(CLK_50MHz),
-				.reset(hst_reset[i]),
-				.data_ready(ana_peak_ready[i]),
-				.data(ana_peak[i]),
-				.address(hst_addr[i]),
-				.q(hst_q[i]));
-*/			
+
+			trigger trigger_unit (
+				.clk(CLK_50MHz),
+				.reset(trg_reset[i]),
+				.data_ready(data_ready[i]),
+				.data(trg_mux_data[i]),
+				.threshold(cfg_trg_threshold[i]),
+				.trigger(osc_trig[i]));
+
+			
 			oscilloscope oscilloscope_unit (
 				.clk(CLK_50MHz),
 				.reset(osc_reset[i]),
-				.data_ready(adc_data_ready[i]),
-				.raw_data(raw_data[i]),
-				.uwt_data(uwt_data[i]),
-				.threshold(osc_thrs[i]),
+				.data_ready(data_ready[i]),
+				.data(osc_mux_data[i]),
+				.trigger(osc_trig[i]),
 				.address(osc_addr[i]),
 				.start_address(osc_start_addr[i]),
@@ -261,9 +411,7 @@
 	endgenerate
 
-	integer j;
-
 	always @*
 	begin
-		for (j = 0; j < 4; j = j + 1)
+		for (j = 0; j < N; j = j + 1)
 		begin
 			osc_reset[j] = 1'b0;
@@ -273,6 +421,8 @@
 		end
 
-		case({mux_type, mux_chan})
-			3'b000, 3'b001, 3'b010, 3'b011:
+		case(mux_type)
+//		case({mux_type, mux_chan})
+			1'b0:
+//			3'b000, 3'b001, 3'b010, 3'b011:
 			begin
 				osc_reset[mux_chan] = mux_reset;
@@ -283,5 +433,6 @@
 			end
 
-			3'b100, 3'b101, 3'b110, 3'b111:
+			1'b1:
+//			3'b100, 3'b101, 3'b110, 3'b011:
 			begin
 				hst_reset[mux_chan] = mux_reset;
@@ -332,4 +483,9 @@
 	control control_unit (
 		.clk(CLK_50MHz),
+		.cfg_reset(cfg_reset),
+		.cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
+		.cfg_src_addr(cfg_src_addr),
+		.cfg_dst_data(cfg_dst_data),
+		.cfg_dst_addr(cfg_dst_addr),
 		.rx_empty(usb_rx_empty),
 		.tx_full(usb_tx_full),
