Index: trunk/MultiChannelUSB/Paella.v =================================================================== --- trunk/MultiChannelUSB/Paella.v (revision 64) +++ trunk/MultiChannelUSB/Paella.v (revision 65) @@ -42,8 +42,12 @@ // Turn output ports off +/* assign RAM_CLK = 1'b0; assign RAM_CE1 = 1'b0; assign RAM_WE = 1'b0; assign RAM_ADDR = 20'h00000; +*/ + assign RAM_CLK = CLK_50MHz; + assign RAM_CE1 = 1'b0; // Turn inout ports to tri-state @@ -55,8 +59,8 @@ assign USB_PA3 = 1'bz; assign USB_PA7 = 1'bz; - assign RAM_DQAP = 1'bz; - assign RAM_DQA = 8'bz; - assign RAM_DQBP = 1'bz; - assign RAM_DQB = 8'bz; +// assign RAM_DQAP = 1'bz; +// assign RAM_DQA = 8'bz; +// assign RAM_DQBP = 1'bz; +// assign RAM_DQB = 8'bz; assign USB_PA2 = ~usb_rden; @@ -300,5 +304,5 @@ endcase end - + control control_unit ( .clk(CLK_50MHz), @@ -318,4 +322,7 @@ .tx_wrreq(usb_tx_wrreq), .tx_data(usb_tx_data), + .ram_we(RAM_WE), + .ram_addr(RAM_ADDR), + .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), .led(LED)); Index: trunk/MultiChannelUSB/control.v =================================================================== --- trunk/MultiChannelUSB/control.v (revision 64) +++ trunk/MultiChannelUSB/control.v (revision 65) @@ -16,8 +16,12 @@ output wire tx_wrreq, output wire [7:0] tx_data, + output wire ram_we, + output wire [19:0] ram_addr, + inout wire [17:0] ram_data, output wire led ); - reg [23:0] rx_counter; + reg [23:0] led_counter; + reg [18:0] ram_counter; reg [10:0] tst_counter; reg [15:0] int_addr, int_max_addr; @@ -30,5 +34,36 @@ + wire crc_error = 1'b0; + reg crc_reset; + reg [2:0] byte_counter; + reg [4:0] idle_counter; + reg [3:0] state; + + wire [15:0] src, dst; + + reg [15:0] memory [15:0]; + reg [7:0] buffer [7:0]; + + assign src = (buffer[0][7]) ? memory[buffer[3][3:0]] : {buffer[2], buffer[3]}; + assign dst = {1'b0, buffer[0][6:0], buffer[1]}; + + reg int_ram_we; + reg [17:0] int_ram_data; + wire [17:0] int_ram_q; + wire [17:0] opt_ram_we; + assign ram_we = ~int_ram_we; + assign int_ram_q = ram_data; +// assign ram_data = int_ram_we ? int_ram_data : 18'bz; + assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]}; + + genvar j; + generate + for (j = 0; j < 18; j = j + 1) + begin : SRAM_WE + assign opt_ram_we[j] = int_ram_we; + assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz; + end + endgenerate always @(posedge clk) @@ -37,9 +72,9 @@ begin int_led <= 1'b0; - rx_counter <= 24'd0; + led_counter <= 24'd0; end else begin - if (&rx_counter) + if (&led_counter) begin int_led <= 1'b1; @@ -47,10 +82,10 @@ else begin - rx_counter <= rx_counter + 24'd1; + led_counter <= led_counter + 24'd1; end end case(state) - 1: + 0: begin int_rdreq <= 1'b1; @@ -60,47 +95,87 @@ int_byte <= 2'd0; int_reset <= 1'b0; - state <= 4'd2; - end - + crc_reset <= 1'b0; + int_ram_we <= 1'b0; + int_ram_data <= 16'd0; + ram_counter <= 19'd0; + idle_counter <= 5'd0; + byte_counter <= 3'd0; + state <= 4'd1; + end + + 1: + begin + // read 8 bytes + if (~rx_empty) + begin + idle_counter <= 5'd0; + byte_counter <= byte_counter + 3'd1; + buffer[byte_counter] <= rx_data; + if (&byte_counter) + begin + int_rdreq <= 1'b0; + state <= 4'd2; + end + end + else if(|byte_counter) + begin + idle_counter <= idle_counter + 5'd1; + if (&idle_counter) + begin + int_rdreq <= 1'b0; + crc_reset <= 1'b1; + state <= 4'd0; + end + end + end + 2: begin - if (~rx_empty) - begin - case (rx_data) - 8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53: - begin - int_rdreq <= 1'b0; - int_type <= rx_data[4]; - int_chan <= rx_data[1:0]; + crc_reset <= 1'b1; + if (~crc_error) + begin + memory[dst[3:0]] <= src; + + case (dst) + 16'h0000: + begin + state <= 4'd0; + end + + 16'h0001: + begin + int_type <= src[4]; + int_chan <= src[1:0]; int_reset <= 1'b1; - state <= 4'd1; - end - - 8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73: - begin - int_rdreq <= 1'b0; - int_type <= rx_data[4]; - int_chan <= rx_data[1:0]; + state <= 4'd0; + end + + 16'h0002: + begin + int_type <= src[4]; + int_chan <= src[1:0]; state <= 4'd3; end - 8'h30: - begin - int_rdreq <= 1'b0; - state <= 4'd1; - end - - 8'h31: - begin - int_rdreq <= 1'b0; + 16'h0003: + begin tst_counter <= 11'd0; state <= 4'd6; end + 16'h0004: + begin + int_ram_we <= 1'b1; + int_ram_data <= 18'd0; + ram_counter <= 19'd0; + state <= 4'd9; + end endcase end end + // mux transfer 3: begin + crc_reset <= 1'b0; int_addr <= mux_min_addr; int_max_addr <= mux_min_addr + mux_max_addr; @@ -124,5 +199,5 @@ if ((int_byte == int_max_byte) && (int_addr == int_max_addr)) begin - state <= 4'd1; + state <= 4'd0; end else @@ -145,8 +220,9 @@ 6: begin + crc_reset <= 1'b0; int_data <= tst_counter; int_wrreq <= 1'b1; tst_counter <= tst_counter + 11'd1; - state <= 4'd8; + state <= 4'd7; end 7: @@ -155,7 +231,7 @@ begin int_data <= tst_counter; - if (tst_counter == 11'd0) - begin - state <= 4'd9; + if (&tst_counter) + begin + state <= 4'd8; end else @@ -170,5 +246,58 @@ begin int_wrreq <= 1'b0; - state <= 4'd1; + state <= 4'd0; + end + end + // ram transfer + 9: + begin + crc_reset <= 1'b0; + state <= 4'd10; + end + 10: + begin + int_ram_data[8:1] <= ram_counter[7:0]; +// int_ram_data[8:1] <= 8'd0; + if (&ram_counter) + begin + state <= 4'd11; + end + else + begin + state <= 4'd9; + ram_counter <= ram_counter + 19'd1; + end + end + 11: + begin + int_ram_we <= 1'b0; + int_ram_data <= 18'd0; + ram_counter <= 19'd0; + state <= 4'd12; + end + 12: + begin + int_wrreq <= 1'b0; + state <= 4'd13; + end + 13: + begin + state <= 4'd14; + end + 14: + begin + if (~tx_full) + begin + int_data <= int_ram_q[8:1]; + int_wrreq <= 1'b1; + if (&ram_counter) + begin + state <= 4'd0; + end + else + begin + state <= 4'd12; + ram_counter <= ram_counter + 19'd1; + end end end @@ -176,5 +305,5 @@ default: begin - state <= 4'd1; + state <= 4'd0; end endcase