Index: /trunk/MultiChannelUSB/Paella.v
===================================================================
--- /trunk/MultiChannelUSB/Paella.v	(revision 62)
+++ /trunk/MultiChannelUSB/Paella.v	(revision 63)
@@ -7,5 +7,5 @@
 		inout	wire	[6:0]	CON_A,
 		inout	wire	[15:0]	CON_B,
-		inout	wire	[12:0]	CON_C,
+		input	wire	[12:0]	CON_C,
 		input	wire	[1:0]	CON_BCLK,
 		input	wire	[1:0]	CON_CCLK,
@@ -51,5 +51,4 @@
 	assign	CON_A		=	7'bz;
 	assign	CON_B		=	16'bz;
-	assign	CON_C		=	13'bz;
 	assign	USB_PA0		=	1'bz;
 	assign	USB_PA1		=	1'bz;
@@ -129,10 +128,33 @@
     wire	[1:0]	uwt_flag [3:0];
     
+    wire	[16:0]	osc_thrs [3:0];
+    wire			adc_pola [3:0];
+
+    assign	osc_thrs[0] = 16'd40;
+    assign	osc_thrs[1] = 16'd300;
+    assign	osc_thrs[2] = 16'd40;
+    assign	osc_thrs[3] = 16'd1650;
+
+    assign	adc_pola[0] = 1'b1;
+    assign	adc_pola[1] = 1'b1;
+    assign	adc_pola[2] = 1'b1;
+    assign	adc_pola[3] = 1'b0;
+
     assign	adc_clk[0] = ADC_FCO;
     assign	adc_clk[1] = ADC_FCO;
     assign	adc_clk[2] = ADC_FCO;
-    
-    assign	adc_clk[3] = CON_B[0];
-    assign	adc_data[3] = CON_B[12:1];
+
+    assign	adc_clk[3] = ADC_FCO;
+/*    
+    assign	adc_clk[3] = CON_CCLK[0];
+    assign	adc_data[3] = CON_C[11:0];
+*/
+	adc_para adc_para_unit (
+		.lvds_dco(ADC_DCO),
+		.lvds_fco(ADC_FCO),
+		.para_data_ready(CON_CCLK[0]),
+ 		.para_data(CON_C[11:0]),
+		.adc_data(adc_data[3]));
+
 /* 
 	wire			adc_pll_clk;
@@ -147,5 +169,5 @@
 
 	test test_unit(
-		.inclk0(CLK_50MHz),
+		.clk(CLK_50MHz),
 		.tst_clk(tst_adc_clk),
 		.tst_data(tst_adc_data));
@@ -168,20 +190,23 @@
 */
 
-	adc_lvds adc_lvds_unit (
+	adc_lvds #(
+		.size(3),
+		.width(12)) adc_lvds_unit (
 		.lvds_dco(ADC_DCO),
 //		.lvds_dco(adc_pll_clk),
 		.lvds_fco(ADC_FCO),
 		.lvds_d(ADC_D),
-		.adc_db(adc_data[2]),
-		.adc_dc(adc_data[1]),
-		.adc_dd(adc_data[0]));
+		.adc_data({	adc_data[0],
+					adc_data[1],
+					adc_data[2]}));
  
 	genvar i;
 	generate
-		for (i = 2; i < 4; i = i + 1)
+		for (i = 1; i < 4; i = i + 1)
 		begin : MCA_CHAIN
 			adc_fifo adc_fifo_unit (
 				.adc_clk(adc_clk[i]),
 				.adc_data(adc_data[i]),
+				.polarity(adc_pola[i]),
 				.clk(CLK_50MHz),
 				.ready(adc_data_ready[i]),
@@ -203,6 +228,6 @@
 				.reset(hst_reset[i]),
 				.data_ready(adc_data_ready[i]),
-//				.data(raw_data[i]),
-				.data(uwt_data[i]),
+				.data(raw_data[i]),
+//				.data(uwt_data[i]),
 				.address(hst_addr[i]),
 				.q(hst_q[i]));
@@ -222,5 +247,5 @@
 				.raw_data(raw_data[i]),
 				.uwt_data(uwt_data[i]),
-				.threshold(16'd40),
+				.threshold(osc_thrs[i]),
 				.address(osc_addr[i]),
 				.start_address(osc_start_addr[i]),
Index: /trunk/MultiChannelUSB/adc_lvds.v
===================================================================
--- /trunk/MultiChannelUSB/adc_lvds.v	(revision 62)
+++ /trunk/MultiChannelUSB/adc_lvds.v	(revision 63)
@@ -1,16 +1,23 @@
 module adc_lvds
+	#(
+		parameter	size	=	3, // number of channels
+		parameter	width	=	12 // channel resolution
+	)
 	(
-		input	wire			lvds_dco,
-		input	wire			lvds_fco,
- 		input	wire	[2:0]	lvds_d,
+		input	wire						lvds_dco,
+		input	wire						lvds_fco,
+ 		input	wire	[2:0]				lvds_d,
 
-		output	reg		[11:0]	adc_db,
-		output	reg		[11:0]	adc_dc,
-		output	reg		[11:0]	adc_dd
+		output	wire	[size*width-1:0]	adc_data
 	);
 
-	wire 	[2:0]	int_data_h, int_data_l;
-	reg 	[11:0]	int_data_next [2:0];
-	reg 	[11:0]	int_data_reg [2:0];
+	wire 	[size-1:0]	int_data_h, int_data_l;
+	reg 	[width-1:0]	int_data_next [size-1:0];
+	reg 	[width-1:0]	int_data_reg [size-1:0];
+
+	reg 	[width-1:0]	int_adc_data [size-1:0];
+
+	integer i;
+	genvar j;
 
 	altddio_in #(
@@ -18,5 +25,5 @@
 		.invert_input_clocks("ON"),
 		.lpm_type("altddio_in"),
-		.width(3)) altddio_in_unit (
+		.width(size)) altddio_in_unit (
 		.datain(lvds_d),
 		.inclock(lvds_dco),
@@ -31,22 +38,32 @@
 	always @ (posedge lvds_dco)
 	begin
-		int_data_reg[0] <= int_data_next[0];
-		int_data_reg[1] <= int_data_next[1];
-		int_data_reg[2] <= int_data_next[2];		
+		for (i = 0; i < size; i = i + 1)
+		begin
+			int_data_reg[i] <= int_data_next[i];
+		end
 	end
 
 	always @ (posedge lvds_fco)
 	begin
-		adc_db <= int_data_next[0];
-		adc_dc <= int_data_next[1];
-		adc_dd <= int_data_next[2];
+		for (i = 0; i < size; i = i + 1)
+		begin
+			int_adc_data[i] <= int_data_next[i];
+		end
 	end
 
 	always @*
 	begin
-		int_data_next[0] = {int_data_reg[0][9:0], int_data_l[0], int_data_h[0]};
-		int_data_next[1] = {int_data_reg[1][9:0], int_data_l[1], int_data_h[1]};
-		int_data_next[2] = {int_data_reg[2][9:0], int_data_l[2], int_data_h[2]};
+		for (i = 0; i < size; i = i + 1)
+		begin
+			int_data_next[i] = {int_data_reg[i][9:0], int_data_l[i], int_data_h[i]};
+		end
 	end
 
+	generate
+		for (j = 1; j < size; j = j + 1)
+		begin : ADC_LVDS_OUTPUT
+			assign adc_data[j*width+width-1:j*width] = int_adc_data[j];
+		end
+	endgenerate
+
 endmodule