Index: /trunk/MultiChannelUSB/Paella.v
===================================================================
--- /trunk/MultiChannelUSB/Paella.v	(revision 58)
+++ /trunk/MultiChannelUSB/Paella.v	(revision 59)
@@ -66,14 +66,9 @@
 	assign	USB_PA6		=	~usb_pktend;
 
-	reg				led_reg;	
-	assign	LED			=	led_reg;
-
 	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
-	wire			usb_fifo_aclr;
-	reg				usb_fifo_tx_wrreq;
-	reg				usb_fifo_rx_rdreq;
-	wire			usb_fifo_tx_full, usb_fifo_rx_empty;
-	reg		[7:0]	usb_fifo_tx_data;
-	wire	[7:0]	usb_fifo_rx_data;
+	wire			usb_aclr;
+	wire			usb_tx_wrreq, usb_rx_rdreq;
+	wire			usb_tx_full, usb_rx_empty;
+	wire	[7:0]	usb_tx_data, usb_rx_data;
 	wire	[1:0]	usb_addr;
 
@@ -81,5 +76,5 @@
 	assign	USB_SLWR = ~usb_wrreq;
 
-	usb_fifo usb_fifo_unit
+	usb_fifo usb_unit
 	(
 		.usb_clk(USB_IFCLK),
@@ -94,18 +89,15 @@
 
 		.clk(CLK_50MHz),
-		.aclr(usb_fifo_aclr),
-
-		.tx_full(usb_fifo_tx_full),
-		.tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
-		.tx_data(usb_fifo_tx_data),
-
-		.rx_empty(usb_fifo_rx_empty),
-		.rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
-		.rx_q(usb_fifo_rx_data)
+		.aclr(usb_aclr),
+
+		.tx_full(usb_tx_full),
+		.tx_wrreq(usb_tx_wrreq),
+		.tx_data(usb_tx_data),
+
+		.rx_empty(usb_rx_empty),
+		.rx_rdreq(usb_rx_rdreq),
+		.rx_q(usb_rx_data)
 	);
 	
-	reg		[23:0]	rx_counter;
-	reg		[10:0]	tst_counter;	
-
 	reg 			ana_reset [3:0];
 	wire			ana_peak_ready [3:0];
@@ -113,8 +105,7 @@
 
 	reg 			osc_reset [3:0];
+	reg 	[9:0]	osc_addr [3:0];
 	wire	[9:0]	osc_start_addr [3:0];
-	reg 	[9:0]	osc_addr [3:0];
 	wire	[15:0]	osc_q [3:0];
-	reg		[15:0]	osc_q_mux;
 
 	reg 			hst_reset [3:0];
@@ -122,15 +113,13 @@
 	wire	[23:0]	hst_q [3:0];
 
-	reg 			mux_reset, mux_type;
-	reg 	[1:0]	mux_chan, mux_byte, mux_max_byte;
-	reg 	[15:0]	mux_addr, mux_min_addr, mux_max_addr, mux_num_addr;
+	wire 			mux_reset, mux_type;
+	wire 	[1:0]	mux_chan, mux_byte;
+	wire 	[15:0]	mux_addr;
+	
 	reg		[7:0]	mux_q;
-
-	reg		[3:0]	state1, state2;
-	reg				adc_fifo_aclr;
+	reg 	[1:0]	mux_max_byte;
+	reg 	[15:0]	mux_min_addr, mux_max_addr;
 
 	wire			adc_clk [3:0];
-
-
 	wire			adc_data_ready [3:0];
 	wire 	[11:0]	adc_data [3:0];
@@ -146,23 +135,23 @@
     assign	adc_clk[3] = CON_B[0];
     assign	adc_data[3] = CON_B[12:1];
- 
+/* 
 	wire			adc_pll_clk;
 
-	wire			tst_adc_clk;
-	reg 	[11:0]	tst_adc_data;
-/*
-    assign	adc_clk[3] = tst_adc_clk;
-    assign	adc_data[3] = tst_adc_data;
-*/
-/*
 	adc_pll adc_pll_unit(
 		.inclk0(ADC_FCO),
 		.c0(adc_pll_clk));
 */
-
-	pll pll_unit(
+/*
+	wire			tst_adc_clk;
+	wire 	[11:0]	tst_adc_data;
+
+	test test_unit(
 		.inclk0(CLK_50MHz),
-		.c0(tst_adc_clk));
-
+		.tst_clk(tst_adc_clk),
+		.tst_data(tst_adc_data));
+
+    assign	adc_clk[3] = tst_adc_clk;
+    assign	adc_data[3] = tst_adc_data;
+*/
 /*
 	altserial_flash_loader #(
@@ -184,17 +173,16 @@
 		.lvds_fco(ADC_FCO),
 		.lvds_d(ADC_D),
-		.adc_db(adc_data[0]),
+		.adc_db(adc_data[2]),
 		.adc_dc(adc_data[1]),
-		.adc_dd(adc_data[2]));
+		.adc_dd(adc_data[0]));
  
 	genvar i;
 	generate
-		for (i = 0; i < 4; i = i + 1)
+		for (i = 2; i < 4; i = i + 1)
 		begin : MCA_CHAIN
 			adc_fifo adc_fifo_unit (
 				.adc_clk(adc_clk[i]),
 				.adc_data(adc_data[i]),
-				.aclr(adc_fifo_aclr),
-				.rdclk(CLK_50MHz),
+				.clk(CLK_50MHz),
 				.ready(adc_data_ready[i]),
 				.raw_data(raw_data[i]),
@@ -253,5 +241,5 @@
 		end
 
-		case({mux_type,mux_chan})
+		case({mux_type, mux_chan})
 			3'b000, 3'b001, 3'b010, 3'b011:
 			begin
@@ -260,5 +248,5 @@
 				mux_max_byte = 2'd1;	
 				mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
-				mux_num_addr = 16'd1023;
+				mux_max_addr = 16'd1023;
 			end
 
@@ -269,5 +257,5 @@
 				mux_max_byte = 2'd2;	
 				mux_min_addr = 16'd0;
-				mux_num_addr = 16'd4095;
+				mux_max_addr = 16'd4095;
 			end
 		endcase
@@ -276,11 +264,11 @@
 	always @*
 	begin
-		case ({mux_type,mux_byte})
-			5'b000: mux_q = osc_q[mux_chan][7:0];
-			5'b001: mux_q = osc_q[mux_chan][15:8];
-
-			5'b100: mux_q = hst_q[mux_chan][7:0];
-			5'b101: mux_q = hst_q[mux_chan][15:8];
-			5'b110: mux_q = hst_q[mux_chan][23:16];
+		case ({mux_type, mux_byte})
+			3'b000: mux_q = osc_q[mux_chan][7:0];
+			3'b001: mux_q = osc_q[mux_chan][15:8];
+
+			3'b100: mux_q = hst_q[mux_chan][7:0];
+			3'b101: mux_q = hst_q[mux_chan][15:8];
+			3'b110: mux_q = hst_q[mux_chan][23:16];
 
 			default: mux_q = 8'd0;
@@ -288,192 +276,22 @@
 	end
 
-
-	always @(posedge CLK_50MHz)
-	begin
-		if (~usb_fifo_rx_empty)
-		begin
-			led_reg <= 1'b0;
-			rx_counter <= 24'd0;
-		end
-		else
-		begin
-			if (&rx_counter)
-			begin
-				led_reg <= 1'b1;
-			end
-			else
-			begin
-				rx_counter <= rx_counter + 24'd1;
-			end
-		end
-
-		case(state1)
-			1:
-			begin
-				usb_fifo_rx_rdreq <= 1'b1;
-				usb_fifo_tx_wrreq <= 1'b0;
-				mux_type <= 1'b0;
-				mux_chan <= 2'd0;
-				mux_byte <= 2'd0;	
-				mux_reset <= 1'b0;
-				state1 <= 4'd2;
-			end
-
-			2: 
-			begin
-				if (~usb_fifo_rx_empty)
-				begin
-					case (usb_fifo_rx_data)
-						8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
-						begin
-							usb_fifo_rx_rdreq <= 1'b0;
-							mux_type <= usb_fifo_rx_data[4];
-							mux_chan <= usb_fifo_rx_data[1:0];
-							mux_reset <= 1'b1;
-							state1 <= 4'd1;
-						end
-
-						8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
-						begin
-							usb_fifo_rx_rdreq <= 1'b0;
-							mux_type <= usb_fifo_rx_data[4];
-							mux_chan <= usb_fifo_rx_data[1:0];
-							state1 <= 4'd3;
-						end
-
-						8'h30:
-						begin
-							usb_fifo_rx_rdreq <= 1'b0;
-							state1 <= 4'd1;
-						end
-
-						8'h31:
-						begin
-							usb_fifo_rx_rdreq <= 1'b0;
-							tst_counter <= 11'd0;	
-							state1 <= 4'd6;
-						end
-					endcase
-				end
-			end
-			// mux transfer
-			3:
-			begin
-				mux_addr <= mux_min_addr;
-				mux_max_addr <= mux_min_addr + mux_num_addr;
-				mux_byte <= 2'd0;	
-				state1 <= 4'd4;
-			end
-	
-			4:
-			begin
-				usb_fifo_tx_wrreq <= 1'b0;
-				state1 <= 4'd5;
-			end
-
-			5:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_data <= mux_q;
-					usb_fifo_tx_wrreq <= 1'b1;
-					if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
-					begin
-						state1 <= 4'd1;
-					end
-					else
-					begin
-						state1 <= 4'd4;
-						if (mux_byte == mux_max_byte)
-						begin
-							mux_addr <= mux_addr + 16'd1;
-							mux_byte <= 2'd0;
-						end
-						else
-						begin
-							mux_byte <= mux_byte + 2'd1;
-						end
-					end
-				end
-			end
-
-			// tst transfer
-			6:
-			begin
-				usb_fifo_tx_data <= tst_counter;
-				usb_fifo_tx_wrreq <= 1'b1;
-				tst_counter <= tst_counter + 11'd1;
-				state1 <= 4'd8;
-			end
-			7:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_data <= tst_counter;
-					if (tst_counter == 11'd0)
-					begin
-						state1 <= 4'd9;
-					end
-					else
-					begin
-						tst_counter <= tst_counter + 11'd1;
-					end
-				end
-			end
-			8:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_wrreq <= 1'b0;
-					state1 <= 4'd1;
-				end
-			end
-						
-			default:
-			begin
-				state1 <= 4'd1;
-			end
-		endcase
-	end
-
-	always @ (posedge tst_adc_clk)
-	begin
-		case (state2)
-			1: 
-			begin
-				tst_adc_data <= 12'd0;
-				state2 <= 4'd2;
-			end
-			
-			2:
-			begin
-				tst_adc_data <= 12'd1024;
-				state2 <= 4'd3;
-			end
-
-			3:
-			begin
-				tst_adc_data <= 12'd2048;
-				state2 <= 4'd4;
-			end
-
-			4:
-			begin
-				tst_adc_data <= 12'd3072;
-				state2 <= 4'd5;
-			end
-
-			5:
-			begin
-				tst_adc_data <= 12'd4095;
-				state2 <= 4'd1;
-			end
-
-			default:
-			begin
-				state2 <= 4'd1;
-			end
-		endcase
-	end
+	control control_unit (
+		.clk(CLK_50MHz),
+		.rx_empty(usb_rx_empty),
+		.tx_full(usb_tx_full),
+		.rx_data(usb_rx_data),
+		.mux_max_byte(mux_max_byte),
+		.mux_min_addr(mux_min_addr),
+		.mux_max_addr(mux_max_addr),
+		.mux_q(mux_q),
+		.mux_reset(mux_reset),
+		.mux_type(mux_type),
+		.mux_chan(mux_chan),
+		.mux_byte(mux_byte),
+		.mux_addr(mux_addr),
+		.rx_rdreq(usb_rx_rdreq),
+		.tx_wrreq(usb_tx_wrreq),
+		.tx_data(usb_tx_data),
+		.led(LED));
 
 endmodule
Index: /trunk/MultiChannelUSB/control.v
===================================================================
--- /trunk/MultiChannelUSB/control.v	(revision 59)
+++ /trunk/MultiChannelUSB/control.v	(revision 59)
@@ -0,0 +1,193 @@
+module control
+	(
+		input	wire			clk,
+		input	wire			rx_empty, tx_full,
+		input	wire	[7:0]	rx_data,
+		input	wire	[1:0]	mux_max_byte,
+		input	wire	[15:0]	mux_min_addr, mux_max_addr,
+		input	wire	[7:0]	mux_q,
+
+		output	wire			mux_reset,
+		output	wire			mux_type,
+		output	wire	[1:0]	mux_chan,
+		output	wire	[1:0]	mux_byte,
+		output	wire	[15:0]	mux_addr,
+		output	wire			rx_rdreq,
+		output	wire			tx_wrreq,
+		output	wire	[7:0]	tx_data,
+		output	wire			led
+	);
+
+	reg		[23:0]	rx_counter;
+	reg		[10:0]	tst_counter;	
+	reg 	[15:0]	int_addr, int_max_addr;
+
+	reg				int_rdreq, int_wrreq;
+	reg				int_type, int_reset;
+	reg		[1:0]	int_chan, int_byte, int_max_byte;
+	reg		[7:0]	int_data;
+	reg				int_led;
+
+
+	reg		[3:0]	state;
+
+	always @(posedge clk)
+	begin
+		if (~rx_empty)
+		begin
+			int_led <= 1'b0;
+			rx_counter <= 24'd0;
+		end
+		else
+		begin
+			if (&rx_counter)
+			begin
+				int_led <= 1'b1;
+			end
+			else
+			begin
+				rx_counter <= rx_counter + 24'd1;
+			end
+		end
+
+		case(state)
+			1:
+			begin
+				int_rdreq <= 1'b1;
+				int_wrreq <= 1'b0;
+				int_type <= 1'b0;
+				int_chan <= 2'd0;
+				int_byte <= 2'd0;	
+				int_reset <= 1'b0;
+				state <= 4'd2;
+			end
+
+			2: 
+			begin
+				if (~rx_empty)
+				begin
+					case (rx_data)
+						8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
+						begin
+							int_rdreq <= 1'b0;
+							int_type <= rx_data[4];
+							int_chan <= rx_data[1:0];
+							int_reset <= 1'b1;
+							state <= 4'd1;
+						end
+
+						8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
+						begin
+							int_rdreq <= 1'b0;
+							int_type <= rx_data[4];
+							int_chan <= rx_data[1:0];
+							state <= 4'd3;
+						end
+
+						8'h30:
+						begin
+							int_rdreq <= 1'b0;
+							state <= 4'd1;
+						end
+
+						8'h31:
+						begin
+							int_rdreq <= 1'b0;
+							tst_counter <= 11'd0;	
+							state <= 4'd6;
+						end
+					endcase
+				end
+			end
+			// mux transfer
+			3:
+			begin
+				int_addr <= mux_min_addr;
+				int_max_addr <= mux_min_addr + mux_max_addr;
+				int_max_byte <= mux_max_byte;
+				int_byte <= 2'd0;	
+				state <= 4'd4;
+			end
+	
+			4:
+			begin
+				int_wrreq <= 1'b0;
+				state <= 4'd5;
+			end
+
+			5:
+			begin
+				if (~tx_full)
+				begin
+					int_data <= mux_q;
+					int_wrreq <= 1'b1;
+					if ((int_byte == int_max_byte) && (int_addr == int_max_addr))
+					begin
+						state <= 4'd1;
+					end
+					else
+					begin
+						state <= 4'd4;
+						if (int_byte == int_max_byte)
+						begin
+							int_addr <= int_addr + 16'd1;
+							int_byte <= 2'd0;
+						end
+						else
+						begin
+							int_byte <= int_byte + 2'd1;
+						end
+					end
+				end
+			end
+
+			// tst transfer
+			6:
+			begin
+				int_data <= tst_counter;
+				int_wrreq <= 1'b1;
+				tst_counter <= tst_counter + 11'd1;
+				state <= 4'd8;
+			end
+			7:
+			begin
+				if (~tx_full)
+				begin
+					int_data <= tst_counter;
+					if (tst_counter == 11'd0)
+					begin
+						state <= 4'd9;
+					end
+					else
+					begin
+						tst_counter <= tst_counter + 11'd1;
+					end
+				end
+			end
+			8:
+			begin
+				if (~tx_full)
+				begin
+					int_wrreq <= 1'b0;
+					state <= 4'd1;
+				end
+			end
+						
+			default:
+			begin
+				state <= 4'd1;
+			end
+		endcase
+	end
+	
+	assign	mux_reset = int_reset;
+	assign	mux_type = int_type;
+	assign	mux_chan = int_chan;
+	assign	mux_byte = int_byte;
+	assign	mux_addr = int_addr;
+	assign	rx_rdreq = int_rdreq & (~rx_empty);
+	assign	tx_wrreq = int_wrreq & (~tx_full);
+	assign	tx_data = int_data;
+	assign	led = int_led;
+
+endmodule
Index: /trunk/MultiChannelUSB/test.v
===================================================================
--- /trunk/MultiChannelUSB/test.v	(revision 59)
+++ /trunk/MultiChannelUSB/test.v	(revision 59)
@@ -0,0 +1,59 @@
+module test
+	(
+		input	wire			clk,
+		output	wire			tst_clk,
+		output	wire	[11:0]	tst_data
+	);
+
+	wire			int_clk;
+	reg 	[11:0]	int_data;
+	reg		[2:0]	state;
+
+	test_pll test_pll_unit(
+		.inclk0(clk),
+		.c0(int_clk));
+
+	always @(posedge int_clk)
+	begin
+		case (state)
+			0: 
+			begin
+				int_data <= 12'd0;
+				state <= 3'd1;
+			end
+			
+			1:
+			begin
+				int_data <= 12'd1024;
+				state <= 3'd2;
+			end
+
+			2:
+			begin
+				int_data <= 12'd2048;
+				state <= 3'd3;
+			end
+
+			3:
+			begin
+				int_data <= 12'd3072;
+				state <= 3'd4;
+			end
+
+			4:
+			begin
+				int_data <= 12'd4095;
+				state <= 3'd0;
+			end
+
+			default:
+			begin
+				state <= 3'd0;
+			end
+		endcase
+	end
+
+	assign	tst_clk = int_clk;
+	assign	tst_data = int_data;
+
+endmodule
Index: /trunk/MultiChannelUSB/test_pll.v
===================================================================
--- /trunk/MultiChannelUSB/test_pll.v	(revision 59)
+++ /trunk/MultiChannelUSB/test_pll.v	(revision 59)
@@ -0,0 +1,145 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: test_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module test_pll (
+	inclk0,
+	c0);
+
+	input	  inclk0;
+	output	  c0;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire4 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  sub_wire2 = inclk0;
+	wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+	altpll	altpll_component (
+				.inclk (sub_wire3),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 5,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 2,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+endmodule