Index: trunk/MultiChannelUSB/fifo.v =================================================================== --- trunk/MultiChannelUSB/fifo.v (revision 56) +++ (revision ) @@ -1,92 +1,0 @@ -// Listing 4.20 -module fifo - #( - parameter B=8, // number of bits in a word - W=4 // number of address bits - ) - ( - input wire clk, reset, - input wire rd, wr, - input wire [B-1:0] w_data, - output wire empty, full, - output wire [B-1:0] r_data - ); - - //signal declaration - reg [B-1:0] array_reg [2**W-1:0]; // register array - reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ; - reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ; - reg full_reg, empty_reg, full_next, empty_next; - wire wr_en; - - // body - // register file write operation - always @(posedge clk) - if (wr_en) - array_reg[w_ptr_reg] <= w_data; - // register file read operation - assign r_data = array_reg[r_ptr_reg]; - // write enabled only when FIFO is not full - assign wr_en = wr & ~full_reg; - - // fifo control logic - // register for read and write pointers - always @(posedge clk, posedge reset) - if (reset) - begin - w_ptr_reg <= 0; - r_ptr_reg <= 0; - full_reg <= 1'b0; - empty_reg <= 1'b1; - end - else - begin - w_ptr_reg <= w_ptr_next; - r_ptr_reg <= r_ptr_next; - full_reg <= full_next; - empty_reg <= empty_next; - end - - // next-state logic for read and write pointers - always @* - begin - // successive pointer values - w_ptr_succ = w_ptr_reg + 1; - r_ptr_succ = r_ptr_reg + 1; - // default: keep old values - w_ptr_next = w_ptr_reg; - r_ptr_next = r_ptr_reg; - full_next = full_reg; - empty_next = empty_reg; - case ({wr, rd}) - // 2'b00: no op - 2'b01: // read - if (~empty_reg) // not empty - begin - r_ptr_next = r_ptr_succ; - full_next = 1'b0; - if (r_ptr_succ==w_ptr_reg) - empty_next = 1'b1; - end - 2'b10: // write - if (~full_reg) // not full - begin - w_ptr_next = w_ptr_succ; - empty_next = 1'b0; - if (w_ptr_succ==r_ptr_reg) - full_next = 1'b1; - end - 2'b11: // write and read - begin - w_ptr_next = w_ptr_succ; - r_ptr_next = r_ptr_succ; - end - endcase - end - - // output - assign full = full_reg; - assign empty = empty_reg; - -endmodule - Index: trunk/MultiChannelUSB/fifo32x12.v =================================================================== --- trunk/MultiChannelUSB/fifo32x12.v (revision 56) +++ (revision ) @@ -1,104 +1,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo32x12.v -// Megafunction Name(s): -// dcfifo -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo32x12 ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - wrfull); - - input aclr; - input [11:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [11:0] q; - output rdempty; - output wrfull; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 aclr; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire sub_wire0; - wire sub_wire1; - wire [11:0] sub_wire2; - wire rdempty = sub_wire0; - wire wrfull = sub_wire1; - wire [11:0] q = sub_wire2[11:0]; - - dcfifo dcfifo_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrfull (sub_wire1), - .q (sub_wire2) - // synopsys translate_off - , - .rdfull (), - .rdusedw (), - .wrempty (), - .wrusedw () - // synopsys translate_on - ); - defparam - dcfifo_component.intended_device_family = "Cyclone III", - dcfifo_component.lpm_numwords = 32, - dcfifo_component.lpm_showahead = "ON", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 12, - dcfifo_component.lpm_widthu = 5, - dcfifo_component.overflow_checking = "ON", - dcfifo_component.underflow_checking = "ON", - dcfifo_component.use_eab = "OFF", - dcfifo_component.write_aclr_synch = "OFF"; - -endmodule Index: trunk/MultiChannelUSB/fifo32x14.v =================================================================== --- trunk/MultiChannelUSB/fifo32x14.v (revision 56) +++ (revision ) @@ -1,105 +1,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo32x14.v -// Megafunction Name(s): -// dcfifo -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo32x14 ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - wrfull); - - input aclr; - input [13:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [13:0] q; - output rdempty; - output wrfull; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 aclr; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire sub_wire0; - wire sub_wire1; - wire [13:0] sub_wire2; - wire rdempty = sub_wire0; - wire wrfull = sub_wire1; - wire [13:0] q = sub_wire2[13:0]; - - dcfifo dcfifo_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrfull (sub_wire1), - .q (sub_wire2) - // synopsys translate_off - , - .rdfull (), - .rdusedw (), - .wrempty (), - .wrusedw () - // synopsys translate_on - ); - defparam - dcfifo_component.intended_device_family = "Cyclone III", - dcfifo_component.lpm_numwords = 32, - dcfifo_component.lpm_showahead = "ON", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 14, - dcfifo_component.lpm_widthu = 5, - dcfifo_component.overflow_checking = "ON", - dcfifo_component.underflow_checking = "ON", - dcfifo_component.use_eab = "OFF", - dcfifo_component.write_aclr_synch = "OFF"; - - -endmodule Index: trunk/MultiChannelUSB/fifo32x8.v =================================================================== --- trunk/MultiChannelUSB/fifo32x8.v (revision 56) +++ (revision ) @@ -1,104 +1,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: dcfifo - -// ============================================================ -// File Name: fifo32x8.v -// Megafunction Name(s): -// dcfifo -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo32x8 ( - aclr, - data, - rdclk, - rdreq, - wrclk, - wrreq, - q, - rdempty, - wrfull); - - input aclr; - input [7:0] data; - input rdclk; - input rdreq; - input wrclk; - input wrreq; - output [7:0] q; - output rdempty; - output wrfull; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 aclr; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire sub_wire0; - wire sub_wire1; - wire [7:0] sub_wire2; - wire rdempty = sub_wire0; - wire wrfull = sub_wire1; - wire [7:0] q = sub_wire2[7:0]; - - dcfifo dcfifo_component ( - .wrclk (wrclk), - .rdreq (rdreq), - .aclr (aclr), - .rdclk (rdclk), - .wrreq (wrreq), - .data (data), - .rdempty (sub_wire0), - .wrfull (sub_wire1), - .q (sub_wire2) - // synopsys translate_off - , - .rdfull (), - .rdusedw (), - .wrempty (), - .wrusedw () - // synopsys translate_on - ); - defparam - dcfifo_component.intended_device_family = "Cyclone III", - dcfifo_component.lpm_numwords = 32, - dcfifo_component.lpm_showahead = "ON", - dcfifo_component.lpm_type = "dcfifo", - dcfifo_component.lpm_width = 8, - dcfifo_component.lpm_widthu = 5, - dcfifo_component.overflow_checking = "ON", - dcfifo_component.underflow_checking = "ON", - dcfifo_component.use_eab = "OFF", - dcfifo_component.write_aclr_synch = "OFF"; - -endmodule Index: trunk/MultiChannelUSB/ram1024x16.v =================================================================== --- trunk/MultiChannelUSB/ram1024x16.v (revision 56) +++ (revision ) @@ -1,110 +1,0 @@ -// megafunction wizard: %RAM: 2-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: ram1024x16.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module ram1024x16 ( - clock, - data, - rdaddress, - wraddress, - wren, - q); - - input clock; - input [15:0] data; - input [9:0] rdaddress; - input [9:0] wraddress; - input wren; - output [15:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 wren; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [15:0] sub_wire0; - wire [15:0] q = sub_wire0[15:0]; - - altsyncram altsyncram_component ( - .wren_a (wren), - .clock0 (clock), - .address_a (wraddress), - .address_b (rdaddress), - .data_a (data), - .q_b (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({16{1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 1024, - altsyncram_component.numwords_b = 1024, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", - altsyncram_component.widthad_a = 10, - altsyncram_component.widthad_b = 10, - altsyncram_component.width_a = 16, - altsyncram_component.width_b = 16, - altsyncram_component.width_byteena_a = 1; - - -endmodule Index: trunk/MultiChannelUSB/ram4096x24.v =================================================================== --- trunk/MultiChannelUSB/ram4096x24.v (revision 56) +++ (revision ) @@ -1,124 +1,0 @@ -// megafunction wizard: %RAM: 2-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: ram4096x24.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module ram4096x24 ( - address_a, - address_b, - clock, - data_a, - data_b, - wren_a, - wren_b, - q_a, - q_b); - - input [11:0] address_a; - input [11:0] address_b; - input clock; - input [23:0] data_a; - input [23:0] data_b; - input wren_a; - input wren_b; - output [23:0] q_a; - output [23:0] q_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 wren_a; - tri1 wren_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [23:0] sub_wire0; - wire [23:0] sub_wire1; - wire [23:0] q_a = sub_wire0[23:0]; - wire [23:0] q_b = sub_wire1[23:0]; - - altsyncram altsyncram_component ( - .wren_a (wren_a), - .clock0 (clock), - .wren_b (wren_b), - .address_a (address_a), - .address_b (address_b), - .data_a (data_a), - .data_b (data_b), - .q_a (sub_wire0), - .q_b (sub_wire1), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .eccstatus (), - .rden_a (1'b1), - .rden_b (1'b1)); - defparam - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.indata_reg_b = "CLOCK0", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 4096, - altsyncram_component.numwords_b = 4096, - altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_a = "UNREGISTERED", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", - altsyncram_component.widthad_a = 12, - altsyncram_component.widthad_b = 12, - altsyncram_component.width_a = 24, - altsyncram_component.width_b = 24, - altsyncram_component.width_byteena_a = 1, - altsyncram_component.width_byteena_b = 1, - altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; - - -endmodule Index: trunk/MultiChannelUSB/ram4096x32.v =================================================================== --- trunk/MultiChannelUSB/ram4096x32.v (revision 56) +++ (revision ) @@ -1,124 +1,0 @@ -// megafunction wizard: %RAM: 2-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: ram4096x32.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module ram4096x32 ( - address_a, - address_b, - clock, - data_a, - data_b, - wren_a, - wren_b, - q_a, - q_b); - - input [11:0] address_a; - input [11:0] address_b; - input clock; - input [31:0] data_a; - input [31:0] data_b; - input wren_a; - input wren_b; - output [31:0] q_a; - output [31:0] q_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 wren_a; - tri1 wren_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [31:0] sub_wire0; - wire [31:0] sub_wire1; - wire [31:0] q_a = sub_wire0[31:0]; - wire [31:0] q_b = sub_wire1[31:0]; - - altsyncram altsyncram_component ( - .wren_a (wren_a), - .clock0 (clock), - .wren_b (wren_b), - .address_a (address_a), - .address_b (address_b), - .data_a (data_a), - .data_b (data_b), - .q_a (sub_wire0), - .q_b (sub_wire1), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .eccstatus (), - .rden_a (1'b1), - .rden_b (1'b1)); - defparam - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.indata_reg_b = "CLOCK0", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 4096, - altsyncram_component.numwords_b = 4096, - altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_a = "UNREGISTERED", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", - altsyncram_component.widthad_a = 12, - altsyncram_component.widthad_b = 12, - altsyncram_component.width_a = 32, - altsyncram_component.width_b = 32, - altsyncram_component.width_byteena_a = 1, - altsyncram_component.width_byteena_b = 1, - altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; - - -endmodule