Index: /trunk/MultiChannelUSB/histogram.v
===================================================================
--- /trunk/MultiChannelUSB/histogram.v	(revision 51)
+++ /trunk/MultiChannelUSB/histogram.v	(revision 52)
@@ -48,5 +48,5 @@
 		.wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
 		.wren_a(wren_reg),
-		.clock0(~clk),
+		.clock0(clk),
 		.wren_b(1'b0),
 		.address_a(addr_wire),
Index: /trunk/MultiChannelUSB/oscilloscope.v
===================================================================
--- /trunk/MultiChannelUSB/oscilloscope.v	(revision 51)
+++ /trunk/MultiChannelUSB/oscilloscope.v	(revision 52)
@@ -47,5 +47,5 @@
 		.width_byteena_a(1)) osc_ram_unit(
 		.wren_a(wren_reg),
-		.clock0(~clk),
+		.clock0(clk),
 		.address_a(addr_reg),
 		.address_b(address),
@@ -117,6 +117,4 @@
 				addr_next = 10'd0;
 				data_next = 16'd0;
-				trig_next = 1'b0;
-				trig_addr_next = 10'd0;
 				counter_next = 10'd0;
 			end
@@ -184,6 +182,4 @@
 				addr_next = 10'd0;
 				data_next = 16'd0;
-				trig_next = 1'b0;
-				trig_addr_next = 10'd0;
 				counter_next = 10'd0;
 			end
@@ -193,5 +189,5 @@
 	// output logic
 	assign	q = q_wire;
-	assign	start_address = trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;
+	assign	start_address = trig_reg ? (trig_addr_reg ^ 10'h200) + 10'd1: addr_reg + 10'd1;
 
 endmodule