Index: /trunk/MultiChannelUSB/histogram.v =================================================================== --- /trunk/MultiChannelUSB/histogram.v (revision 50) +++ /trunk/MultiChannelUSB/histogram.v (revision 51) @@ -9,4 +9,5 @@ // signal declaration reg [3:0] state_reg, state_next; + reg flag_reg, flag_next; reg wren_reg, wren_next; reg [11:0] addr_reg, addr_next; @@ -14,4 +15,10 @@ wire [23:0] q_a_wire, q_b_wire; + + wire [11:0] addr_wire; + wire [23:0] data_wire; + + assign addr_wire = (flag_reg) ? data : addr_reg; + assign data_wire = (flag_reg) ? (q_a_wire + 24'd1) : data_reg; altsyncram #( @@ -39,28 +46,28 @@ .width_byteena_a(1), .width_byteena_b(1), - .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit ( - .wren_a (wren_reg), - .clock0 (~clk), - .wren_b (1'b0), - .address_a (addr_reg), - .address_b (address), - .data_a (data_reg), - .data_b (), - .q_a (q_a_wire), - .q_b (q_b_wire), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .eccstatus (), - .rden_a (1'b1), - .rden_b (1'b1)); + .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( + .wren_a(wren_reg), + .clock0(~clk), + .wren_b(1'b0), + .address_a(addr_wire), + .address_b(address), + .data_a(data_wire), + .data_b(), + .q_a(q_a_wire), + .q_b(q_b_wire), + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .eccstatus(), + .rden_a(1'b1), + .rden_b(1'b1)); // body @@ -69,12 +76,17 @@ if (reset) begin + flag_reg <= 1'b0; + wren_reg <= 1'b1; + addr_reg <= 12'd0; + data_reg <= 24'd0; state_reg <= 4'b1; end else begin - state_reg <= state_next; + flag_reg <= flag_next; wren_reg <= wren_next; addr_reg <= addr_next; data_reg <= data_next; + state_reg <= state_next; end end @@ -82,25 +94,28 @@ always @* begin - state_next = state_reg; + flag_next = flag_reg; wren_next = wren_reg; addr_next = addr_reg; data_next = data_reg; + state_next = state_reg; case (state_reg) - 0: ; // nothing to do - 1: + 0: begin - // start reset - wren_next = 1'b1; - addr_next = 0; - data_next = 0; - state_next = 4'd2; + // nothing to do + flag_next = 1'b0; + wren_next = 1'b0; + addr_next = 12'd0; + data_next = 24'd0; + state_next = 4'd0; end - - 2: + + 1: begin // write zeros if (&addr_reg) begin - state_next = 4'd3; + flag_next = 1'b1; + wren_next = 1'b0; + state_next = 4'd2; end else @@ -108,32 +123,35 @@ addr_next = addr_reg + 12'd1; end - end - - 3: + end + + 2: begin - // read - wren_next = 1'b0; - if (&data_reg) + if (data_ready) begin - state_next = 4'd0; - end - else if (data_ready) - begin - // set addr - addr_next = data; - state_next = 4'd4; + if (&q_a_wire) + begin + flag_next = 1'b0; + state_next = 4'd0; + end + else + begin + wren_next = 1'b1; + state_next = 4'd3; + end end end - 4: + 3: begin - // increment and write - wren_next = 1'b1; - data_next = q_a_wire + 24'd1; - state_next = 4'd3; + wren_next = 1'b0; + state_next = 4'd2; end default: begin + flag_next = 1'b0; + wren_next = 1'b0; + addr_next = 12'd0; + data_next = 24'd0; state_next = 4'd0; end Index: /trunk/MultiChannelUSB/oscilloscope.v =================================================================== --- /trunk/MultiChannelUSB/oscilloscope.v (revision 50) +++ /trunk/MultiChannelUSB/oscilloscope.v (revision 51) @@ -11,5 +11,5 @@ // signal declaration reg [3:0] state_reg, state_next; - + reg flag_reg, flag_next; reg wren_reg, wren_next; reg [9:0] addr_reg, addr_next; @@ -22,11 +22,51 @@ wire [15:0] q_wire; - ram1024x16 ram1024x16_unit ( - .clock(~clk), - .data(data_reg), - .rdaddress(address), - .wraddress(addr_reg), - .wren(wren_reg), - .q(q_wire)); + wire [15:0] data_wire; + + assign data_wire = (flag_reg) ? raw_data : data_reg; + + altsyncram #( + .address_reg_b("CLOCK0"), + .clock_enable_input_a("BYPASS"), + .clock_enable_input_b("BYPASS"), + .clock_enable_output_a("BYPASS"), + .clock_enable_output_b("BYPASS"), + .intended_device_family("Cyclone III"), + .lpm_type("altsyncram"), + .numwords_a(1024), + .numwords_b(1024), + .operation_mode("DUAL_PORT"), + .outdata_aclr_b("NONE"), + .outdata_reg_b("UNREGISTERED"), + .power_up_uninitialized("FALSE"), + .read_during_write_mode_mixed_ports("OLD_DATA"), + .widthad_a(10), + .widthad_b(10), + .width_a(16), + .width_b(16), + .width_byteena_a(1)) osc_ram_unit( + .wren_a(wren_reg), + .clock0(~clk), + .address_a(addr_reg), + .address_b(address), + .data_a(data_wire), + .q_b(q_wire), + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .data_b({16{1'b1}}), + .eccstatus(), + .q_a(), + .rden_a(1'b1), + .rden_b(1'b1), + .wren_b(1'b0)); // body @@ -36,8 +76,16 @@ begin state_reg <= 4'b1; + flag_reg <= 1'b0; + wren_reg <= 1'b1; + addr_reg <= 10'd0; + data_reg <= 16'd0; + trig_reg <= 1'b0; + trig_addr_reg <= 10'd0; + counter_reg <= 10'd0; end else begin state_reg <= state_next; + flag_reg <= flag_next; wren_reg <= wren_next; addr_reg <= addr_next; @@ -52,4 +100,5 @@ begin state_next = state_reg; + flag_next = flag_reg; wren_next = wren_reg; addr_next = addr_reg; @@ -60,24 +109,25 @@ case (state_reg) - 0: ; // nothing to do - 1: + 0: begin - // start reset - wren_next = 1'b1; - addr_next = 0; - data_next = 0; - trig_next = 0; - trig_addr_next = 0; - counter_next = 0; - state_next = 4'd2; + // nothing to do + state_next = 4'b0; + flag_next = 1'b0; + wren_next = 1'b0; + addr_next = 10'd0; + data_next = 16'd0; + trig_next = 1'b0; + trig_addr_next = 10'd0; + counter_next = 10'd0; end - 2: + 1: begin // write zeros if (&addr_reg) begin + flag_next = 1'b1; wren_next = 1'b0; - state_next = 4'd3; + state_next = 4'd2; end else @@ -87,15 +137,28 @@ end + 2: + begin + if (data_ready) + begin + wren_next = 1'b1; + state_next = 4'd3; + end + end + 3: begin + // stop write + wren_next = 1'b0; + addr_next = addr_reg + 10'd1; + if (&counter_reg) begin + flag_next = 1'b0; state_next = 4'd0; end - else if (data_ready) + else begin - // start write - wren_next = 1'b1; - data_next = raw_data; + state_next = 4'd2; + if ((~trig_reg) & (counter_reg == 10'd512) @@ -106,23 +169,22 @@ trig_addr_next = addr_reg; end - state_next = 4'd4; + + if (trig_reg | (counter_reg < 10'd512)) + begin + counter_next = counter_reg + 10'd1; + end end - end - - 4: - begin - // stop write - wren_next = 1'b0; - addr_next = addr_reg + 10'd1; - if (trig_reg | (counter_reg < 10'd512)) - begin - counter_next = counter_reg + 10'd1; - end - state_next = 4'd3; end default: begin - state_next = 4'd0; + state_next = 4'b0; + flag_next = 1'b0; + wren_next = 1'b0; + addr_next = 10'd0; + data_next = 16'd0; + trig_next = 1'b0; + trig_addr_next = 10'd0; + counter_next = 10'd0; end endcase