Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 47)
+++ trunk/MultiChannelUSB/Paella.v	(revision 48)
@@ -61,5 +61,4 @@
 	assign	RAM_DQB		=	8'bz;
 
-
 	assign	USB_PA2		=	~usb_rden;
 	assign	USB_PA4		=	usb_addr[0];
@@ -67,7 +66,5 @@
 	assign	USB_PA6		=	~usb_pktend;
 
-	reg		[31:0]	counter;	
 	reg				led_reg;	
-//	assign	LED			=	counter[24];
 	assign	LED			=	led_reg;
 
@@ -115,6 +112,4 @@
 	wire	[11:0]	ana_peak [3:0];
 
-	reg		[9:0]	osc_counter;	
-
 	reg 			osc_reset [3:0];
 	wire	[9:0]	osc_start_addr [3:0];
@@ -129,5 +124,5 @@
 	reg 			mux_reset, mux_type;
 	reg 	[1:0]	mux_chan, mux_byte, mux_max_byte;
-	reg 	[15:0]	mux_addr, mux_min_addr, mux_max_addr;
+	reg 	[15:0]	mux_addr, mux_min_addr, mux_max_addr, mux_num_addr;
 	reg		[7:0]	mux_q;
 
@@ -137,5 +132,4 @@
 	wire			adc_clk [3:0];
 
-//	reg 	[11:0]	adc_data;
 
 	wire			adc_data_ready [3:0];
@@ -149,11 +143,18 @@
     assign	adc_clk[1] = ADC_FCO;
     assign	adc_clk[2] = ADC_FCO;
+/*    
     assign	adc_clk[3] = CON_B[0];
     assign	adc_data[3] = CON_B[12:1];
-/* 
+*/ 
+	wire			tst_adc_clk;
+	reg 	[11:0]	tst_adc_data;
+
+    assign	adc_clk[3] = tst_adc_clk;
+    assign	adc_data[3] = tst_adc_data;
+
 	pll pll_unit(
 		.inclk0(CLK_50MHz),
-		.c0(adc_clk));
-*/
+		.c0(tst_adc_clk));
+
 /*
 	altserial_flash_loader #(
@@ -179,5 +180,5 @@
 	genvar i;
 	generate
-		for (i = 0; i < 4; i = i + 1)
+		for (i = 2; i < 4; i = i + 1)
 		begin : MCA_CHAIN
 			adc_fifo adc_fifo_unit (
@@ -228,11 +229,4 @@
 	endgenerate
 
-/*
-	always @ (posedge adc_clk)
-	begin
-		counter <= counter + 32'd1;
-	end
-*/
-
 	integer j;
 
@@ -254,5 +248,5 @@
 				mux_max_byte = 2'd1;	
 				mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
-				mux_max_addr = {6'd0, osc_start_addr[mux_chan]} + 16'd1023;
+				mux_num_addr = 16'd1023;
 			end
 
@@ -263,5 +257,5 @@
 				mux_max_byte = 2'd2;	
 				mux_min_addr = 16'd0;
-				mux_max_addr = 16'd4095;
+				mux_num_addr = 16'd4095;
 			end
 		endcase
@@ -355,4 +349,5 @@
 			begin
 				mux_addr <= mux_min_addr;
+				mux_max_addr <= mux_min_addr + mux_num_addr;
 				mux_byte <= 2'd0;	
 				state1 <= 4'd4;
@@ -409,5 +404,5 @@
 				begin
 					usb_fifo_tx_data <= tst_counter;
-					if (tst_counter == 11'd0) //(&osc_counter)
+					if (tst_counter == 11'd0)
 					begin
 						state1 <= 4'd9;
@@ -434,11 +429,11 @@
 		endcase
 	end
-/*
-	always @ (posedge adc_clk)
+
+	always @ (posedge tst_adc_clk)
 	begin
 		case (state2)
 			1: 
 			begin
-				adc_data <= 12'd0;
+				tst_adc_data <= 12'd0;
 				state2 <= 4'd2;
 			end
@@ -446,5 +441,5 @@
 			2:
 			begin
-				adc_data <= 12'd1024;
+				tst_adc_data <= 12'd1024;
 				state2 <= 4'd3;
 			end
@@ -452,5 +447,5 @@
 			3:
 			begin
-				adc_data <= 12'd2048;
+				tst_adc_data <= 12'd2048;
 				state2 <= 4'd4;
 			end
@@ -458,5 +453,5 @@
 			4:
 			begin
-				adc_data <= 12'd3072;
+				tst_adc_data <= 12'd3072;
 				state2 <= 4'd5;
 			end
@@ -464,5 +459,5 @@
 			5:
 			begin
-				adc_data <= 12'd4095;
+				tst_adc_data <= 12'd4095;
 				state2 <= 4'd1;
 			end
@@ -474,4 +469,4 @@
 		endcase
 	end
-*/
+
 endmodule