Index: trunk/MultiChannelUSB/histogram.v
===================================================================
--- trunk/MultiChannelUSB/histogram.v	(revision 46)
+++ trunk/MultiChannelUSB/histogram.v	(revision 47)
@@ -15,14 +15,52 @@
 	wire	[23:0]	q_a_wire, q_b_wire;
 
-	ram4096x24 ram4096x24_unit (
-		.address_a(addr_reg),
-		.address_b(address),
-		.clock(~clk),
-		.data_a(data_reg),
-		.data_b(),
-		.wren_a(wren_reg),
-		.wren_b(1'b0),
-		.q_a(q_a_wire),
-		.q_b(q_b_wire));
+	altsyncram #(
+		.address_reg_b("CLOCK0"),
+		.clock_enable_input_a("BYPASS"),
+		.clock_enable_input_b("BYPASS"),
+		.clock_enable_output_a("BYPASS"),
+		.clock_enable_output_b("BYPASS"),
+		.indata_reg_b("CLOCK0"),
+		.intended_device_family("Cyclone III"),
+		.lpm_type("altsyncram"),
+		.numwords_a(4096),
+		.numwords_b(4096),
+		.operation_mode("BIDIR_DUAL_PORT"),
+		.outdata_aclr_a("NONE"),
+		.outdata_aclr_b("NONE"),
+		.outdata_reg_a("UNREGISTERED"),
+		.outdata_reg_b("UNREGISTERED"),
+		.power_up_uninitialized("FALSE"),
+		.read_during_write_mode_mixed_ports("OLD_DATA"),
+		.widthad_a(12),
+		.widthad_b(12),
+		.width_a(24),
+		.width_b(24),
+		.width_byteena_a(1),
+		.width_byteena_b(1),
+		.wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit (
+		.wren_a (wren_reg),
+		.clock0 (~clk),
+		.wren_b (1'b0),
+		.address_a (addr_reg),
+		.address_b (address),
+		.data_a (data_reg),
+		.data_b (),
+		.q_a (q_a_wire),
+		.q_b (q_b_wire),
+		.aclr0 (1'b0),
+		.aclr1 (1'b0),
+		.addressstall_a (1'b0),
+		.addressstall_b (1'b0),
+		.byteena_a (1'b1),
+		.byteena_b (1'b1),
+		.clock1 (1'b1),
+		.clocken0 (1'b1),
+		.clocken1 (1'b1),
+		.clocken2 (1'b1),
+		.clocken3 (1'b1),
+		.eccstatus (),
+		.rden_a (1'b1),
+		.rden_b (1'b1));
 
 	// body