Index: trunk/MultiChannelUSB/Paella.qsf
===================================================================
--- trunk/MultiChannelUSB/Paella.qsf	(revision 44)
+++ trunk/MultiChannelUSB/Paella.qsf	(revision 45)
@@ -47,9 +47,7 @@
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
 set_global_assignment -name VERILOG_FILE adc_fifo.v
 set_global_assignment -name VERILOG_FILE adc_lvds.v
-set_global_assignment -name VERILOG_FILE fifo32x8.v
-set_global_assignment -name VERILOG_FILE fifo32x12.v
-set_global_assignment -name VERILOG_FILE fifo32x14.v
 set_global_assignment -name VERILOG_FILE analyser.v
 set_global_assignment -name VERILOG_FILE histogram.v
@@ -57,5 +55,5 @@
 set_global_assignment -name VERILOG_FILE pll.v
 set_global_assignment -name VERILOG_FILE ram1024x16.v
-set_global_assignment -name VERILOG_FILE ram4096x32.v
+set_global_assignment -name VERILOG_FILE ram4096x24.v
 set_global_assignment -name VERILOG_FILE usb_fifo.v
 set_global_assignment -name VERILOG_FILE uwt_bior31.v
Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 44)
+++ trunk/MultiChannelUSB/Paella.v	(revision 45)
@@ -111,41 +111,49 @@
 	reg		[10:0]	tst_counter;	
 
-	reg 			ana_reset [2:0];
-	wire			ana_peak_ready [2:0];
-	wire	[11:0]	ana_peak [2:0];
+	reg 			ana_reset [3:0];
+	wire			ana_peak_ready [3:0];
+	wire	[11:0]	ana_peak [3:0];
 
 	reg		[9:0]	osc_counter;	
-	reg 			osc_byte_num;
-
-	reg 			osc_reset_mux, osc_reset [2:0];
-	wire	[9:0]	osc_start_addr [2:0];
-	reg 	[9:0]	osc_start_addr_mux, osc_addr_mux, osc_addr [2:0];
-	wire	[15:0]	osc_q [2:0];
+
+	reg 			osc_reset [3:0];
+	wire	[9:0]	osc_start_addr [3:0];
+	reg 	[9:0]	osc_addr [3:0];
+	wire	[15:0]	osc_q [3:0];
 	reg		[15:0]	osc_q_mux;
 
-	reg 	[1:0]	hst_byte_num;
-
-	reg 			hst_reset_mux, hst_reset [2:0];
-	reg 	[11:0]	hst_addr_mux, hst_addr [2:0];
-	wire	[31:0]	hst_q [2:0];
-	reg		[31:0]	hst_q_mux;
-
-	reg		[3:0]	select, state1, state2;
+	reg 			hst_reset [3:0];
+	reg 	[11:0]	hst_addr [3:0];
+	wire	[23:0]	hst_q [3:0];
+
+	reg 			mux_reset, mux_type;
+	reg 	[1:0]	mux_chan, mux_byte, mux_max_byte;
+	reg 	[15:0]	mux_addr, mux_min_addr, mux_max_addr;
+	reg		[7:0]	mux_q;
+
+	reg		[3:0]	state1, state2;
 	reg				adc_fifo_aclr;
 
-	wire			adc_clk;
-
-	reg 	[11:0]	adc_data;
-
-	wire			adc_data_ready [2:0];
-	wire 	[11:0]	adc_lvds_data [2:0];
-
-    wire	[11:0]	raw_data [2:0];
-    wire	[11:0]	uwt_data [2:0];
-    wire	[1:0]	uwt_flag [2:0];
- 
+	wire			adc_clk [3:0];
+
+//	reg 	[11:0]	adc_data;
+
+	wire			adc_data_ready [3:0];
+	wire 	[11:0]	adc_data [3:0];
+
+    wire	[11:0]	raw_data [3:0];
+    wire	[11:0]	uwt_data [3:0];
+    wire	[1:0]	uwt_flag [3:0];
+    
+    assign	adc_clk[0] = ADC_FCO;
+    assign	adc_clk[1] = ADC_FCO;
+    assign	adc_clk[2] = ADC_FCO;
+    assign	adc_clk[3] = CON_B[0];
+    assign	adc_data[3] = CON_B[12:1];
+/* 
 	pll pll_unit(
 		.inclk0(CLK_50MHz),
 		.c0(adc_clk));
+*/
 /*
 	altserial_flash_loader #(
@@ -165,15 +173,15 @@
 		.lvds_fco(ADC_FCO),
 		.lvds_d(ADC_D),
-		.adc_db(adc_lvds_data[0]),
-		.adc_dc(adc_lvds_data[1]),
-		.adc_dd(adc_lvds_data[2]));
+		.adc_db(adc_data[0]),
+		.adc_dc(adc_data[1]),
+		.adc_dd(adc_data[2]));
  
 	genvar i;
 	generate
-		for (i = 0; i < 3; i = i + 1)
+		for (i = 0; i < 4; i = i + 1)
 		begin : MCA_CHAIN
 			adc_fifo adc_fifo_unit (
-				.adc_clk(ADC_FCO),
-				.adc_data(adc_lvds_data[i]),
+				.adc_clk(adc_clk[i]),
+				.adc_data(adc_data[i]),
 				.aclr(adc_fifo_aclr),
 				.rdclk(CLK_50MHz),
@@ -229,51 +237,55 @@
 	always @*
 	begin
-		case(select)
-			4'h0:
-			begin
-				osc_reset[0] = osc_reset_mux;
-				osc_addr[0] = osc_addr_mux;
-				osc_q_mux = osc_q[0];
-				osc_start_addr_mux = osc_start_addr[0];
-				
-				hst_reset[0] = hst_reset_mux;
-				hst_addr[0] = hst_addr_mux;
-				hst_q_mux = hst_q[0];
-			end
-			4'h1:
-			begin
-				osc_reset[1] = osc_reset_mux;
-				osc_addr[1] = osc_addr_mux;
-				osc_q_mux = osc_q[1];
-				osc_start_addr_mux = osc_start_addr[1];
-				
-				hst_reset[1] = hst_reset_mux;
-				hst_addr[1] = hst_addr_mux;
-				hst_q_mux = hst_q[1];
-			end
-			4'h2:
-			begin
-				osc_reset[2] = osc_reset_mux;
-				osc_addr[2] = osc_addr_mux;
-				osc_q_mux = osc_q[2];
-				osc_start_addr_mux = osc_start_addr[2];
-				
-				hst_reset[2] = hst_reset_mux;
-				hst_addr[2] = hst_addr_mux;
-				hst_q_mux = hst_q[2];
-			end
-			default:
-			begin
-				osc_reset[0] = osc_reset_mux;
-				osc_addr[0] = osc_addr_mux;
-				osc_q_mux = osc_q[0];
-				osc_start_addr_mux = osc_start_addr[0];
-				
-				hst_reset[0] = hst_reset_mux;
-				hst_addr[0] = hst_addr_mux;
-				hst_q_mux = hst_q[0];
+		osc_reset[0] = 1'b0;
+		osc_addr[0] = 10'b0;
+		osc_reset[1] = 1'b0;
+		osc_addr[1] = 10'b0;
+		osc_reset[2] = 1'b0;
+		osc_addr[2] = 10'b0;
+		osc_reset[3] = 1'b0;
+		osc_addr[3] = 10'b0;
+		hst_reset[0] = 1'b0;
+		hst_addr[0] = 12'b0;
+		hst_reset[1] = 1'b0;
+		hst_addr[1] = 12'b0;
+		hst_reset[2] = 1'b0;
+		hst_addr[2] = 12'b0;
+		hst_reset[3] = 1'b0;
+		hst_addr[3] = 12'b0;
+		case({mux_type,mux_chan})
+			3'b000, 3'b001, 3'b010, 3'b011:
+			begin
+				osc_reset[mux_chan] = mux_reset;
+				osc_addr[mux_chan] = mux_addr[9:0];
+				mux_max_byte = 2'd1;	
+				mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
+				mux_max_addr = {6'd0, osc_start_addr[mux_chan]} + 16'd1023;
+			end
+
+			3'b100, 3'b101, 3'b110, 3'b111:
+			begin
+				hst_reset[mux_chan] = mux_reset;
+				hst_addr[mux_chan] = mux_addr[11:0];
+				mux_max_byte = 2'd2;	
+				mux_min_addr = 16'd0;
+				mux_max_addr = 16'd4095;
 			end
 		endcase
 	end
+	
+	always @*
+	begin
+		case ({mux_type,mux_byte})
+			5'b000: mux_q = osc_q[mux_chan][7:0];
+			5'b001: mux_q = osc_q[mux_chan][15:8];
+
+			5'b100: mux_q = hst_q[mux_chan][7:0];
+			5'b101: mux_q = hst_q[mux_chan][15:8];
+			5'b110: mux_q = hst_q[mux_chan][23:16];
+
+			default: mux_q = 8'd0;
+		endcase     
+	end
+
 
 	always @(posedge CLK_50MHz)
@@ -301,6 +313,8 @@
 				usb_fifo_rx_rdreq <= 1'b1;
 				usb_fifo_tx_wrreq <= 1'b0;
-				hst_reset_mux <= 1'b0;
-				osc_reset_mux <= 1'b0;
+				mux_type <= 1'b0;
+				mux_chan <= 2'd0;
+				mux_byte <= 2'd0;	
+				mux_reset <= 1'b0;
 				state1 <= 4'd2;
 			end
@@ -311,35 +325,21 @@
 				begin
 					case (usb_fifo_rx_data)
-						8'h40, 8'h41, 8'h42:
+						8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
 						begin
 							usb_fifo_rx_rdreq <= 1'b0;
-							hst_reset_mux <= 1'b1;
-							select <= usb_fifo_rx_data[3:0];
+							mux_type <= usb_fifo_rx_data[4];
+							mux_chan <= usb_fifo_rx_data[1:0];
+							mux_reset <= 1'b1;
 							state1 <= 4'd1;
 						end
-						8'h50, 8'h51, 8'h52:
+
+						8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
 						begin
 							usb_fifo_rx_rdreq <= 1'b0;
-							hst_addr_mux <= 12'd0;
-							hst_byte_num <= 2'd0;	
-							select <= usb_fifo_rx_data[3:0];
+							mux_type <= usb_fifo_rx_data[4];
+							mux_chan <= usb_fifo_rx_data[1:0];
 							state1 <= 4'd3;
 						end
-						8'h60, 8'h61, 8'h62:
-						begin
-							usb_fifo_rx_rdreq <= 1'b0;
-							osc_reset_mux <= 1'b1;
-							select <= usb_fifo_rx_data[3:0];
-							state1 <= 4'd1;
-						end
-						8'h70, 8'h71, 8'h72:
-						begin
-							usb_fifo_rx_rdreq <= 1'b0;
-							osc_addr_mux <= osc_start_addr_mux;
-							osc_counter <= 10'd0;
-							osc_byte_num <= 1'd0;	
-							select <= usb_fifo_rx_data[3:0];
-							state1 <= 4'd6;
-						end
+
 						8'h30:
 						begin
@@ -347,4 +347,5 @@
 							state1 <= 4'd1;
 						end
+
 						8'h31:
 						begin
@@ -356,38 +357,42 @@
 				end
 			end
-
-			// hst transfer
+			// mux transfer
 			3:
 			begin
-				usb_fifo_tx_data <= hst_q_mux[7:0];
+				mux_addr <= mux_min_addr;
+				mux_byte <= 2'd0;	
+				state1 <= 4'd4;
+			end
+			4:
+			begin
+				usb_fifo_tx_data <= mux_q;
 				usb_fifo_tx_wrreq <= 1'b1;
-				hst_byte_num <= 2'd1;
-				state1 <= 4'd4;
-			end
-			4:
+				mux_byte <= 2'd1;
+				state1 <= 4'd5;
+			end
+			5:
 			begin
 				if (~usb_fifo_tx_full)
 				begin
-					case (hst_byte_num)
-						2'd0: usb_fifo_tx_data <= hst_q_mux[7:0];
-						2'd1: usb_fifo_tx_data <= hst_q_mux[15:8];
-						2'd2: usb_fifo_tx_data <= hst_q_mux[23:16];
-						2'd3: usb_fifo_tx_data <= hst_q_mux[31:24];
-					endcase
-					if ((&hst_byte_num) & (&hst_addr_mux))
+					usb_fifo_tx_data <= mux_q;
+					if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
 					begin
-						state1 <= 4'd5;
+						state1 <= 4'd6;
 					end
 					else
 					begin
-						if (&hst_byte_num)
-						begin
-							hst_addr_mux <= hst_addr_mux + 12'd1;
-						end
-						hst_byte_num <= hst_byte_num + 2'd1;
+						if (mux_byte == mux_max_byte)
+						begin
+							mux_addr <= mux_addr + 16'd1;
+							mux_byte <= 2'd0;
+						end
+						else
+						begin
+							mux_byte <= mux_byte + 2'd1;
+						end
 					end
 				end
 			end
-			5:
+			6:
 			begin
 				if (~usb_fifo_tx_full)
@@ -397,53 +402,13 @@
 				end
 			end
-
-			// osc transfer
-			6:
-			begin
-				usb_fifo_tx_data <= osc_q_mux[7:0];
-				usb_fifo_tx_wrreq <= 1'b1;
-				osc_byte_num <= 1'd1;
-				state1 <= 4'd7;
-			end
+			// tst transfer
 			7:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					case (osc_byte_num)
-						1'd0: usb_fifo_tx_data <= osc_q_mux[7:0];
-						1'd1: usb_fifo_tx_data <= osc_q_mux[15:8];
-					endcase
-					if ((&osc_byte_num) & (&osc_counter))
-					begin
-						state1 <= 4'd8;
-					end
-					else
-					begin
-						if (&osc_byte_num)
-						begin
-							osc_addr_mux <= osc_addr_mux + 10'd1;
-							osc_counter <= osc_counter + 10'd1;
-						end
-						osc_byte_num <= osc_byte_num + 1'd1;
-					end
-				end
-			end
-			8:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_wrreq <= 1'b0;
-					state1 <= 4'd1;
-				end
-			end
-			// tst transfer
-			9:
 			begin
 				usb_fifo_tx_data <= tst_counter;
 				usb_fifo_tx_wrreq <= 1'b1;
 				tst_counter <= tst_counter + 11'd1;
-				state1 <= 4'd10;
-			end
-			10:
+				state1 <= 4'd8;
+			end
+			8:
 			begin
 				if (~usb_fifo_tx_full)
@@ -452,5 +417,5 @@
 					if (tst_counter == 11'd0) //(&osc_counter)
 					begin
-						state1 <= 4'd11;
+						state1 <= 4'd9;
 					end
 					else
@@ -460,5 +425,5 @@
 				end
 			end
-			11:
+			9:
 			begin
 				if (~usb_fifo_tx_full)
@@ -475,5 +440,5 @@
 		endcase
 	end
-
+/*
 	always @ (posedge adc_clk)
 	begin
@@ -515,4 +480,4 @@
 		endcase
 	end
-
+*/
 endmodule
Index: trunk/MultiChannelUSB/adc_fifo.v
===================================================================
--- trunk/MultiChannelUSB/adc_fifo.v	(revision 44)
+++ trunk/MultiChannelUSB/adc_fifo.v	(revision 45)
@@ -47,6 +47,17 @@
 		.flag(uwt_flag3));
 
-
-	fifo32x12 fifo0 (
+	dcfifo #(
+		.intended_device_family("Cyclone III"),
+		.lpm_numwords(16),
+		.lpm_showahead("ON"),
+		.lpm_type("dcfifo"),
+		.lpm_width(12),
+		.lpm_widthu(4),
+		.rdsync_delaypipe(4),
+		.wrsync_delaypipe(4),
+		.overflow_checking("ON"),
+		.underflow_checking("ON"),
+		.use_eab("OFF"),
+		.write_aclr_synch("OFF")) fifo_raw (
 		.aclr(aclr),
 		.data(adc_data),
@@ -57,7 +68,23 @@
 		.q(raw_data),
 		.rdempty(int_rdempty),
-		.wrfull(wrfull[0]));
+		.wrfull(wrfull[0]),
+		.rdfull(),
+		.rdusedw(),
+		.wrempty(),
+		.wrusedw());
 
-	fifo32x14 fifo1 (
+	dcfifo #(
+		.intended_device_family("Cyclone III"),
+		.lpm_numwords(16),
+		.lpm_showahead("ON"),
+		.lpm_type("dcfifo"),
+		.lpm_width(14),
+		.lpm_widthu(4),
+		.rdsync_delaypipe(4),
+		.wrsync_delaypipe(4),
+		.overflow_checking("ON"),
+		.underflow_checking("ON"),
+		.use_eab("OFF"),
+		.write_aclr_synch("OFF")) fifo_uwt (
 		.aclr(aclr),
 		.data({uwt_flag3, uwt_peak3[11:0]}),
@@ -68,5 +95,9 @@
 		.q(uwt_data),
 		.rdempty(),
-		.wrfull(wrfull[1]));
+		.wrfull(wrfull[1]),
+		.rdfull(),
+		.rdusedw(),
+		.wrempty(),
+		.wrusedw());
 
 	always @ (posedge rdclk)
Index: trunk/MultiChannelUSB/analyser.v
===================================================================
--- trunk/MultiChannelUSB/analyser.v	(revision 44)
+++ trunk/MultiChannelUSB/analyser.v	(revision 45)
@@ -68,5 +68,5 @@
 					if (&counter_reg)
 					begin
-						state_next <= 2'd1;
+						state_next = 2'd1;
 					end
                 end
@@ -80,5 +80,5 @@
 					if (&counter_reg)
 					begin
-						state_next <= 2'd2;
+						state_next = 2'd2;
 					end
                 end
Index: trunk/MultiChannelUSB/histogram.v
===================================================================
--- trunk/MultiChannelUSB/histogram.v	(revision 44)
+++ trunk/MultiChannelUSB/histogram.v	(revision 45)
@@ -4,5 +4,5 @@
 		input	wire			data_ready,
 		input	wire	[11:0]  data, address,
-		output	wire	[31:0]  q
+		output	wire	[23:0]  q
 	);
 	
@@ -11,9 +11,9 @@
 	reg				wren_reg, wren_next;
 	reg		[11:0]	addr_reg, addr_next;
-	reg		[31:0]	data_reg, data_next;
+	reg		[23:0]	data_reg, data_next;
 
-	wire	[31:0]	q_a_wire, q_b_wire;
+	wire	[23:0]	q_a_wire, q_b_wire;
 
-	ram4096x32 ram4096x32_unit (
+	ram4096x24 ram4096x24_unit (
 		.address_a(addr_reg),
 		.address_b(address),
@@ -92,5 +92,5 @@
 				// increment and write
 				wren_next = 1'b1;
-				data_next = q_a_wire + 32'd1;
+				data_next = q_a_wire + 24'd1;
 				state_next = 4'd3;
 			end
@@ -104,4 +104,4 @@
 
 	// output logic
-	assign	q			=	q_b_wire;
+	assign	q = q_b_wire;
 endmodule
Index: trunk/MultiChannelUSB/oscilloscope.v
===================================================================
--- trunk/MultiChannelUSB/oscilloscope.v	(revision 44)
+++ trunk/MultiChannelUSB/oscilloscope.v	(revision 45)
@@ -130,6 +130,6 @@
 
 	// output logic
-	assign	q				=	q_wire;
-	assign	start_address	=	trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;
+	assign	q = q_wire;
+	assign	start_address = trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;
 
 endmodule
Index: trunk/MultiChannelUSB/ram4096x24.v
===================================================================
--- trunk/MultiChannelUSB/ram4096x24.v	(revision 45)
+++ trunk/MultiChannelUSB/ram4096x24.v	(revision 45)
@@ -0,0 +1,124 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4096x24.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram4096x24 (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[11:0]  address_a;
+	input	[11:0]  address_b;
+	input	  clock;
+	input	[23:0]  data_a;
+	input	[23:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[23:0]  q_a;
+	output	[23:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  wren_a;
+	tri1	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [23:0] sub_wire0;
+	wire [23:0] sub_wire1;
+	wire [23:0] q_a = sub_wire0[23:0];
+	wire [23:0] q_b = sub_wire1[23:0];
+
+	altsyncram	altsyncram_component (
+				.wren_a (wren_a),
+				.clock0 (clock),
+				.wren_b (wren_b),
+				.address_a (address_a),
+				.address_b (address_b),
+				.data_a (data_a),
+				.data_b (data_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 4096,
+		altsyncram_component.numwords_b = 4096,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
+		altsyncram_component.widthad_a = 12,
+		altsyncram_component.widthad_b = 12,
+		altsyncram_component.width_a = 24,
+		altsyncram_component.width_b = 24,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
Index: trunk/MultiChannelUSB/usb_fifo.v
===================================================================
--- trunk/MultiChannelUSB/usb_fifo.v	(revision 44)
+++ trunk/MultiChannelUSB/usb_fifo.v	(revision 45)
@@ -24,5 +24,17 @@
 	wire	[7:0]	int_tx_q;
 
-	fifo32x8 fifo_tx_unit (
+	dcfifo #(
+		.intended_device_family("Cyclone III"),
+		.lpm_numwords(16),
+		.lpm_showahead("ON"),
+		.lpm_type("dcfifo"),
+		.lpm_width(8),
+		.lpm_widthu(4),
+		.rdsync_delaypipe(4),
+		.wrsync_delaypipe(4),
+		.overflow_checking("ON"),
+		.underflow_checking("ON"),
+		.use_eab("OFF"),
+		.write_aclr_synch("OFF")) fifo_tx (
 		.aclr(aclr),
 		.data(tx_data),
@@ -33,7 +45,23 @@
 		.q(int_tx_q),
 		.rdempty(int_tx_empty),
-		.wrfull(tx_full));
+		.wrfull(tx_full),
+		.rdfull(),
+		.rdusedw(),
+		.wrempty(),
+		.wrusedw());
 
-	fifo32x8 fifo_rx_unit (
+	dcfifo #(
+		.intended_device_family("Cyclone III"),
+		.lpm_numwords(16),
+		.lpm_showahead("ON"),
+		.lpm_type("dcfifo"),
+		.lpm_width(8),
+		.lpm_widthu(4),
+		.rdsync_delaypipe(4),
+		.wrsync_delaypipe(4),
+		.overflow_checking("ON"),
+		.underflow_checking("ON"),
+		.use_eab("OFF"),
+		.write_aclr_synch("OFF")) fifo_rx (
 		.aclr(aclr),
 		.data(int_rx_data),
@@ -44,5 +72,9 @@
 		.q(rx_q),
 		.rdempty(rx_empty),
-		.wrfull(int_rx_full));
+		.wrfull(int_rx_full),
+		.rdfull(),
+		.rdusedw(),
+		.wrempty(),
+		.wrusedw());
 	
 	assign	rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);