Index: /trunk/MultiChannelUSB/Paella.dpf
===================================================================
--- /trunk/MultiChannelUSB/Paella.dpf	(revision 40)
+++ /trunk/MultiChannelUSB/Paella.dpf	(revision 41)
@@ -11,15 +11,15 @@
 		<pin name="ADC_FCO(n)" direction="Input" source="Assignments" diff_pair_node="ADC_FCO" >
 		</pin>
-		<pin name="ADC_DB" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_DB(n)" >
+		<pin name="ADC_D[0]" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_D[0](n)" >
 		</pin>
-		<pin name="ADC_DB(n)" direction="Input" source="Assignments" diff_pair_node="ADC_DB" >
+		<pin name="ADC_D[0](n)" direction="Input" source="Assignments" diff_pair_node="ADC_D[0]" >
 		</pin>
-		<pin name="ADC_DC" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_DC(n)" >
+		<pin name="ADC_D[1]" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_D[1](n)" >
 		</pin>
-		<pin name="ADC_DC(n)" direction="Input" source="Assignments" diff_pair_node="ADC_DC" >
+		<pin name="ADC_D[1](n)" direction="Input" source="Assignments" diff_pair_node="ADC_D[1]" >
 		</pin>
-		<pin name="ADC_DD" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_DD(n)" >
+		<pin name="ADC_D[2]" direction="Input" source="Hierarchy Database" diff_pair_node="ADC_D[2](n)" >
 		</pin>
-		<pin name="ADC_DD(n)" direction="Input" source="Assignments" diff_pair_node="ADC_DD" >
+		<pin name="ADC_D[2](n)" direction="Input" source="Assignments" diff_pair_node="ADC_D[2]" >
 		</pin>
 		<pin name="\GEN_ASMI_TYPE_2:asmi_inst~ALTERA_SDO" source="Pin Planner" >
Index: /trunk/MultiChannelUSB/Paella.qsf
===================================================================
--- /trunk/MultiChannelUSB/Paella.qsf	(revision 40)
+++ /trunk/MultiChannelUSB/Paella.qsf	(revision 41)
@@ -48,4 +48,5 @@
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name VERILOG_FILE adc_fifo.v
+set_global_assignment -name VERILOG_FILE adc_lvds.v
 set_global_assignment -name VERILOG_FILE fifo32x8.v
 set_global_assignment -name VERILOG_FILE fifo32x12.v
@@ -124,13 +125,11 @@
 set_location_assignment PIN_94 -to "ADC_FCO(n)"
 set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
-set_location_assignment PIN_98 -to ADC_DB
-set_location_assignment PIN_99 -to "ADC_DB(n)"
-set_instance_assignment -name IO_STANDARD LVDS -to ADC_DB
-set_location_assignment PIN_108 -to ADC_DC
-set_location_assignment PIN_109 -to "ADC_DC(n)"
-set_instance_assignment -name IO_STANDARD LVDS -to ADC_DC
-set_location_assignment PIN_119 -to ADC_DD
-set_location_assignment PIN_120 -to "ADC_DD(n)"
-set_instance_assignment -name IO_STANDARD LVDS -to ADC_DD
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0]
+set_location_assignment PIN_108 -to ADC_D[0]
+set_location_assignment PIN_109 -to "ADC_D[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1]
+set_location_assignment PIN_119 -to ADC_D[2]
+set_location_assignment PIN_120 -to "ADC_D[2](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2]
 set_location_assignment PIN_126 -to CON_B[0]
 set_location_assignment PIN_127 -to CON_B[1]
Index: /trunk/MultiChannelUSB/Paella.v
===================================================================
--- /trunk/MultiChannelUSB/Paella.v	(revision 40)
+++ /trunk/MultiChannelUSB/Paella.v	(revision 41)
@@ -13,7 +13,5 @@
 		input	wire			ADC_DCO,
 		input	wire			ADC_FCO,
-		input	wire			ADC_DB,
-		input	wire			ADC_DC,
-		input	wire			ADC_DD,
+		input	wire	[2:0]	ADC_D,
 
 		output	wire			USB_SLRD, 
@@ -133,5 +131,10 @@
 	reg				adc_data_ready;
 	wire			adc_clk;
+
 	reg 	[11:0]	adc_data;
+
+	wire			adc_lvds_clk;
+	wire 	[11:0]	adc_lvds_data [2:0];
+
     wire	[11:0]	raw_data;
     wire	[11:0]	uwt_data;
@@ -141,5 +144,5 @@
 		.inclk0(CLK_50MHz),
 		.c0(adc_clk));
-
+/*
 	altserial_flash_loader #(
 		.enable_shared_access("OFF"),
@@ -153,8 +156,17 @@
 		.scein(),
 		.sdoin());
+*/
+	adc_lvds adc_lvds_unit (
+		.lvds_dco(ADC_DCO),
+		.lvds_fco(ADC_FCO),
+		.lvds_d(ADC_D),
+		.adc_clk(adc_lvds_clk),
+		.adc_db(adc_lvds_data[0]),
+		.adc_dc(adc_lvds_data[1]),
+		.adc_dd(adc_lvds_data[2]));
 
 	adc_fifo adc_fifo_unit (
-		.adc_clk(adc_clk),
-		.adc_data(adc_data),
+		.adc_clk(adc_lvds_clk),
+		.adc_data(adc_lvds_data[1]),
 		.aclr(adc_fifo_aclr),
 		.rdclk(CLK_50MHz),
@@ -170,6 +182,5 @@
 		.data(raw_data),
 		.address(hst_addr),
-		.q(hst_q)
-	);
+		.q(hst_q));
 	
 	oscilloscope oscilloscope_unit (
@@ -182,6 +193,5 @@
 		.address(osc_addr),
 		.start_address(osc_start_addr),
-		.q(osc_q)
-	);
+		.q(osc_q));
 
 /*
Index: /trunk/MultiChannelUSB/adc_lvds.v
===================================================================
--- /trunk/MultiChannelUSB/adc_lvds.v	(revision 41)
+++ /trunk/MultiChannelUSB/adc_lvds.v	(revision 41)
@@ -0,0 +1,60 @@
+module adc_lvds
+	(
+		input	wire			lvds_dco,
+		input	wire			lvds_fco,
+ 		input	wire	[2:0]	lvds_d,
+
+		output	wire			adc_clk,
+		output	wire	[11:0]	adc_db,
+		output	wire	[11:0]	adc_dc,
+		output	wire	[11:0]	adc_dd
+	);
+
+
+	wire 	[2:0]	int_data_h, int_data_l;
+	reg 	[11:0]	int_data_sr [2:0];
+	reg 	[11:0]	int_data [2:0];
+	reg				int_fco;
+
+	integer			i;
+
+	altddio_in #(
+		.intended_device_family("Cyclone III"),
+		.invert_input_clocks("OFF"),
+		.lpm_type("altddio_in"),
+		.width(3)) altddio_in_unit (
+		.datain(lvds_d),
+		.inclock(lvds_dco),
+		.aclr(1'b0),
+		.dataout_h(int_data_h),
+		.dataout_l(int_data_l),
+		.aset(1'b0),
+		.inclocken(1'b1),
+		.sclr(1'b0),
+		.sset(1'b0));
+
+	always @ (posedge lvds_dco)
+	begin
+		for(i = 0; i < 3; i = i + 1)
+		begin
+			int_data_sr[i] <= {int_data_sr[i][9:0], int_data_h[i], int_data_l[i]};
+		end
+
+		// one clock delay for FCO
+		int_fco <= lvds_fco;
+		
+		if((lvds_fco) & (~int_fco))
+		begin
+			for(i = 0; i < 3; i = i + 1)
+			begin
+				int_data[i] <= {int_data_sr[i][9:0], int_data_h[i], int_data_l[i]};
+			end
+		end
+	end
+
+	assign	adc_clk = int_fco;
+	assign	adc_db = int_data[0];
+	assign	adc_dc = int_data[1];
+	assign	adc_dd = int_data[2];
+
+endmodule