Index: trunk/FirmwareFX2/Makefile =================================================================== --- trunk/FirmwareFX2/Makefile (revision 4) +++ trunk/FirmwareFX2/Makefile (revision 4) @@ -0,0 +1,90 @@ +#----------------------------------------------------------------------------- +# Makefile for usb_jtag FX2 firmware +#----------------------------------------------------------------------------- +# Copyright 2007 Kolja Waschk, ixo.de +#----------------------------------------------------------------------------- +# This code is part of usbjtag. usbjtag is free software; you can redistribute +# it and/or modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of the License, +# or (at your option) any later version. usbjtag is distributed in the hope +# that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. You should have received a +# copy of the GNU General Public License along with this program in the file +# COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +# St, Fifth Floor, Boston, MA 02110-1301 USA +#----------------------------------------------------------------------------- + +LIBDIR=fx2 +LIB=libfx2.lib + +ifeq (${HARDWARE},) + #HARDWARE=hw_basic + HARDWARE=hw_fynu +endif + +CC=sdcc +CFLAGS+=-mmcs51 --no-xinit-opt -I${LIBDIR} -D${HARDWARE} +CFLAGS+=--opt-code-size + +# added by bram +CFLAGS+=--stack-auto + + +AS=asx8051 +ASFLAGS+=-plosgff + +LDFLAGS=--code-loc 0x0000 --code-size 0x1800 +LDFLAGS+=--xram-loc 0x1800 --xram-size 0x0800 +LDFLAGS+=-Wl '-b USBDESCSEG = 0xE100' +LDFLAGS+=-L ${LIBDIR} + +%.rel : %.a51 + $(AS) $(ASFLAGS) $< + +%.rel : %.c + $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@ + +%.iic : %.hex + ./hex2bix -ir -f 0xC2 -m 0xF000 -c 0x1 -o $@ $< + +default: usbjtag.iic + +usbjtag.hex: vectors.rel spi.rel usbjtag.rel dscr.rel eeprom.rel ${HARDWARE}.rel startup.rel ${LIBDIR}/${LIB} + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $+ + packihx $@ > .tmp.hex + rm $@ + mv .tmp.hex $@ + +${LIBDIR}/${LIB}: + make -C ${LIBDIR} + +.PHONY: boot +boot: usbjtag.hex + -test -e /dev/usb_jtag && /sbin/fxload -D /dev/usb_jtag -I usbjtag.hex -t fx2 + -test -e /dev/tracii_xl2 && /sbin/fxload -D /dev/tracii_xl2 -I usbjtag.hex -t fx2 + -test -e /dev/xilinx_xpcu && /sbin/fxload -D /dev/xilinx_xpcu -I usbjtag.hex -t fx2 + +REF=/home/kawk/work/xilinx/xtern/xusbdfwu/xusbdfwu-1025.hex + +.PHONY: ref +ref: + -test -e /dev/usb_jtag && /sbin/fxload -D /dev/usb_jtag -I ${REF} -t fx2 + -test -e /dev/tracii_xl2 && /sbin/fxload -D /dev/tracii_xl2 -I ${REF} -t fx2 + -test -e /dev/xilinx_xpcu && /sbin/fxload -D /dev/xilinx_xpcu -I ${REF} -t fx2 + +dscr.rel: dscr.a51 +eeprom.rel: eeprom.c eeprom.h +usbjtag.rel: usbjtag.c hardware.h eeprom.h +${HARDWARE}.rel: ${HARDWARE}.c hardware.h + +.PHONY: clean distclean + +clean: + make -C ${LIBDIR} clean + rm -f *.lst *.asm *.lib *.sym *.rel *.mem *.map *.rst *.lnk *.ihx *.iic + +distclean: clean + + + Index: trunk/FirmwareFX2/copying.txt =================================================================== --- trunk/FirmwareFX2/copying.txt (revision 4) +++ trunk/FirmwareFX2/copying.txt (revision 4) @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Index: trunk/FirmwareFX2/dscr.a51 =================================================================== --- trunk/FirmwareFX2/dscr.a51 (revision 4) +++ trunk/FirmwareFX2/dscr.a51 (revision 4) @@ -0,0 +1,375 @@ +;;; -*- asm -*- +;;; +;;;----------------------------------------------------------------------------- +;;; USB Descriptor(s) +;;;----------------------------------------------------------------------------- +;;; Copyright 2005..2007 Kolja Waschk, ixo.de +;;; Modified by LAP for FPGA4U project, Jan 2007. lap.epfl.ch +;;;----------------------------------------------------------------------------- +;;; Code based on USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + + .module usb_descriptors + + VID = 0x09FB ; Changed by LAP to match Altera VID + PID = 0x6001 ; Changed by LAP to match Altera USBBlaster PID + VERSION = 0x0400 ; Product Version (4 indicates *BM device) + USB_VER = 0x0110 ; Support USB version 1.10 + USB_ATTR = 0x80 ; Bus powered, not self-powered, no remote wakeup + FTD_ATTR = 0x001C ; Set USB version, use version string, enable suspend PD + MAX_POWER = 75 ; need 2*75 mA max + + DSCR_DEVICE = 1 ; Descriptor type: Device + DSCR_CONFIG = 2 ; Descriptor type: Configuration + DSCR_STRING = 3 ; Descriptor type: String + DSCR_INTRFC = 4 ; Descriptor type: Interface + DSCR_ENDPNT = 5 ; Descriptor type: Endpoint + DSCR_DEVQUAL = 6 ; Descriptor type: Device Qualifier + + DSCR_DEVICE_LEN = 18 + DSCR_CONFIG_LEN = 9 + DSCR_INTRFC_LEN = 9 + DSCR_ENDPNT_LEN = 7 + DSCR_DEVQUAL_LEN = 10 + + ET_CONTROL = 0 ; Endpoint type: Control + ET_ISO = 1 ; Endpoint type: Isochronous + ET_BULK = 2 ; Endpoint type: Bulk + ET_INT = 3 ; Endpoint type: Interrupt + +;;; -------------------------------------------------------- +;;; external ram data +;;;-------------------------------------------------------- + + .area USBDESCSEG (XDATA) + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at high speed (480Mb/sec) +;;; ---------------------------------------------------------------- + + .even ; descriptors must be 2-byte aligned for SUDPTR{H,L} to work + + ;; The .even directive isn't really honored by the linker. Bummer! + ;; (There's no way to specify an alignment requirement for a given area, + ;; hence when they're concatenated together, even doesn't work.) + ;; + ;; We work around this by telling the linker to put USBDESCSEG + ;; at 0xE000 absolute. This means that the maximimum length of this + ;; segment is 480 bytes, leaving room for the two hash slots + ;; at 0xE1EO to 0xE1FF. + ;; Note from LAP: TODOOOOO + +_high_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE +_dscr_usbver:: + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 +_dscr_vidpidver:: + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice +_dscr_strorder:: + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + + .even +_high_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB (MSB) + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 12Mb/sec) + .db 0 ; bReserved + + .even +_high_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_high_speed_config_descr_end - _high_speed_config_descr) ; LSB + .db >(_high_speed_config_descr_end - _high_speed_config_descr) ; MSB + .db 2 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration +_dscr_attrpow:: + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 0.5 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (ep 1 IN) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (ep 2 OUT) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 1 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x06 ; bEndpointAddress (ep 6 OUT) + .db ET_BULK ; bmAttributes + .db 0x00 ; wMaxPacketSize (LSB) + .db 0x02 ; wMaxPacketSize (MSB) + .db 0x00 ; Polling interval + + ;; endpoint descriptor + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x88 ; bEndpointAddress (ep 8 IN) + .db ET_BULK ; bmAttributes + .db 0x00 ; wMaxPacketSize (LSB) + .db 0x02 ; wMaxPacketSize (MSB) + .db 0x00 ; Polling interval + +_high_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at full speed (12Mb/sec) +;;; ---------------------------------------------------------------- + + .even +_full_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (None) + .db 1 ; bNumConfigurations + +;;; describes the other speed (480Mb/sec) + .even +_full_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 480Mb/sec) + .db 0 ; bReserved + + .even +_full_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_full_speed_config_descr_end - _full_speed_config_descr) ; LSB + .db >(_full_speed_config_descr_end - _full_speed_config_descr) ; MSB + .db 2 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 0.5 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (ep 1 IN) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (ep 2 OUT) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 1 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x06 ; bEndpointAddress (ep 6 OUT) + .db ET_BULK ; bmAttributes + .db 0x40 ; wMaxPacketSize (LSB) + .db 0x00 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x88 ; bEndpointAddress (ep 8 IN) + .db ET_BULK ; bmAttributes + .db 0x40 ; wMaxPacketSize (LSB) + .db 0x00 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + +_full_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; string descriptors +;;; ---------------------------------------------------------------- + +_nstring_descriptors:: + .db (_string_descriptors_end - _string_descriptors) / 2 + +_string_descriptors:: + .db str0 + .db str1 + .db str2 + .db str3 +_string_descriptors_end: + + SI_NONE = 0 + ;; str0 contains the language ID's. + .even +_str0:: +str0: .db str0_end - str0 + .db DSCR_STRING + .db 0 + .db 0 + .db <0x0409 ; magic code for US English (LSB) + .db >0x0409 ; magic code for US English (MSB) +str0_end: + + SI_VENDOR = 1 + .even +_str1:: +str1: .db str1_end - str1 + .db DSCR_STRING + .db 'F, 0 ; 16-bit unicode + .db 'Y, 0 + .db 'N, 0 + .db 'U, 0 +str1_end: + + SI_PRODUCT = 2 + .even +_str2:: +str2: .db str2_end - str2 + .db DSCR_STRING + .db 'U, 0 + .db 'S, 0 + .db 'B, 0 + .db '-, 0 + .db 'B, 0 + .db 'l, 0 + .db 'a, 0 + .db 's, 0 + .db 't, 0 + .db 'e, 0 + .db 'r, 0 +str2_end: + + SI_SERIAL = 3 + .even +_str3:: +str3: .db str3_end - str3 + .db DSCR_STRING + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 +str3_end: + Index: trunk/FirmwareFX2/eeprom.c =================================================================== --- trunk/FirmwareFX2/eeprom.c (revision 4) +++ trunk/FirmwareFX2/eeprom.c (revision 4) @@ -0,0 +1,77 @@ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "eeprom.h" +#include "usb_descriptors.h" + +xdata unsigned char eeprom[128]; + +extern xdata char dscr_vidpidver[6]; +extern xdata char dscr_attrpow[2]; +extern xdata char dscr_usbver[2]; +extern xdata char dscr_strorder[4]; +extern xdata char str1[]; +extern xdata char str2[]; +extern xdata char str3[]; + +static unsigned char ee_ptr; +static unsigned short ee_cksum; + +void eeprom_append(unsigned char nb) +{ + unsigned char pree_ptr = ee_ptr & ~1; + if(pree_ptr != ee_ptr) + { + ee_cksum = ee_cksum ^((unsigned short)nb << 8); + ee_cksum = ee_cksum ^ eeprom[pree_ptr]; + ee_cksum = (ee_cksum << 1) | (ee_cksum >> 15); + }; + eeprom[ee_ptr++] = nb; +} + +void eeprom_init(void) +{ + char j,sofs; + ee_ptr = 0; + ee_cksum = 0xAAAA; + + eeprom_append(0x00); + eeprom_append(0x00); + for(j=0;j<6;j++) eeprom_append(dscr_vidpidver[j]); + for(j=0;j<2;j++) eeprom_append(dscr_attrpow[j]); + eeprom_append(0x1C); + eeprom_append(0x00); + for(j=0;j<2;j++) eeprom_append(dscr_usbver[j]); + sofs = 0x80 + ee_ptr + 6; + eeprom_append(sofs); + eeprom_append(str1[0]); + sofs += str1[0]; + eeprom_append(sofs); + eeprom_append(str2[0]); + sofs += str2[0]; + eeprom_append(sofs); + eeprom_append(str3[0]); + for(j=0;j>8)&0xFF; +} + Index: trunk/FirmwareFX2/eeprom.h =================================================================== --- trunk/FirmwareFX2/eeprom.h (revision 4) +++ trunk/FirmwareFX2/eeprom.h (revision 4) @@ -0,0 +1,26 @@ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _EEPROM_H +#define _EEPROM_H 1 + +extern xdata unsigned char eeprom[128]; +extern void eeprom_init(void); + +#endif /* _EEPROM_H */ + Index: trunk/FirmwareFX2/fx2/Makefile =================================================================== --- trunk/FirmwareFX2/fx2/Makefile (revision 4) +++ trunk/FirmwareFX2/fx2/Makefile (revision 4) @@ -0,0 +1,35 @@ +#----------------------------------------------------------------------------- +# Makefile for FX2 library code +#----------------------------------------------------------------------------- +# Copyright (C) 2007 Kolja Waschk, ixo.de +#----------------------------------------------------------------------------- +# This code is part of usbjtag. usbjtag is free software; you can redistribute +# it and/or modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of the License, +# or (at your option) any later version. usbjtag is distributed in the hope +# that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. You should have received a +# copy of the GNU General Public License along with this program in the file +# COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +# St, Fifth Floor, Boston, MA 02110-1301 USA +#----------------------------------------------------------------------------- + +CC=sdcc +CFLAGS+=-mmcs51 --no-xinit-opt -I. +CPPFLAGS+= + +%.rel : %.c + $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@ + +libfx2.lib: delay.rel fx2utils.rel i2c.rel isr.rel timer.rel usb_common.rel + rm -f $@ + touch $@ + for obj in $^ ; do basename $$obj .rel >> $@ ; done + +clean: + rm -f *.lst *.asm *.lib *.sym *.rel *.lib + + + + Index: trunk/FirmwareFX2/fx2/delay.c =================================================================== --- trunk/FirmwareFX2/fx2/delay.c (revision 4) +++ trunk/FirmwareFX2/fx2/delay.c (revision 4) @@ -0,0 +1,74 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Delay routines + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +/* + * Delay approximately 1 microsecond (including overhead in udelay). + */ +static void +udelay1 (void) _naked +{ + _asm ; lcall that got us here took 4 bus cycles + ret ; 4 bus cycles + _endasm; +} + +/* + * delay for approximately usecs microseconds + */ +void +udelay (unsigned char usecs) +{ + do { + udelay1 (); + } while (--usecs != 0); +} + + +/* + * Delay approximately 1 millisecond. + * We're running at 48 MHz, so we need 48,000 clock cycles. + * + * Note however, that each bus cycle takes 4 clock cycles (not obvious, + * but explains the factor of 4 problem below). + */ +static void +mdelay1 (void) _naked +{ + _asm + mov dptr,#(-1200 & 0xffff) +002$: + inc dptr ; 3 bus cycles + mov a, dpl ; 2 bus cycles + orl a, dph ; 2 bus cycles + jnz 002$ ; 3 bus cycles + + ret + _endasm; +} + +void +mdelay (unsigned int msecs) +{ + do { + mdelay1 (); + } while (--msecs != 0); +} + + Index: trunk/FirmwareFX2/fx2/delay.h =================================================================== --- trunk/FirmwareFX2/fx2/delay.h (revision 4) +++ trunk/FirmwareFX2/fx2/delay.h (revision 4) @@ -0,0 +1,36 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Delay routines + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _DELAY_H_ +#define _DELAY_H_ + +/* + * delay for approximately usecs microseconds + * Note limit of 255 usecs. + */ +void udelay (unsigned char usecs); + +/* + * delay for approximately msecs milliseconds + */ +void mdelay (unsigned short msecs); + + +#endif /* _DELAY_H_ */ Index: trunk/FirmwareFX2/fx2/fx2regs.h =================================================================== --- trunk/FirmwareFX2/fx2/fx2regs.h (revision 4) +++ trunk/FirmwareFX2/fx2/fx2regs.h (revision 4) @@ -0,0 +1,714 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * FX2 register definitions + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +/* +//----------------------------------------------------------------------------- +// File: FX2regs.h +// Contents: EZ-USB FX2 register declarations and bit mask definitions. +// +// $Archive: /USB/Target/Inc/fx2regs.h $ +// $Date: 2009-08-26 09:14:41 $ +// $Revision: 1.1 $ +// +// +// Copyright (c) 2000 Cypress Semiconductor, All rights reserved +//----------------------------------------------------------------------------- +*/ + + +#ifndef FX2REGS_H /* Header Sentry */ +#define FX2REGS_H + +#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h + +/* +//----------------------------------------------------------------------------- +// FX2 Related Register Assignments +//----------------------------------------------------------------------------- + +// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register +// address allocation by using "#define ALLOCATE_EXTERN". +// When using "#define ALLOCATE_EXTERN", you get (for instance): +// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40; +// Such lines are created from FX2.h by using the preprocessor. +// Incidently, these lines will not generate any space in the resulting hex +// file; they just bind the symbols to the addresses for compilation. +// You just need to put "#define ALLOCATE_EXTERN" in your main program file; +// i.e. fw.c or a stand-alone C source file. +// Without "#define ALLOCATE_EXTERN", you just get the external reference: +// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40; +// This uses the concatenation operator "##" to insert a comment "//" +// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted. +*/ + + +#ifdef ALLOCATE_EXTERN +#define EXTERN +#define _AT_(a) at a +#else +#define EXTERN extern +#define _AT_ ;/ ## / +#endif + +typedef unsigned char BYTE; +typedef unsigned short WORD; + +EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128]; +EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ; + +// General Configuration + +EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status +EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration +EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments +EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments +EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state +EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint +EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H +EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L +EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2 +EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities +EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision +EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control + +// Endpoint Configuration + +EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration +EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration +EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration +EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration +EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration +EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration +EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration +EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration +EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration +EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration +EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only) +EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only) +EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only) +EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only) +EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only) +EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only) +EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only) +EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only) +EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H +EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L +EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H +EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L +EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H +EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L +EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H +EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L +EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3) +EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3) +EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3) +EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3) +EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End +EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End + +// Interrupts + +EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable +EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request +EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable +EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request +EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable +EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request +EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable +EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request +EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable +EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request +EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable +EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request +EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables +EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests +EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables +EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests +EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable +EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request +EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables +EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests +EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit +EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0] +EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector +EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector +EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup + +// Input/Output + +EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration +EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration +EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration +EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status +EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data +EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control +EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access +EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access + +#define EXTAUTODAT1 XAUTODAT1 +#define EXTAUTODAT2 XAUTODAT2 + +// USB Control + +EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status +EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend +EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity +EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control +EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H +EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L +EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7 +EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address + +// Endpoints + +EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H +EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L +EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count +EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count +EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H +EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L +EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H +EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L +EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H +EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L +EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H +EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L +EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status +EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status +EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status +EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status +EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status +EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status +EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status +EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags +EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags +EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags +EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags +EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H +EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L +EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H +EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L +EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H +EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L +EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H +EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L +EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte +EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte +EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode +EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data + +// GPIF + +EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector +EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode +EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states +EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive +EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H +EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L + +EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3 +EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2 +EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1 +EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0 + +#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) +#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) +#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) +#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) + +// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High +// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low +EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select +EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag +EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger +// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High +// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low +EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select +EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag +EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger +// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High +// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low +EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select +EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag +EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger +// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High +// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low +EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select +EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag +EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger +EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only) +EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac +EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger +EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG +EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states +EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles + +// UDMA + +EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state +EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria +EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state +EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state +EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ; +EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe +EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge +EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe +EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift +EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte +EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte +EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only + + +// Debug/Test + +EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug +EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration +EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes +EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override +EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM +EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals +EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs + +// Endpoint Buffers + +EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer +EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer +EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer +EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT) +EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT) +EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT) +EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT) + +#undef EXTERN +#undef _AT_ + +/*----------------------------------------------------------------------------- + Special Function Registers (SFRs) + The byte registers and bits defined in the following list are based + on the Synopsis definition of the 8051 Special Function Registers for EZ-USB. + If you modify the register definitions below, please regenerate the file + "ezregs.inc" which includes the same basic information for assembly inclusion. +-----------------------------------------------------------------------------*/ + +sfr at 0x80 IOA; +sfr at 0x81 SP; +sfr at 0x82 DPL; +sfr at 0x83 DPH; +sfr at 0x84 DPL1; +sfr at 0x85 DPH1; +sfr at 0x86 DPS; + /* DPS */ + sbit at 0x86+0 SEL; +sfr at 0x87 PCON; /* PCON */ + //sbit IDLE = 0x87+0; + //sbit STOP = 0x87+1; + //sbit GF0 = 0x87+2; + //sbit GF1 = 0x87+3; + //sbit SMOD0 = 0x87+7; +sfr at 0x88 TCON; + /* TCON */ + sbit at 0x88+0 IT0; + sbit at 0x88+1 IE0; + sbit at 0x88+2 IT1; + sbit at 0x88+3 IE1; + sbit at 0x88+4 TR0; + sbit at 0x88+5 TF0; + sbit at 0x88+6 TR1; + sbit at 0x88+7 TF1; +sfr at 0x89 TMOD; + /* TMOD */ + //sbit M00 = 0x89+0; + //sbit M10 = 0x89+1; + //sbit CT0 = 0x89+2; + //sbit GATE0 = 0x89+3; + //sbit M01 = 0x89+4; + //sbit M11 = 0x89+5; + //sbit CT1 = 0x89+6; + //sbit GATE1 = 0x89+7; +sfr at 0x8A TL0; +sfr at 0x8B TL1; +sfr at 0x8C TH0; +sfr at 0x8D TH1; +sfr at 0x8E CKCON; + /* CKCON */ + //sbit MD0 = 0x89+0; + //sbit MD1 = 0x89+1; + //sbit MD2 = 0x89+2; + //sbit T0M = 0x89+3; + //sbit T1M = 0x89+4; + //sbit T2M = 0x89+5; +// sfr at 0x8F SPC_FNC; // Was WRS in Reg320 + /* CKCON */ + //sbit WRS = 0x8F+0; +sfr at 0x90 IOB; +sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320 + /* EXIF */ + //sbit USBINT = 0x91+4; + //sbit I2CINT = 0x91+5; + //sbit IE4 = 0x91+6; + //sbit IE5 = 0x91+7; +sfr at 0x92 MPAGE; +sfr at 0x98 SCON0; + /* SCON0 */ + sbit at 0x98+0 RI; + sbit at 0x98+1 TI; + sbit at 0x98+2 RB8; + sbit at 0x98+3 TB8; + sbit at 0x98+4 REN; + sbit at 0x98+5 SM2; + sbit at 0x98+6 SM1; + sbit at 0x98+7 SM0; +sfr at 0x99 SBUF0; + +sfr at 0x9A APTR1H; +sfr at 0x9B APTR1L; +sfr at 0x9C AUTODAT1; +sfr at 0x9D AUTOPTRH2; +sfr at 0x9E AUTOPTRL2; +sfr at 0x9F AUTODAT2; +sfr at 0xA0 IOC; +sfr at 0xA1 INT2CLR; +sfr at 0xA2 INT4CLR; + +#define AUTOPTRH1 APTR1H +#define AUTOPTRL1 APTR1L + +sfr at 0xA8 IE; + /* IE */ + sbit at 0xA8+0 EX0; + sbit at 0xA8+1 ET0; + sbit at 0xA8+2 EX1; + sbit at 0xA8+3 ET1; + sbit at 0xA8+4 ES0; + sbit at 0xA8+5 ET2; + sbit at 0xA8+6 ES1; + sbit at 0xA8+7 EA; + +sfr at 0xAA EP2468STAT; + /* EP2468STAT */ + //sbit EP2E = 0xAA+0; + //sbit EP2F = 0xAA+1; + //sbit EP4E = 0xAA+2; + //sbit EP4F = 0xAA+3; + //sbit EP6E = 0xAA+4; + //sbit EP6F = 0xAA+5; + //sbit EP8E = 0xAA+6; + //sbit EP8F = 0xAA+7; + +sfr at 0xAB EP24FIFOFLGS; +sfr at 0xAC EP68FIFOFLGS; +sfr at 0xAF AUTOPTRSETUP; + /* AUTOPTRSETUP */ + sbit at 0xAF+0 EXTACC; + sbit at 0xAF+1 APTR1FZ; + sbit at 0xAF+2 APTR2FZ; + +sfr at 0xB0 IOD; +sfr at 0xB1 IOE; +sfr at 0xB2 OEA; +sfr at 0xB3 OEB; +sfr at 0xB4 OEC; +sfr at 0xB5 OED; +sfr at 0xB6 OEE; + +sfr at 0xB8 IP; + /* IP */ + sbit at 0xB8+0 PX0; + sbit at 0xB8+1 PT0; + sbit at 0xB8+2 PX1; + sbit at 0xB8+3 PT1; + sbit at 0xB8+4 PS0; + sbit at 0xB8+5 PT2; + sbit at 0xB8+6 PS1; + +sfr at 0xBA EP01STAT; +sfr at 0xBB GPIFTRIG; + +sfr at 0xBD GPIFSGLDATH; +sfr at 0xBE GPIFSGLDATLX; +sfr at 0xBF GPIFSGLDATLNOX; + +sfr at 0xC0 SCON1; + /* SCON1 */ + sbit at 0xC0+0 RI1; + sbit at 0xC0+1 TI1; + sbit at 0xC0+2 RB81; + sbit at 0xC0+3 TB81; + sbit at 0xC0+4 REN1; + sbit at 0xC0+5 SM21; + sbit at 0xC0+6 SM11; + sbit at 0xC0+7 SM01; +sfr at 0xC1 SBUF1; +sfr at 0xC8 T2CON; + /* T2CON */ + sbit at 0xC8+0 CP_RL2; + sbit at 0xC8+1 C_T2; + sbit at 0xC8+2 TR2; + sbit at 0xC8+3 EXEN2; + sbit at 0xC8+4 TCLK; + sbit at 0xC8+5 RCLK; + sbit at 0xC8+6 EXF2; + sbit at 0xC8+7 TF2; +sfr at 0xCA RCAP2L; +sfr at 0xCB RCAP2H; +sfr at 0xCC TL2; +sfr at 0xCD TH2; +sfr at 0xD0 PSW; + /* PSW */ + sbit at 0xD0+0 P; + sbit at 0xD0+1 FL; + sbit at 0xD0+2 OV; + sbit at 0xD0+3 RS0; + sbit at 0xD0+4 RS1; + sbit at 0xD0+5 F0; + sbit at 0xD0+6 AC; + sbit at 0xD0+7 CY; +sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320 + /* EICON */ + sbit at 0xD8+3 INT6; + sbit at 0xD8+4 RESI; + sbit at 0xD8+5 ERESI; + sbit at 0xD8+7 SMOD1; +sfr at 0xE0 ACC; +sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320 + /* EIE */ + sbit at 0xE8+0 EIUSB; + sbit at 0xE8+1 EI2C; + sbit at 0xE8+2 EIEX4; + sbit at 0xE8+3 EIEX5; + sbit at 0xE8+4 EIEX6; +sfr at 0xF0 B; +sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320 + /* EIP */ + sbit at 0xF8+0 PUSB; + sbit at 0xF8+1 PI2C; + sbit at 0xF8+2 EIPX4; + sbit at 0xF8+3 EIPX5; + sbit at 0xF8+4 EIPX6; + +/*----------------------------------------------------------------------------- + Bit Masks +-----------------------------------------------------------------------------*/ + +#define bmBIT0 1 +#define bmBIT1 2 +#define bmBIT2 4 +#define bmBIT3 8 +#define bmBIT4 16 +#define bmBIT5 32 +#define bmBIT6 64 +#define bmBIT7 128 + +/* CPU Control & Status Register (CPUCS) */ +#define bmPRTCSTB bmBIT5 +#define bmCLKSPD (bmBIT4 | bmBIT3) +#define bmCLKSPD1 bmBIT4 +#define bmCLKSPD0 bmBIT3 +#define bmCLKINV bmBIT2 +#define bmCLKOE bmBIT1 +#define bm8051RES bmBIT0 +/* Port Alternate Configuration Registers */ +/* Port A (PORTACFG) */ +#define bmFLAGD bmBIT7 +#define bmINT1 bmBIT1 +#define bmINT0 bmBIT0 +/* Port C (PORTCCFG) */ +#define bmGPIFA7 bmBIT7 +#define bmGPIFA6 bmBIT6 +#define bmGPIFA5 bmBIT5 +#define bmGPIFA4 bmBIT4 +#define bmGPIFA3 bmBIT3 +#define bmGPIFA2 bmBIT2 +#define bmGPIFA1 bmBIT1 +#define bmGPIFA0 bmBIT0 +/* Port E (PORTECFG) */ +#define bmGPIFA8 bmBIT7 +#define bmT2EX bmBIT6 +#define bmINT6 bmBIT5 +#define bmRXD1OUT bmBIT4 +#define bmRXD0OUT bmBIT3 +#define bmT2OUT bmBIT2 +#define bmT1OUT bmBIT1 +#define bmT0OUT bmBIT0 + +/* I2C Control & Status Register (I2CS) */ +#define bmSTART bmBIT7 +#define bmSTOP bmBIT6 +#define bmLASTRD bmBIT5 +#define bmID (bmBIT4 | bmBIT3) +#define bmBERR bmBIT2 +#define bmACK bmBIT1 +#define bmDONE bmBIT0 +/* I2C Control Register (I2CTL) */ +#define bmSTOPIE bmBIT1 +#define bm400KHZ bmBIT0 +/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */ +#define bmIV4 bmBIT6 +#define bmIV3 bmBIT5 +#define bmIV2 bmBIT4 +#define bmIV1 bmBIT3 +#define bmIV0 bmBIT2 +/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */ +#define bmEP0ACK bmBIT6 +#define bmHSGRANT bmBIT5 +#define bmURES bmBIT4 +#define bmSUSP bmBIT3 +#define bmSUTOK bmBIT2 +#define bmSOF bmBIT1 +#define bmSUDAV bmBIT0 +/* Breakpoint register (BREAKPT) */ +#define bmBREAK bmBIT3 +#define bmBPPULSE bmBIT2 +#define bmBPEN bmBIT1 +/* Interrupt 2 & 4 Setup (INTSETUP) */ +#define bmAV2EN bmBIT3 +#define bmINT4IN bmBIT1 +#define bmAV4EN bmBIT0 +/* USB Control & Status Register (USBCS) */ +#define bmHSM bmBIT7 +#define bmDISCON bmBIT3 +#define bmNOSYNSOF bmBIT2 +#define bmRENUM bmBIT1 +#define bmSIGRESUME bmBIT0 +/* Wakeup Control and Status Register (WAKEUPCS) */ +#define bmWU2 bmBIT7 +#define bmWU bmBIT6 +#define bmWU2POL bmBIT5 +#define bmWUPOL bmBIT4 +#define bmDPEN bmBIT2 +#define bmWU2EN bmBIT1 +#define bmWUEN bmBIT0 +/* End Point 0 Control & Status Register (EP0CS) */ +#define bmHSNAK bmBIT7 +/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */ +#define bmEPBUSY bmBIT1 +#define bmEPSTALL bmBIT0 +/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */ +#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4) +#define bmEPFULL bmBIT3 +#define bmEPEMPTY bmBIT2 +/* Endpoint Status (EP2468STAT) SFR bits */ +#define bmEP8FULL bmBIT7 +#define bmEP8EMPTY bmBIT6 +#define bmEP6FULL bmBIT5 +#define bmEP6EMPTY bmBIT4 +#define bmEP4FULL bmBIT3 +#define bmEP4EMPTY bmBIT2 +#define bmEP2FULL bmBIT1 +#define bmEP2EMPTY bmBIT0 +/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */ +#define bmSDPAUTO bmBIT0 +/* Endpoint Data Toggle Control (TOGCTL) */ +#define bmQUERYTOGGLE bmBIT7 +#define bmSETTOGGLE bmBIT6 +#define bmRESETTOGGLE bmBIT5 +#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0 +/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */ +#define bmEP8IBN bmBIT5 +#define bmEP6IBN bmBIT4 +#define bmEP4IBN bmBIT3 +#define bmEP2IBN bmBIT2 +#define bmEP1IBN bmBIT1 +#define bmEP0IBN bmBIT0 + +/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */ +#define bmEP8PING bmBIT7 +#define bmEP6PING bmBIT6 +#define bmEP4PING bmBIT5 +#define bmEP2PING bmBIT4 +#define bmEP1PING bmBIT3 +#define bmEP0PING bmBIT2 +#define bmIBN bmBIT0 + +/* Interface Configuration bits (IFCONFIG) */ +#define bmIFCLKSRC bmBIT7 // set == INTERNAL +#define bm3048MHZ bmBIT6 // set == 48 MHz +#define bmIFCLKOE bmBIT5 +#define bmIFCLKPOL bmBIT4 +#define bmASYNC bmBIT3 +#define bmGSTATE bmBIT2 +#define bmIFCFG1 bmBIT1 +#define bmIFCFG0 bmBIT0 +#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1) +#define bmIFGPIF bmIFCFG1 + +/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */ +#define bmINFM bmBIT6 +#define bmOEP bmBIT5 +#define bmAUTOOUT bmBIT4 +#define bmAUTOIN bmBIT3 +#define bmZEROLENIN bmBIT2 +// must be zero bmBIT1 +#define bmWORDWIDE bmBIT0 + +/* + * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features + */ +#define bmNOAUTOARM bmBIT1 // these don't match the docs +#define bmSKIPCOMMIT bmBIT0 // these don't match the docs + +#define bmDYN_OUT bmBIT1 // these do... +#define bmENH_PKT bmBIT0 + + +/* Fifo Reset bits (FIFORESET) */ +#define bmNAKALL bmBIT7 + +/* Endpoint Configuration (EPxCFG) */ +#define bmVALID bmBIT7 +#define bmIN bmBIT6 +#define bmTYPE1 bmBIT5 +#define bmTYPE0 bmBIT4 +#define bmISOCHRONOUS bmTYPE0 +#define bmBULK bmTYPE1 +#define bmINTERRUPT (bmTYPE1 | bmTYPE0) +#define bm1KBUF bmBIT3 +#define bmBUF1 bmBIT1 +#define bmBUF0 bmBIT0 +#define bmQUADBUF 0 +#define bmINVALIDBUF bmBUF0 +#define bmDOUBLEBUF bmBUF1 +#define bmTRIPLEBUF (bmBUF1 | bmBUF0) + +/* OUTPKTEND */ +#define bmSKIP bmBIT7 // low 4 bits specify which end point + +/* GPIFTRIG defs */ +#define bmGPIF_IDLE bmBIT7 // status bit + +#define bmGPIF_EP2_START 0 +#define bmGPIF_EP4_START 1 +#define bmGPIF_EP6_START 2 +#define bmGPIF_EP8_START 3 +#define bmGPIF_READ bmBIT2 +#define bmGPIF_WRITE 0 + +/* EXIF bits */ +#define bmEXIF_USBINT bmBIT4 +#define bmEXIF_I2CINT bmBIT5 +#define bmEXIF_IE4 bmBIT6 +#define bmEXIF_IE5 bmBIT7 + + +#endif /* FX2REGS_H */ Index: trunk/FirmwareFX2/fx2/fx2utils.c =================================================================== --- trunk/FirmwareFX2/fx2/fx2utils.c (revision 4) +++ trunk/FirmwareFX2/fx2/fx2utils.c (revision 4) @@ -0,0 +1,52 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * FX2 specific subroutines + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "fx2utils.h" +#include "fx2regs.h" +#include "delay.h" + +void +fx2_stall_ep0 (void) +{ + EP0CS |= bmEPSTALL; +} + +void +fx2_reset_data_toggle (unsigned char ep) +{ + TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f)); + TOGCTL |= bmRESETTOGGLE; +} + +void +fx2_renumerate (void) +{ + USBCS |= bmDISCON | bmRENUM; + + // mdelay (1500); // FIXME why 1.5 seconds? + mdelay (250); // FIXME why 1.5 seconds? + + USBIRQ = 0xff; // clear any pending USB irqs... + EPIRQ = 0xff; // they're from before the renumeration + + EXIF &= ~bmEXIF_USBINT; + + USBCS &= ~bmDISCON; // reconnect USB +} Index: trunk/FirmwareFX2/fx2/fx2utils.h =================================================================== --- trunk/FirmwareFX2/fx2/fx2utils.h (revision 4) +++ trunk/FirmwareFX2/fx2/fx2utils.h (revision 4) @@ -0,0 +1,30 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * FX2 specific subroutines + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _FX2UTILS_H_ +#define _FX2UTILS_H_ + +void fx2_stall_ep0 (void); +void fx2_reset_data_toggle (unsigned char ep); +void fx2_renumerate (void); + + + +#endif /* _FX2UTILS_H_ */ Index: trunk/FirmwareFX2/fx2/i2c.c =================================================================== --- trunk/FirmwareFX2/fx2/i2c.c (revision 4) +++ trunk/FirmwareFX2/fx2/i2c.c (revision 4) @@ -0,0 +1,121 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * I2C read/write functions for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "i2c.h" +#include "fx2regs.h" +#include + + +// issue a stop bus cycle and wait for completion + + +// returns non-zero if successful, else 0 +unsigned char +i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len) +{ + volatile unsigned char junk; + + if (len == 0) // reading zero bytes always works + return 1; + + while (I2CS & bmSTOP) // wait for stop to clear + ; + + I2CS = bmSTART; + I2DAT = (addr << 1) | 1; // write address and direction (1's the read bit) + + while ((I2CS & bmDONE) == 0) + ; + + if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered... + goto fail; + + if (len == 1) + I2CS |= bmLASTRD; + + junk = I2DAT; // trigger the first read cycle + + while (--len != 0){ + while ((I2CS & bmDONE) == 0) + ; + + if (I2CS & bmBERR) + goto fail; + + if (len == 1) + I2CS |= bmLASTRD; + + *buf++ = I2DAT; // get data, trigger another read + } + + // wait for final byte + + while ((I2CS & bmDONE) == 0) + ; + + if (I2CS & bmBERR) + goto fail; + + I2CS |= bmSTOP; + *buf = I2DAT; + + return 1; + + fail: + I2CS |= bmSTOP; + return 0; +} + + + +// returns non-zero if successful, else 0 +unsigned char +i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len) +{ + while (I2CS & bmSTOP) // wait for stop to clear + ; + + I2CS = bmSTART; + I2DAT = (addr << 1) | 0; // write address and direction (0's the write bit) + + while ((I2CS & bmDONE) == 0) + ; + + if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered... + goto fail; + + while (len > 0){ + I2DAT = *buf++; + len--; + + while ((I2CS & bmDONE) == 0) + ; + + if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered... + goto fail; + } + + I2CS |= bmSTOP; + return 1; + + fail: + I2CS |= bmSTOP; + return 0; +} Index: trunk/FirmwareFX2/fx2/i2c.h =================================================================== --- trunk/FirmwareFX2/fx2/i2c.h (revision 4) +++ trunk/FirmwareFX2/fx2/i2c.h (revision 4) @@ -0,0 +1,30 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * I2C read/write functions for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +// returns non-zero if successful, else 0 +unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len); + +// returns non-zero if successful, else 0 +unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len); + +#endif /* _I2C_H_ */ Index: trunk/FirmwareFX2/fx2/isr.c =================================================================== --- trunk/FirmwareFX2/fx2/isr.c (revision 4) +++ trunk/FirmwareFX2/fx2/isr.c (revision 4) @@ -0,0 +1,168 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Interrupt handling for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "isr.h" +#include "fx2regs.h" +#include "syncdelay.h" + +extern xdata unsigned char _standard_interrupt_vector[]; +extern xdata unsigned char _usb_autovector[]; +extern xdata unsigned char _fifo_gpif_autovector[]; + +#define LJMP_OPCODE 0x02 + +/* + * Hook standard interrupt vector. + * + * vector_number is from the SV_ list. + * addr is the address of the interrupt service routine. + */ +void +hook_sv (unsigned char vector_number, unsigned short addr) +{ + bit t; + + // sanity checks + + if (vector_number < SV_MIN || vector_number > SV_MAX) + return; + + if ((vector_number & 0x0f) != 0x03 && (vector_number & 0x0f) != 0x0b) + return; + + t = EA; + EA = 0; + _standard_interrupt_vector[vector_number] = LJMP_OPCODE; + _standard_interrupt_vector[vector_number + 1] = addr >> 8; + _standard_interrupt_vector[vector_number + 2] = addr & 0xff; + EA = t; +} + +/* + * Hook usb interrupt vector. + * + * vector_number is from the UV_ list. + * addr is the address of the interrupt service routine. + */ +void +hook_uv (unsigned char vector_number, unsigned short addr) +{ + bit t; + + // sanity checks + +#if UV_MIN>0 + if (vector_number < UV_MIN) return; +#endif + if (vector_number > UV_MAX) + return; + + if ((vector_number & 0x3) != 0) + return; + + t = EA; + EA = 0; + _usb_autovector[vector_number] = LJMP_OPCODE; + _usb_autovector[vector_number + 1] = addr >> 8; + _usb_autovector[vector_number + 2] = addr & 0xff; + EA = t; +} + +/* + * Hook fifo/gpif interrupt vector. + * + * vector_number is from the FGV_ list. + * addr is the address of the interrupt service routine. + */ +void +hook_fgv (unsigned char vector_number, unsigned short addr) +{ + bit t; + + // sanity checks + + if (vector_number < FGV_MIN || vector_number > FGV_MAX) + return; + + if ((vector_number & 0x3) != 0) + return; + + t = EA; + EA = 0; + _fifo_gpif_autovector[vector_number] = LJMP_OPCODE; + _fifo_gpif_autovector[vector_number + 1] = addr >> 8; + _fifo_gpif_autovector[vector_number + 2] = addr & 0xff; + EA = t; +} + +/* + * One time call to enable autovectoring for both USB and FIFO/GPIF. + * + * This disables all USB and FIFO/GPIF interrupts and clears + * any pending interrupts too. It leaves the master USB and FIFO/GPIF + * interrupts enabled. + */ +void +setup_autovectors (void) +{ + // disable master usb and fifo/gpif interrupt enables + EIUSB = 0; + EIEX4 = 0; + + hook_sv (SV_INT_2, (unsigned short) _usb_autovector); + hook_sv (SV_INT_4, (unsigned short) _fifo_gpif_autovector); + + // disable all fifo interrupt enables + SYNCDELAY; + EP2FIFOIE = 0; SYNCDELAY; + EP4FIFOIE = 0; SYNCDELAY; + EP6FIFOIE = 0; SYNCDELAY; + EP8FIFOIE = 0; SYNCDELAY; + + // clear all pending fifo irqs + EP2FIFOIRQ = 0xff; SYNCDELAY; + EP4FIFOIRQ = 0xff; SYNCDELAY; + EP6FIFOIRQ = 0xff; SYNCDELAY; + EP8FIFOIRQ = 0xff; SYNCDELAY; + + IBNIE = 0; + IBNIRQ = 0xff; + NAKIE = 0; + NAKIRQ = 0xff; + USBIE = 0; + USBIRQ = 0xff; + EPIE = 0; + EPIRQ = 0xff; + SYNCDELAY; GPIFIE = 0; + SYNCDELAY; GPIFIRQ = 0xff; + USBERRIE = 0; + USBERRIRQ = 0xff; + CLRERRCNT = 0; + + INTSETUP = bmAV2EN | bmAV4EN | bmINT4IN; + + // clear master irq's for usb and fifo/gpif + EXIF &= ~bmEXIF_USBINT; + EXIF &= ~bmEXIF_IE4; + + // enable master usb and fifo/gpif interrrupts + EIUSB = 1; + EIEX4 = 1; +} Index: trunk/FirmwareFX2/fx2/isr.h =================================================================== --- trunk/FirmwareFX2/fx2/isr.h (revision 4) +++ trunk/FirmwareFX2/fx2/isr.h (revision 4) @@ -0,0 +1,170 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Interrupt handling for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _ISR_H_ +#define _ISR_H_ + +/* + * ---------------------------------------------------------------- + * routines for managing interrupt services routines + * ---------------------------------------------------------------- + */ + +/* + * The FX2 has three discrete sets of interrupt vectors. + * The first set is the standard 8051 vector (13 8-byte entries). + * The second set is USB interrupt autovector (32 4-byte entries). + * The third set is the FIFO/GPIF autovector (14 4-byte entries). + * + * Since all the code we're running in the FX2 is ram based, we + * forego the typical "initialize the interrupt vectors at link time" + * strategy, in favor of calls at run time that install the correct + * pointers to functions. + */ + +/* + * Standard Vector numbers + */ + +#define SV_INT_0 0x03 +#define SV_TIMER_0 0x0b +#define SV_INT_1 0x13 +#define SV_TIMER_1 0x1b +#define SV_SERIAL_0 0x23 +#define SV_TIMER_2 0x2b +#define SV_RESUME 0x33 +#define SV_SERIAL_1 0x3b +#define SV_INT_2 0x43 // (INT_2) points at USB autovector +#define SV_I2C 0x4b +#define SV_INT_4 0x53 // (INT_4) points at FIFO/GPIF autovector +#define SV_INT_5 0x5b +#define SV_INT_6 0x63 + +#define SV_MIN SV_INT_0 +#define SV_MAX SV_INT_6 + +/* + * USB Auto Vector numbers + */ + +#define UV_SUDAV 0x00 +#define UV_SOF 0x04 +#define UV_SUTOK 0x08 +#define UV_SUSPEND 0x0c +#define UV_USBRESET 0x10 +#define UV_HIGHSPEED 0x14 +#define UV_EP0ACK 0x18 +#define UV_SPARE_1C 0x1c +#define UV_EP0IN 0x20 +#define UV_EP0OUT 0x24 +#define UV_EP1IN 0x28 +#define UV_EP1OUT 0x2c +#define UV_EP2 0x30 +#define UV_EP4 0x34 +#define UV_EP6 0x38 +#define UV_EP8 0x3c +#define UV_IBN 0x40 +#define UV_SPARE_44 0x44 +#define UV_EP0PINGNAK 0x48 +#define UV_EP1PINGNAK 0x4c +#define UV_EP2PINGNAK 0x50 +#define UV_EP4PINGNAK 0x54 +#define UV_EP6PINGNAK 0x58 +#define UV_EP8PINGNAK 0x5c +#define UV_ERRLIMIT 0x60 +#define UV_SPARE_64 0x64 +#define UV_SPARE_68 0x68 +#define UV_SPARE_6C 0x6c +#define UV_EP2ISOERR 0x70 +#define UV_EP4ISOERR 0x74 +#define UV_EP6ISOERR 0x78 +#define UV_EP8ISOERR 0x7c + +#define UV_MIN UV_SUDAV +#define UV_MAX UV_EP8ISOERR + +/* + * FIFO/GPIF Auto Vector numbers + */ + +#define FGV_EP2PF 0x80 +#define FGV_EP4PF 0x84 +#define FGV_EP6PF 0x88 +#define FGV_EP8PF 0x8c +#define FGV_EP2EF 0x90 +#define FGV_EP4EF 0x94 +#define FGV_EP6EF 0x98 +#define FGV_EP8EF 0x9c +#define FGV_EP2FF 0xa0 +#define FGV_EP4FF 0xa4 +#define FGV_EP6FF 0xa8 +#define FGV_EP8FF 0xac +#define FGV_GPIFDONE 0xb0 +#define FGV_GPIFWF 0xb4 + +#define FGV_MIN FGV_EP2PF +#define FGV_MAX FGV_GPIFWF + + +/* + * Hook standard interrupt vector. + * + * vector_number is from the SV_ list above. + * addr is the address of the interrupt service routine. + */ +void hook_sv (unsigned char vector_number, unsigned short addr); + +/* + * Hook usb interrupt vector. + * + * vector_number is from the UV_ list above. + * addr is the address of the interrupt service routine. + */ +void hook_uv (unsigned char vector_number, unsigned short addr); + +/* + * Hook fifo/gpif interrupt vector. + * + * vector_number is from the FGV_ list above. + * addr is the address of the interrupt service routine. + */ +void hook_fgv (unsigned char vector_number, unsigned short addr); + +/* + * One time call to enable autovectoring for both USB and FIFO/GPIF + */ +void setup_autovectors (void); + + +/* + * Must be called in each usb interrupt handler + */ +#define clear_usb_irq() \ + EXIF &= ~bmEXIF_USBINT; \ + INT2CLR = 0 + +/* + * Must be calledin each fifo/gpif interrupt handler + */ +#define clear_fifo_gpif_irq() \ + EXIF &= ~bmEXIF_IE4; \ + INT4CLR = 0 + +#endif /* _ISR_H_ */ Index: trunk/FirmwareFX2/fx2/syncdelay.h =================================================================== --- trunk/FirmwareFX2/fx2/syncdelay.h (revision 4) +++ trunk/FirmwareFX2/fx2/syncdelay.h (revision 4) @@ -0,0 +1,64 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Synchronization delay for FX2 access to specific registers + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _SYNCDELAY_H_ +#define _SYNCDELAY_H_ + +/* + * Magic delay required between access to certain xdata registers (TRM page 15-106). + * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each + * NOP is a single cycle.... + * + * From TRM page 15-105: + * + * Under certain conditions, some read and write access to the FX2 registers must + * be separated by a "synchronization delay". The delay is necessary only under the + * following conditions: + * + * - between a write to any register in the 0xE600 - 0xE6FF range and a write to one + * of the registers listed below. + * + * - between a write to one of the registers listed below and a read from any register + * in the 0xE600 - 0xE6FF range. + * + * Registers which require a synchronization delay: + * + * FIFORESET FIFOPINPOLAR + * INPKTEND EPxBCH:L + * EPxFIFOPFH:L EPxAUTOINLENH:L + * EPxFIFOCFG EPxGPIFFLGSEL + * PINFLAGSAB PINFLAGSCD + * EPxFIFOIE EPxFIFOIRQ + * GPIFIE GPIFIRQ + * UDMACRCH:L GPIFADRH:L + * GPIFTRIG EPxGPIFTRIG + * OUTPKTEND REVCTL + * GPIFTCB3 GPIFTCB2 + * GPIFTCB1 GPIFTCB0 + */ + +/* + * FIXME ensure that the peep hole optimizer isn't screwing us + */ +#define SYNCDELAY _asm nop; nop; nop; _endasm +#define NOP _asm nop; _endasm + + +#endif /* _SYNCDELAY_H_ */ Index: trunk/FirmwareFX2/fx2/timer.c =================================================================== --- trunk/FirmwareFX2/fx2/timer.c (revision 4) +++ trunk/FirmwareFX2/fx2/timer.c (revision 4) @@ -0,0 +1,47 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Timer handling for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "timer.h" +#include "fx2regs.h" +#include "isr.h" + +/* + * Arrange to have isr_tick_handler called at 100 Hz. + * + * The cpu clock is running at 48e6. The input to the timer + * is 48e6 / 12 = 4e6. + * + * We arrange to have the timer overflow every 40000 clocks == 100 Hz + */ + +#define RELOAD_VALUE ((unsigned short) -40000) + +void +hook_timer_tick (unsigned short isr_tick_handler) +{ + ET2 = 0; // disable timer 2 interrupts + hook_sv (SV_TIMER_2, isr_tick_handler); + + RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value + RCAP2L = RELOAD_VALUE & 0xFF; + + T2CON = 0x04; // interrupt on overflow; reload; run + ET2 = 1; // enable timer 2 interrupts +} Index: trunk/FirmwareFX2/fx2/timer.h =================================================================== --- trunk/FirmwareFX2/fx2/timer.h (revision 4) +++ trunk/FirmwareFX2/fx2/timer.h (revision 4) @@ -0,0 +1,33 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Timer handling for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +/* + * Arrange to have isr_tick_handler called at 100 Hz + */ +void hook_timer_tick (unsigned short isr_tick_handler); + +#define clear_timer_irq() \ + TF2 = 0 /* clear overflow flag */ + + +#endif /* _TIMER_H_ */ Index: trunk/FirmwareFX2/fx2/usb_common.c =================================================================== --- trunk/FirmwareFX2/fx2/usb_common.c (revision 4) +++ trunk/FirmwareFX2/fx2/usb_common.c (revision 4) @@ -0,0 +1,376 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Common USB code for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "usb_common.h" +#include "fx2regs.h" +#include "syncdelay.h" +#include "fx2utils.h" +#include "isr.h" +#include "usb_descriptors.h" +#include "usb_requests.h" + +extern xdata char str0[]; +extern xdata char str1[]; +extern xdata char str2[]; +extern xdata char str3[]; +extern xdata char str4[]; +extern xdata char str5[]; + +volatile bit _usb_got_SUDAV; + +unsigned char _usb_config = 0; +unsigned char _usb_alt_setting = 0; // FIXME really 1/interface + +xdata unsigned char *current_device_descr; +xdata unsigned char *current_devqual_descr; +xdata unsigned char *current_config_descr; +xdata unsigned char *other_config_descr; + +static void +setup_descriptors (void) +{ + if (USBCS & bmHSM){ // high speed mode + current_device_descr = high_speed_device_descr; + current_devqual_descr = high_speed_devqual_descr; + current_config_descr = high_speed_config_descr; + other_config_descr = full_speed_config_descr; + EP8AUTOINLENH = 0x02; SYNCDELAY; // Size in bytes of the IN data automatically commited (512 bytes here) + EP8AUTOINLENL = 0x00; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet + } + else { + current_device_descr = full_speed_device_descr; + current_devqual_descr = full_speed_devqual_descr; + current_config_descr = full_speed_config_descr; + other_config_descr = high_speed_config_descr; + EP8AUTOINLENH = 0x00; SYNCDELAY; // Size in bytes of the IN data automatically commited (64 bytes here) + EP8AUTOINLENL = 0x40; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet + } + + // whack the type fields + // FIXME, may not be required. + // current_config_descr[1] = DT_CONFIG; + // other_config_descr[1] = DT_OTHER_SPEED; +} + +static void +isr_SUDAV (void) interrupt +{ + clear_usb_irq (); + _usb_got_SUDAV = 1; +} + +static void +isr_USBRESET (void) interrupt +{ + clear_usb_irq (); + setup_descriptors (); +} + +static void +isr_HIGHSPEED (void) interrupt +{ + clear_usb_irq (); + setup_descriptors (); +} + +void +usb_install_handlers (void) +{ + setup_descriptors (); // ensure that they're set before use + + hook_uv (UV_SUDAV, (unsigned short) isr_SUDAV); + hook_uv (UV_USBRESET, (unsigned short) isr_USBRESET); + hook_uv (UV_HIGHSPEED, (unsigned short) isr_HIGHSPEED); + + USBIE = bmSUDAV | bmURES | bmHSGRANT; +} + +// On the FX2 the only plausible endpoints are 0, 1, 2, 4, 6, 8 +// This doesn't check to see that they're enabled + +unsigned char +plausible_endpoint (unsigned char ep) +{ + ep &= ~0x80; // ignore direction bit + + if (ep > 8) + return 0; + + if (ep == 1) + return 1; + + return (ep & 0x1) == 0; // must be even +} + +// return pointer to control and status register for endpoint. +// only called with plausible_endpoints + +xdata volatile unsigned char * +epcs (unsigned char ep) +{ + if (ep == 0x01) // ep1 has different in and out CS regs + return EP1OUTCS; + + if (ep == 0x81) + return EP1INCS; + + ep &= ~0x80; // ignore direction bit + + if (ep == 0x00) // ep0 + return EP0CS; + + return EP2CS + (ep >> 1); // 2, 4, 6, 8 are consecutive +} + +void +usb_handle_setup_packet (void) +{ + _usb_got_SUDAV = 0; + + // handle the standard requests... + + switch (bRequestType & bmRT_TYPE_MASK){ + + case bmRT_TYPE_CLASS: + case bmRT_TYPE_RESERVED: + fx2_stall_ep0 (); // we don't handle these. indicate error + break; + + case bmRT_TYPE_VENDOR: + // call the application code. + // If it handles the command it returns non-zero + + if (!app_vendor_cmd ()) + fx2_stall_ep0 (); + break; + + case bmRT_TYPE_STD: + // these are the standard requests... + + if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_IN){ + + //////////////////////////////////// + // handle the IN requests + //////////////////////////////////// + + switch (bRequest){ + + case RQ_GET_CONFIG: + EP0BUF[0] = _usb_config; // FIXME app should handle + EP0BCH = 0; + EP0BCL = 1; + break; + + // -------------------------------- + + case RQ_GET_INTERFACE: + EP0BUF[0] = _usb_alt_setting; // FIXME app should handle + EP0BCH = 0; + EP0BCL = 1; + break; + + // -------------------------------- + + case RQ_GET_DESCR: + switch (wValueH){ + + case DT_DEVICE: + SUDPTRH = MSB (current_device_descr); + SUDPTRL = LSB (current_device_descr); + break; + + case DT_DEVQUAL: + SUDPTRH = MSB (current_devqual_descr); + SUDPTRL = LSB (current_devqual_descr); + break; + + case DT_CONFIG: + if (0 && wValueL != 1) // FIXME only a single configuration + fx2_stall_ep0 (); + else { + SUDPTRH = MSB (current_config_descr); + SUDPTRL = LSB (current_config_descr); + } + break; + + case DT_OTHER_SPEED: + if (0 && wValueL != 1) // FIXME only a single configuration + fx2_stall_ep0 (); + else { + SUDPTRH = MSB (other_config_descr); + SUDPTRL = LSB (other_config_descr); + } + break; + + case DT_STRING: + if (wValueL >= nstring_descriptors) + fx2_stall_ep0 (); + else { + xdata char *p = string_descriptors[wValueL]; + SUDPTRH = MSB (p); + SUDPTRL = LSB (p); + } + break; + + default: + fx2_stall_ep0 (); // invalid request + break; + } + break; + + // -------------------------------- + + case RQ_GET_STATUS: + switch (bRequestType & bmRT_RECIP_MASK){ + case bmRT_RECIP_DEVICE: + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + + case bmRT_RECIP_INTERFACE: + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + + case bmRT_RECIP_ENDPOINT: + if (plausible_endpoint (wIndexL)){ + EP0BUF[0] = *epcs (wIndexL) & bmEPSTALL; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + } + else + fx2_stall_ep0 (); + break; + + default: + fx2_stall_ep0 (); + break; + } + break; + + // -------------------------------- + + case RQ_SYNCH_FRAME: // not implemented + default: + fx2_stall_ep0 (); + break; + } + } + + else { + + //////////////////////////////////// + // handle the OUT requests + //////////////////////////////////// + + switch (bRequest){ + + case RQ_SET_CONFIG: + IOE &= ~(1 << 6); + _usb_config = wValueL; // FIXME app should handle + break; + + case RQ_SET_INTERFACE: + _usb_alt_setting = wValueL; // FIXME app should handle + break; + + // -------------------------------- + + case RQ_CLEAR_FEATURE: + switch (bRequestType & bmRT_RECIP_MASK){ + + case bmRT_RECIP_DEVICE: + switch (wValueL){ + case FS_DEV_REMOTE_WAKEUP: + default: + fx2_stall_ep0 (); + } + break; + + case bmRT_RECIP_ENDPOINT: + if (wValueL == FS_ENDPOINT_HALT && plausible_endpoint (wIndexL)){ + *epcs (wIndexL) &= ~bmEPSTALL; + fx2_reset_data_toggle (wIndexL); + } + else + fx2_stall_ep0 (); + break; + + default: + fx2_stall_ep0 (); + break; + } + break; + + // -------------------------------- + + case RQ_SET_FEATURE: + switch (bRequestType & bmRT_RECIP_MASK){ + + case bmRT_RECIP_DEVICE: + switch (wValueL){ + case FS_TEST_MODE: + // hardware handles this after we complete SETUP phase handshake + break; + + case FS_DEV_REMOTE_WAKEUP: + default: + fx2_stall_ep0 (); + break; + } + } + break; + + case bmRT_RECIP_ENDPOINT: + switch (wValueL){ + case FS_ENDPOINT_HALT: + if (plausible_endpoint (wIndexL)) + *epcs (wIndexL) |= bmEPSTALL; + else + fx2_stall_ep0 (); + break; + + default: + fx2_stall_ep0 (); + break; + } + break; + + // -------------------------------- + + case RQ_SET_ADDRESS: // handled by fx2 hardware + case RQ_SET_DESCR: // not implemented + default: + fx2_stall_ep0 (); + } + + } + break; + + } // bmRT_TYPE_MASK + + // ack handshake phase of device request + EP0CS |= bmHSNAK; +} Index: trunk/FirmwareFX2/fx2/usb_common.h =================================================================== --- trunk/FirmwareFX2/fx2/usb_common.h (revision 4) +++ trunk/FirmwareFX2/fx2/usb_common.h (revision 4) @@ -0,0 +1,50 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * Common USB code for FX2 + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _USB_COMMON_H_ +#define _USB_COMMON_H_ + +#define bRequestType SETUPDAT[0] +#define bRequest SETUPDAT[1] +#define wValueL SETUPDAT[2] +#define wValueH SETUPDAT[3] +#define wIndexL SETUPDAT[4] +#define wIndexH SETUPDAT[5] +#define wLengthL SETUPDAT[6] +#define wLengthH SETUPDAT[7] + +#define MSB(x) (((unsigned short) x) >> 8) +#define LSB(x) (((unsigned short) x) & 0xff) + +extern volatile bit _usb_got_SUDAV; + +// Provided by user application to report device status. +// returns non-zero if it handled the command. +unsigned char app_get_status (void); +// Provided by user application to handle VENDOR commands. +// returns non-zero if it handled the command. +unsigned char app_vendor_cmd (void); + +void usb_install_handlers (void); +void usb_handle_setup_packet (void); + +#define usb_setup_packet_avail() _usb_got_SUDAV + +#endif /* _USB_COMMON_H_ */ Index: trunk/FirmwareFX2/fx2/usb_descriptors.h =================================================================== --- trunk/FirmwareFX2/fx2/usb_descriptors.h (revision 4) +++ trunk/FirmwareFX2/fx2/usb_descriptors.h (revision 4) @@ -0,0 +1,38 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * USB descriptor references + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +extern xdata const char high_speed_device_descr[]; +extern xdata const char high_speed_devqual_descr[]; +extern xdata const char high_speed_config_descr[]; + +extern xdata const char full_speed_device_descr[]; +extern xdata const char full_speed_devqual_descr[]; +extern xdata const char full_speed_config_descr[]; + +extern xdata unsigned char nstring_descriptors; +extern xdata char * xdata string_descriptors[]; + +/* + * We patch these locations with info read from the usrp config eeprom + */ +extern xdata char usb_desc_hw_rev_binary_patch_location_0[]; +extern xdata char usb_desc_hw_rev_binary_patch_location_1[]; +extern xdata char usb_desc_hw_rev_ascii_patch_location_0[]; +extern xdata char usb_desc_serial_number_ascii[]; Index: trunk/FirmwareFX2/fx2/usb_requests.h =================================================================== --- trunk/FirmwareFX2/fx2/usb_requests.h (revision 4) +++ trunk/FirmwareFX2/fx2/usb_requests.h (revision 4) @@ -0,0 +1,86 @@ +/* -*- c++ -*- */ +/*----------------------------------------------------------------------------- + * USB request definitions + *----------------------------------------------------------------------------- + * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, + * Copyright 2003 Free Software Foundation, Inc. + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +// Standard USB requests. +// These are contained in end point 0 setup packets + + +#ifndef _USB_REQUESTS_H_ +#define _USB_REQUESTS_H_ + +// format of bmRequestType byte + +#define bmRT_DIR_MASK (0x1 << 7) +#define bmRT_DIR_IN (1 << 7) +#define bmRT_DIR_OUT (0 << 7) + +#define bmRT_TYPE_MASK (0x3 << 5) +#define bmRT_TYPE_STD (0 << 5) +#define bmRT_TYPE_CLASS (1 << 5) +#define bmRT_TYPE_VENDOR (2 << 5) +#define bmRT_TYPE_RESERVED (3 << 5) + +#define bmRT_RECIP_MASK (0x1f << 0) +#define bmRT_RECIP_DEVICE (0 << 0) +#define bmRT_RECIP_INTERFACE (1 << 0) +#define bmRT_RECIP_ENDPOINT (2 << 0) +#define bmRT_RECIP_OTHER (3 << 0) + + +// standard request codes (bRequest) + +#define RQ_GET_STATUS 0 +#define RQ_CLEAR_FEATURE 1 +#define RQ_RESERVED_2 2 +#define RQ_SET_FEATURE 3 +#define RQ_RESERVED_4 4 +#define RQ_SET_ADDRESS 5 +#define RQ_GET_DESCR 6 +#define RQ_SET_DESCR 7 +#define RQ_GET_CONFIG 8 +#define RQ_SET_CONFIG 9 +#define RQ_GET_INTERFACE 10 +#define RQ_SET_INTERFACE 11 +#define RQ_SYNCH_FRAME 12 + +// standard descriptor types + +#define DT_DEVICE 1 +#define DT_CONFIG 2 +#define DT_STRING 3 +#define DT_INTERFACE 4 +#define DT_ENDPOINT 5 +#define DT_DEVQUAL 6 +#define DT_OTHER_SPEED 7 +#define DT_INTERFACE_POWER 8 + +// standard feature selectors + +#define FS_ENDPOINT_HALT 0 // recip: endpoint +#define FS_DEV_REMOTE_WAKEUP 1 // recip: device +#define FS_TEST_MODE 2 // recip: device + +// Get Status device attributes + +#define bmGSDA_SELF_POWERED 0x01 +#define bmGSDA_REM_WAKEUP 0x02 + + +#endif /* _USB_REQUESTS_H_ */ Index: trunk/FirmwareFX2/hardware.h =================================================================== --- trunk/FirmwareFX2/hardware.h (revision 4) +++ trunk/FirmwareFX2/hardware.h (revision 4) @@ -0,0 +1,34 @@ +/*----------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _HARDWARE_H +#define _HARDWARE_H 1 + +extern void ProgIO_Init(void); +extern void ProgIO_Poll(void); +extern void ProgIO_Enable(void); +extern void ProgIO_Disable(void); +extern void ProgIO_Deinit(void); + +extern void ProgIO_Set_State(unsigned char d); +extern unsigned char ProgIO_Set_Get_State(unsigned char d); +extern void ProgIO_ShiftOut(unsigned char x); +extern unsigned char ProgIO_ShiftInOut(unsigned char x); + +#endif /* _HARDWARE_H */ + Index: trunk/FirmwareFX2/hw_basic.c =================================================================== --- trunk/FirmwareFX2/hw_basic.c (revision 4) +++ trunk/FirmwareFX2/hw_basic.c (revision 4) @@ -0,0 +1,278 @@ +/*----------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +#define HAVE_OE_LED 1 + +//----------------------------------------------------------------------------- + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB3 TDI; /* Port D.3 */ +#define bmTDIOE bmBIT0 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB2 TCK; /* Port D.2 */ +#define bmTCKOE bmBIT3 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB1 TMS; /* Port D.1 */ +#define bmTMSOE bmBIT2 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT1 +#define GetTDO(x) TDO + +//----------------------------------------------------------------------------- + +#ifdef HAVE_OE_LED + + sbit at 0xB4 OELED; /* Port D.4 */ + #define bmOELEDOE bmBIT7 + #define SetOELED(x) do{OELED=(x);}while(0) + +#else + + #define bmOELEDOE 0 + #define SetOELED(x) while(0){} + +#endif + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE|bmOELEDOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +// These aren't called anywhere in usbjtag.c, but I plan to do so... +void ProgIO_Enable(void) {} +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // set the CPU clock to 48MHz, enable clock output to FPGA + CPUCS = bmCLKOE | bmCLKSPD1; + + // Use external clock, use "Slave FIFO" mode for all pins + IFCONFIG = bmIFCFG1 | bmIFCFG0; + + // TDO input, others output + OED = (OED&~bmPROGINOE) | bmPROGOUTOE; +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.2 => nCE (only #ifdef HAVE_AS_MODE) + * d.3 => nCS (only #ifdef HAVE_AS_MODE) + * d.4 => TDI + * d.5 => LED / Output Enable + */ + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +#ifdef HAVE_OE_LED + SetOELED((d & bmBIT5) ? 1 : 0); +#endif +} + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return 2|GetTDO(); /* DATAOUT assumed high, no AS mode */ +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + + + Index: trunk/FirmwareFX2/readme-spi.txt =================================================================== --- trunk/FirmwareFX2/readme-spi.txt (revision 4) +++ trunk/FirmwareFX2/readme-spi.txt (revision 4) @@ -0,0 +1,31 @@ +==== SPI Master on FX2 ==== + +This firmware implements a SPI Master. + +The following pins on IOA are used : + +SCLK BIT0 +SDO BIT1 +SDI BIT3 +SS_N BIT7 + +There is only one slave select available (all other pins of IOA are being used +by used by bulk transfer control lines, and the other IOx aren't routed to the +fpga) + +By default, those lines are not enabled. + +Control of the SPI master is done through vendor commands. Those include: +- Output enable VEN_SPI_EN 0x96 +- Output disable VEN_SPI_DIS 0x97 +- Read VEN_SPI_RD 0x98 +- Write VEN_SPI_WR 0x99 + +spi specific code is in spi.c + +==== C code examples ==== +To be done + + + +--- 2008, Matthias P. Braendli Index: trunk/FirmwareFX2/readme.txt =================================================================== --- trunk/FirmwareFX2/readme.txt (revision 4) +++ trunk/FirmwareFX2/readme.txt (revision 4) @@ -0,0 +1,74 @@ +usb_jtag using Cypress FX2 chip +=============================== + +The code in this directory is for Cypress FX2 (e.g. CY7C68013A) and can be compiled with +the SDCC compiler (I tried version 2.6 as shipped with Ubuntu 6.10). Once I had a version +that could be compiled with Keil tools (until early 2007), but switched to SDCC because I +usually develop on a Linux host. + +No logic beside the FX2 itself and only a few external components are required for a basic +JTAG adapter. I don't have detailed schematics available; my test setup consists of a FX2 +on a custom board where it's directly connected to a Cyclone FPGA. + + ____________ + | | + | Cypress | + USB__| EZ-USB FX2 |__JTAG(TDI,TDO,TCK,TMS) + | CY7C68013A | + |____________| + __|__________ + | | + | 24 MHz XTAL | + |_____________| + + +Similar eval boards are now available from fpga4fun.com - the boards named +"Saxo-L" and "Xylo-EM" are pre-wired for use with an adapted version of my +code, while "Saxo" and "Xylo" can be used after soldering 4 extra wires: + + http://www.fpga4fun.com/board_Xylo.html + + +As is, the code assumes the following pin assignment: + + Port C.0: TDI + Port C.1: TDO + Port C.2: TCK + Port C.3: TMS + +Other assignments are possible; you'll have to adapt the definitions in hardware.h and maybe +in hardware.c, too. + +The USB identification data (vendor/product ID, strings, ...) can be modified in dscr.a51. My +firmware emulates the 128 byte EEPROM that usually holds configuration data for the FT245 and +which can be read from the host; its content is computed from the data in dscr.a51 as well. + +The WAKEUP pin should be high for the re-numeration to work reliably (thanks Jean/fpga4fun!) + +From this release on, there is new code to support running in the "Xilinx +Platform Cable USB". If you select HARDWARE=hw_xpcu_i or hw_xpcu_x at the top +of the Makefile, a firmware for the XPCU will be built. I've tested this only +with unmodified CPLD version 18 (0x12) on a Spartan-3E starter kit, as it was +programmed by my WebPack 8.2i. The code needs optimization; yet it is merely a +proof of concept. + + hw_xpcu_i: Access "internal" chain (the XPCU CPLD, IC3, itself) + hw_xpcu_x: Access "external" chain (the Spartan 3E, PROM, etc.) + +Changes since previous release on 2007-01-28: + - Initial suppport for running on Xilinx XPCU. + - New FX2 code, based on USRP2 from the GNU Radio Project; + - Firmware can now be compiled using SDCC 2.6. No more Keil support. + - EEPROM content is automatically computed from descriptors, including checksum. + +Changes since initial release on 2006-04-23: + - added this readme.txt + - reorganized my project folder: diff is now created from Subversion repository + - stripped *.dist extension from eeprom.c and dscr.a51 + - added unique proper product and vendor ID (thanks to Antti Lukats!) + - fixed checksum in eeprom.c + - added comments about AS/PS mode pins in usbjtag.c + + + + Index: trunk/FirmwareFX2/spi.c =================================================================== --- trunk/FirmwareFX2/spi.c (revision 4) +++ trunk/FirmwareFX2/spi.c (revision 4) @@ -0,0 +1,212 @@ +/* -*- c++ -*- */ +/* + * Copyright 2004,2006 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + * + * + * Modified by Matthias P. Braendli +*/ + +#include "spi.h" +#include "fx2regs.h" +#include "fx2utils.h" + +void +init_spi (void) +{ + SPI |= bmSS; /* active low, disable slave */ + bitS_OUT = 0; /* idle state has CLK = 0 */ +} + +unsigned char +spi_read (unsigned char header_hi, unsigned char header_lo, + unsigned char format, unsigned char address, + xdata unsigned char *buf, unsigned char len) +{ + SPI &= ~bmSS; // enable slave select + + spi_write_byte_msb(address); // send destination periph address + + switch (format & SPI_FMT_HDR_MASK){ + case SPI_FMT_HDR_0: + break; + case SPI_FMT_HDR_1: + spi_write_byte_msb (header_lo); + break; + case SPI_FMT_HDR_2: + spi_write_byte_msb (header_hi); + spi_write_byte_msb (header_lo); + break; + default: + return 1; // error + } + if (len != 0) + spi_read_bytes_msb (buf, len); + + + SPI |= bmSS; /* active low, disable slave */ + + return 0; // success +} + + +unsigned char +spi_write (unsigned char header_hi, unsigned char header_lo, + unsigned char format, unsigned char address, + const xdata unsigned char *buf, unsigned char len) +{ + SPI &= ~bmSS; // enable slave select + + spi_write_byte_msb(address); // send destination periph address + + switch (format & SPI_FMT_HDR_MASK){ + case SPI_FMT_HDR_0: + break; + case SPI_FMT_HDR_1: + spi_write_byte_msb (header_lo); + break; + case SPI_FMT_HDR_2: + spi_write_byte_msb (header_hi); + spi_write_byte_msb (header_lo); + break; + default: + SPI |= bmSS; /* active low, disable slave */ + return 1; // error + } + + if (len != 0) + spi_write_bytes_msb (buf, len); + + SPI |= bmSS; /* active low, disable slave */ + return 0; // success +} + +// ---------------------------------------------------------------- + +void +spi_write_byte_msb (unsigned char v) +{ + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; + + v = (v << 1) | (v >> 7); // rotate left (MSB into bottom bit) + bitS_OUT = v & 0x1; + bitS_CLK = 1; + bitS_CLK = 0; +} + +void +spi_write_bytes_msb (const xdata unsigned char *buf, unsigned char len) +{ + while (len-- != 0){ + spi_write_byte_msb (*buf++); + } +} + +unsigned char +spi_read_byte_msb (void) _naked +{ + _asm + clr a + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + setb _bitS_CLK + mov c, _bitS_IN + rlc a + clr _bitS_CLK + + mov dpl,a + ret + _endasm; +} + +void +spi_read_bytes_msb (xdata unsigned char *buf, unsigned char len) +{ + while (len-- != 0){ + *buf++ = spi_read_byte_msb (); + } +} + Index: trunk/FirmwareFX2/spi.h =================================================================== --- trunk/FirmwareFX2/spi.h (revision 4) +++ trunk/FirmwareFX2/spi.h (revision 4) @@ -0,0 +1,74 @@ +/* -*- c++ -*- */ +/* + * Copyright 2004 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_SPI_H +#define INCLUDED_SPI_H + +// FX2 is SPI bus master going to fpga +#define SPI IOA +#define SPI_OE OEA +#define bmSPI_OE 0x8B // bits on PA +#define VEN_SPI_EN 0x96 // vendor commands +#define VEN_SPI_DIS 0x97 +#define VEN_SPI_RD 0x98 +#define VEN_SPI_WR 0x99 + +#define bmSCLK bmBIT0 // sclk on port A +#define bmSDO bmBIT1 // SPI MOSI +#define bmSDI bmBIT3 // SPI MISO +#define bmSS bmBIT7 // Slave select +#define SPI_FMT_HDR_MASK (3 << 5) +#define SPI_FMT_HDR_0 (0 << 5) // 0 header bytes +#define SPI_FMT_HDR_1 (1 << 5) // 1 header byte +#define SPI_FMT_HDR_2 (2 << 5) // 2 header bytes + +sbit at 0x80+0 bitS_CLK; // 0x80 is the bit address of IOA +sbit at 0x80+1 bitS_OUT; // out from FX2 point of view +sbit at 0x80+3 bitS_IN; // in from FX2 point of view + +void init_spi (void); // one time call to init + +// returns non-zero if successful, else 0 +unsigned char +spi_read (unsigned char header_hi, unsigned char header_lo, + unsigned char enables, unsigned char format, + xdata unsigned char *buf, unsigned char len); + +// returns non-zero if successful, else 0 +unsigned char +spi_write (unsigned char header_hi, unsigned char header_lo, + unsigned char enables, unsigned char format, + const xdata unsigned char *buf, unsigned char len); + +void +spi_write_byte_msb (unsigned char v); + +void +spi_write_bytes_msb (const xdata unsigned char *buf, unsigned char len); + +unsigned char +spi_read_byte_msb (void) _naked; + +void +spi_read_bytes_msb (xdata unsigned char *buf, unsigned char len); + +#endif /* INCLUDED_SPI_H */ Index: trunk/FirmwareFX2/startup.a51 =================================================================== --- trunk/FirmwareFX2/startup.a51 (revision 4) +++ trunk/FirmwareFX2/startup.a51 (revision 4) @@ -0,0 +1,78 @@ +;;; -*- asm -*- +;;; +;;;----------------------------------------------------------------------------- +;;; Startup code +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; The default external memory initialization provided by sdcc is not +;;; appropriate to the FX2. This is derived from the sdcc code, but uses +;;; the FX2 specific _MPAGE sfr. + + + ;; .area XISEG (XDATA) ; the initialized external data area + ;; .area XINIT (CODE) ; the code space consts to init XISEG + .area XSEG (XDATA) ; zero initialized xdata + .area USBDESCSEG (XDATA) ; usb descriptors + + + .area CSEG (CODE) + + ;; sfr that sets upper address byte of MOVX using @r0 or @r1 + _MPAGE = 0x0092 + +__sdcc_external_startup:: + ;; This system is now compiled with the --no-xinit-opt + ;; which means that any initialized XDATA is handled + ;; inline by code in the GSINIT segs emitted for each file. + ;; + ;; We zero XSEG and all of the internal ram to ensure + ;; a known good state for uninitialized variables. + +; _mcs51_genRAMCLEAR() start + mov r0,#l_XSEG + mov a,r0 + orl a,#(l_XSEG >> 8) + jz 00002$ + mov r1,#((l_XSEG + 255) >> 8) + mov dptr,#s_XSEG + clr a + +00001$: movx @dptr,a + inc dptr + djnz r0,00001$ + djnz r1,00001$ + + ;; We're about to clear internal memory. This will overwrite + ;; the stack which contains our return address. + ;; Pop our return address into DPH, DPL +00002$: pop dph + pop dpl + + ;; R0 and A contain 0. This loop will execute 256 times. + ;; + ;; FWIW the first iteration writes direct address 0x00, + ;; which is the location of r0. We get lucky, we're + ;; writing the correct value (0) + +00003$: mov @r0,a + djnz r0,00003$ + + push dpl ; restore our return address + push dph + + mov dpl,#0 ; indicate that data init is still required + ret Index: trunk/FirmwareFX2/usbjtag.c =================================================================== --- trunk/FirmwareFX2/usbjtag.c (revision 4) +++ trunk/FirmwareFX2/usbjtag.c (revision 4) @@ -0,0 +1,541 @@ +/*----------------------------------------------------------------------------- + * Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter + *----------------------------------------------------------------------------- + * Copyright (C) 2005..2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * Check hardware.h/.c if it matches your hardware configuration (e.g. pinout). + * Changes regarding USB identification should be made in product.inc! + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "isr.h" +#include "timer.h" +#include "delay.h" +#include "fx2regs.h" +#include "fx2utils.h" +#include "usb_common.h" +#include "usb_descriptors.h" +#include "usb_requests.h" + +#include "syncdelay.h" + +#include "eeprom.h" +#include "hardware.h" + +#include "spi.h" + +//----------------------------------------------------------------------------- +// Define USE_MOD256_OUTBUFFER: +// Saves about 256 bytes in code size, improves speed a little. +// A further optimization could be not to use an extra output buffer at +// all, but to write directly into EP1INBUF. Not implemented yet. When +// downloading large amounts of data _to_ the target, there is no output +// and thus the output buffer isn't used at all and doesn't slow down things. + +#define USE_MOD256_OUTBUFFER 1 + +//----------------------------------------------------------------------------- +// Global data + +typedef bit BOOL; +#define FALSE 0 +#define TRUE 1 +static BOOL Running; +static BOOL WriteOnly; + +static BYTE ClockBytes; +static WORD Pending; + +#ifdef USE_MOD256_OUTBUFFER + static BYTE FirstDataInOutBuffer; + static BYTE FirstFreeInOutBuffer; +#else + static WORD FirstDataInOutBuffer; + static WORD FirstFreeInOutBuffer; +#endif + +#ifdef USE_MOD256_OUTBUFFER + /* Size of output buffer must be exactly 256 */ + #define OUTBUFFER_LEN 0x100 + /* Output buffer must begin at some address with lower 8 bits all zero */ + xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN]; +#else + #define OUTBUFFER_LEN 0x200 + static xdata BYTE OutBuffer[OUTBUFFER_LEN]; +#endif + +//----------------------------------------------------------------------------- + +void usb_jtag_init(void) // Called once at startup +{ + WORD tmp; + + Running = FALSE; + ClockBytes = 0; + Pending = 0; + WriteOnly = TRUE; + FirstDataInOutBuffer = 0; + FirstFreeInOutBuffer = 0; + + ProgIO_Init(); + + ProgIO_Enable(); + + // Make Timer2 reload at 100 Hz to trigger Keepalive packets + tmp = 65536 - ( 48000000 / 12 / 100 ); + RCAP2H = tmp >> 8; + RCAP2L = tmp & 0xFF; + CKCON = 0; // Default Clock + T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock. + + // Enable Autopointer + EXTACC = 1; // Enable + APTR1FZ = 1; // Don't freeze + APTR2FZ = 1; // Don't freeze + + // define endpoint configuration + + REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer + FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all, reset all FIFOS + FIFORESET = 0x02; SYNCDELAY; // Reset FIFO 2 + FIFORESET = 0x04; SYNCDELAY; // Reset FIFO 4 + FIFORESET = 0x06; SYNCDELAY; // Reset FIFO 6 + FIFORESET = 0x08; SYNCDELAY; // Reset FIFO 8 + FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour + + EP1OUTCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk + EP1INCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk + + EP2FIFOCFG = 0x00; SYNCDELAY; // Endpoint 2 + EP2CFG = 0xA2; SYNCDELAY; // Endpoint 2 Valid, Out, Type Bulk, Double buffered + + EP4FIFOCFG = 0x00; SYNCDELAY; // Endpoint 4 not used + EP4CFG = 0xA0; SYNCDELAY; // Endpoint 4 not used + + REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer, enable auto-arming when AUTOOUT is switched to 1 + + EP6CFG = 0xA2; SYNCDELAY; // Out endpoint, Bulk, Double buffering + EP6FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming + EP6FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; // Endpoint 6 used for user communicationn, auto commitment, 16 bits data bus + + EP8CFG = 0xE0; SYNCDELAY; // In endpoint, Bulk + EP8FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming + EP8FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY; // Endpoint 8 used for user communication, auto commitment, 16 bits data bus + + EP8AUTOINLENH = 0x00; SYNCDELAY; // Size in bytes of the IN data automatically commited (64 bytes here, but changed dynamically depending on the connection) + EP8AUTOINLENL = 0x40; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet + + // Out endpoints do not come up armed + // Since the defaults are double buffered we must write dummy byte counts twice + EP2BCL = 0x80; SYNCDELAY; // Arm EP2OUT by writing byte count w/skip.= + EP4BCL = 0x80; SYNCDELAY; + EP2BCL = 0x80; SYNCDELAY; // Arm EP4OUT by writing byte count w/skip.= + EP4BCL = 0x80; SYNCDELAY; + + // JTAG from FX2 enabled by default + IOC |= (1 << 7); + + // Put the system in high speed by default (REM: USB-Blaster is in full speed) + // This can be changed by vendor commands + CT1 &= ~0x02; +} + +void OutputByte(BYTE d) +{ +#ifdef USE_MOD256_OUTBUFFER + OutBuffer[FirstFreeInOutBuffer] = d; + FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF; +#else + OutBuffer[FirstFreeInOutBuffer++] = d; + if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0; +#endif + Pending++; +} + +//----------------------------------------------------------------------------- +// usb_jtag_activity does most of the work. It now happens to behave just like +// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's +// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte +// shift mode. It starts in Bit banging mode. While bytes are received +// from the host on EP2OUT, each byte B of them is processed as follows: +// +// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here. +// Support for these would be required for AS/PS mode and isn't too complicated, +// but I haven't had the time yet. +// +// Bit banging mode: +// +// 1. Remember bit 6 (0x40) in B as the "Read bit". +// +// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming +// X bytes ( X := B & 0x3F ), and don't do anything else now. +// +// 3. Otherwise, set the JTAG signals as follows: +// TCK/DCLK high if bit 0 was set (0x01), otherwise low +// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low +// nCE high if bit 2 was set (0x04), otherwise low +// nCS high if bit 3 was set (0x08), otherwise low +// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low +// Output Enable/LED active if bit 5 was set (0x20), otherwise low +// +// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and +// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the +// output FIFO _to_ the host (the code here reads TDO only and assumes +// DATAOUT=1) +// +// Byte shift mode: +// +// 1. Load shift register with byte from host +// +// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51) +// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT +// 2b) Rotate shift register through carry bit +// 2c) TDI := Carry bit +// 2d) Raise TCK, then lower TCK. +// +// 3. If "Read bit" was set when switching into byte shift mode, +// record the shift register content and put it into the FIFO +// _to_ the host. +// +// Some more (minor) things to consider to emulate the FT245BM: +// +// a) The FT245BM seems to transmit just packets of no more than 64 bytes +// (which perfectly matches the USB spec). Each packet starts with +// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows +// might show a number of packets to you as if it was a large transfer +// because of the way that Windows understands it: it _is_ a large +// transfer until terminated with an USB packet smaller than 64 byte. +// +// b) The Windows driver expects to get some data packets (with at least +// the two leading bytes 0x31,0x60) immediately after "resetting" the +// FT chip and then in regular intervals. Otherwise a blue screen may +// appear... In the code below, I make sure that every 10ms there is +// some packet. +// +// c) Vendor specific commands to configure the FT245 are mostly ignored +// in my code. Only those for reading the EEPROM are processed. See +// DR_GetStatus and DR_VendorCmd below for my implementation. +// +// All other TD_ and DR_ functions remain as provided with CY3681. +// +//----------------------------------------------------------------------------- + +void usb_jtag_activity(void) // Called repeatedly while the device is idle +{ + if(!Running) return; + + ProgIO_Poll(); + + if(!(EP1INCS & bmEPBUSY)) + { + if(Pending > 0) + { + BYTE o, n; + + AUTOPTRH2 = MSB( EP1INBUF ); + AUTOPTRL2 = LSB( EP1INBUF ); + + XAUTODAT2 = 0x31; + XAUTODAT2 = 0x60; + + if(Pending > 0x3E) { n = 0x3E; Pending -= n; } + else { n = Pending; Pending = 0; }; + + o = n; + +#ifdef USE_MOD256_OUTBUFFER + APTR1H = MSB( OutBuffer ); + APTR1L = FirstDataInOutBuffer; + while(n--) + { + XAUTODAT2 = XAUTODAT1; + APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer + }; + FirstDataInOutBuffer = APTR1L; +#else + APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) ); + APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) ); + while(n--) + { + XAUTODAT2 = XAUTODAT1; + + if(++FirstDataInOutBuffer >= OUTBUFFER_LEN) + { + FirstDataInOutBuffer = 0; + APTR1H = MSB( OutBuffer ); + APTR1L = LSB( OutBuffer ); + }; + }; +#endif + SYNCDELAY; + EP1INBC = 2 + o; + TF2 = 1; // Make sure there will be a short transfer soon + } + else if(TF2) + { + EP1INBUF[0] = 0x31; + EP1INBUF[1] = 0x60; + SYNCDELAY; + EP1INBC = 2; + TF2 = 0; + }; + }; + + if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F)) + { + WORD i, n = EP2BCL|EP2BCH<<8; + + APTR1H = MSB( EP2FIFOBUF ); + APTR1L = LSB( EP2FIFOBUF ); + + for(i=0;i 0) + { + WORD m; + + m = n-i; + if(ClockBytes < m) m = ClockBytes; + ClockBytes -= m; + i += m; + + /* Shift out 8 bits from d */ + + if(WriteOnly) /* Shift out 8 bits from d */ + { + while(m--) ProgIO_ShiftOut(XAUTODAT1); + } + else /* Shift in 8 bits at the other end */ + { + while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1)); + } + } + else + { + BYTE d = XAUTODAT1; + WriteOnly = (d & bmBIT6) ? FALSE : TRUE; + + if(d & bmBIT7) + { + /* Prepare byte transfer, do nothing else yet */ + + ClockBytes = d & 0x3F; + } + else + { + if(WriteOnly) + ProgIO_Set_State(d); + else + OutputByte(ProgIO_Set_Get_State(d)); + }; + i++; + }; + }; + + SYNCDELAY; + EP2BCL = 0x80; // Re-arm endpoint 2 + }; +} + +//----------------------------------------------------------------------------- +// Handler for Vendor Requests ( +//----------------------------------------------------------------------------- + +unsigned char app_vendor_cmd(void) +{ + // because of fx2/usb_common.c, this code returns nonzero on success + // OUT requests. Pretend we handle them all... + + if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT) + { + if(bRequest == RQ_GET_STATUS) + { + Running = 1; + } + + if (bRequest == VEN_SPI_WR) // 0x99 + { + // get EP0 data + EP0BCL = 0; // arm EP0 for OUT xfer. This sets the busy bit + + while (EP0CS & bmEPBUSY) // wait for busy to clear + ; + + // head_hi, head_l , format , address, *buf , len + return !spi_write (wValueH, wValueL, wIndexH, wIndexL, EP0BUF, EP0BCL); + } + + + return 1; + } + + // IN requests. + + // change USB speed + if (bRequest == 0x91) + { + if (wIndexL == 0) // high speed + { + CT1 &= ~0x02; + fx2_renumerate(); // renumerate + } + else // full speed + { + CT1 |= 0x02; + fx2_renumerate(); // renumerate + } + } + + // change JTAG enable + if (bRequest == 0x92) + { + if (wIndexL == 0) // FX2 is master of JTAG + { + IOC |= (1 << 7); + } + else // external connector is master of JTAG + { + IOC &= ~(1 << 7); + } + } + // change synchronous/asynchronous mode + if (bRequest == 0x93) + { + if(IFCONFIG & bmASYNC) + { + IFCONFIG &= ~bmASYNC; + } + else + { + IFCONFIG |= bmASYNC; + } + } + + if (bRequest == 0x94) // change to synchronous mode + { + IFCONFIG &= ~bmASYNC; + } + + if (bRequest == VEN_SPI_EN) // 0x96 + { + SPI_OE |= bmSPI_OE; // PA.0,1,3,7 output enable + init_spi(); + EP0BUF[0] = 0; + EP0BUF[1] = 0; + } + + if (bRequest == VEN_SPI_DIS) // 0x97 + { + SPI_OE &= ~bmSPI_OE; // PA.0,1,3,7 output disable + EP0BUF[0] = 0x42; + EP0BUF[1] = 0x43; + EP0BUF[2] = 0x42; + EP0BUF[3] = 0x43; + EP0BCH = 0; + EP0BCL = wLengthL; +// EP0CS |= bmHSNAK; // Bram + return 1; + } + + if (bRequest == VEN_SPI_RD) // 0x98 + { + // header_H,header_L, format, address, *buf , len + if (spi_read (wValueH, wValueL, wIndexH, wIndexL, EP0BUF, wLengthL)) + return 0; + + EP0BCH = 0; + EP0BCL = wLengthL; + return 1; + } + + if (bRequest == 0x95) // For debugging purposes + { + + SPI &= ~bmSS; // enable slave select + + spi_write_byte_msb(wValueL); // address + spi_write_byte_msb(wIndexL); // header + EP0BUF[0] = spi_read_byte_msb(); // read back value from slave + + SPI |= bmSS; /* active low, disable slave */ + + EP0BCH = 0; + EP0BCL = 1; // Arm the EP + return 1; + + /*static xdata unsigned char buf[2]; + buf[0] = 0xFF; + buf[1] = 0x10; + spi_read(0x00, wValueL, SPI_FMT_HDR_1, wValueH, buf, 0); + //spi_write_byte_msb(wValueL); + EP0BUF[0] = 0x51; + EP0BUF[1] = wValueL; + EP0BCH = 0; + EP0BCL = wLengthL; + return 1;*/ + } + + if(bRequest == 0x90) + { + BYTE addr = (wIndexL<<1) & 0x7F; + EP0BUF[0] = eeprom[addr]; + EP0BUF[1] = eeprom[addr+1]; + } + else + { + // dummy data + EP0BUF[0] = 0x36; + EP0BUF[1] = 0x83; + } + + EP0BCH = 0; + EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer + //EP0CS |= bmHSNAK; // Bram + + return 1; +} + +//----------------------------------------------------------------------------- + +static void main_loop(void) +{ + while(1) + { + if(usb_setup_packet_avail()) usb_handle_setup_packet(); + usb_jtag_activity(); + } +} + +//----------------------------------------------------------------------------- + +void main(void) +{ + EA = 0; // disable all interrupts + + usb_jtag_init(); + eeprom_init(); + setup_autovectors (); + usb_install_handlers (); + + + EA = 1; // enable interrupts + + fx2_renumerate(); // simulates disconnect / reconnect + + main_loop(); +} + + + + Index: trunk/FirmwareFX2/usbjtag.hex =================================================================== --- trunk/FirmwareFX2/usbjtag.hex (revision 4) +++ trunk/FirmwareFX2/usbjtag.hex (revision 4) @@ -0,0 +1,306 @@ +:0600000002117702006B03 +:03000B0002006B85 +:0300130002006B7D +:03001B0002006B75 +:0300230002006B6D +:03002B0002006B65 +:0300330002006B5D +:03003B0002006B55 +:0300430002006B4D +:03004B0002006B45 +:0300530002006B3D +:03005B0002006B35 +:0300630002006B2D +:01006B003262 +:1000800002006B0002006B0002006B0002006B00BC +:1000900002006B0002006B0002006B0002006B00AC +:1000A00002006B0002006B0002006B0002006B009C +:0800B00002006B0002006B006E +:1001000002006B0002006B0002006B0002006B003B +:1001100002006B0002006B0002006B0002006B002B +:1001200002006B0002006B0002006B0002006B001B +:1001300002006B0002006B0002006B0002006B000B +:1001400002006B0002006B0002006B0002006B00FB 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+;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; N.B. This object module must come first in the list of modules + + .module vectors + +;;; ---------------------------------------------------------------- +;;; standard FX2 interrupt vectors +;;; ---------------------------------------------------------------- + + .area CSEG (CODE) + .area GSINIT (CODE) + .area CSEG (CODE) +__standard_interrupt_vector:: +__reset_vector:: + ljmp s_GSINIT + + ;; 13 8-byte entries. We point them all at __isr_nop + ljmp __isr_nop ; 3 bytes + .ds 5 ; + 5 = 8 bytes for vector slot + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + +__isr_nop:: + reti + +;;; ---------------------------------------------------------------- +;;; the FIFO/GPIF autovector. 14 4-byte entries. +;;; must start on a 128 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0080 + +__fifo_gpif_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + + +;;; ---------------------------------------------------------------- +;;; the USB autovector. 32 4-byte entries. +;;; must start on a 256 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0100 + +__usb_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop