Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 34)
+++ trunk/MultiChannelUSB/Paella.v	(revision 35)
@@ -72,10 +72,8 @@
 	reg				led_reg;	
 //	assign	LED			=	counter[24];
-//	assign	LED			=	~usb_fifo_rx_empty;
 	assign	LED			=	led_reg;
-//	assign	LED			=	usb_fifo_led;
 
 	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
-	wire			usb_fifo_aclr, usb_fifo_led;
+	wire			usb_fifo_aclr;
 	reg				usb_fifo_tx_wrreq;
 	reg				usb_fifo_rx_rdreq;
@@ -104,18 +102,15 @@
 
 		.tx_full(usb_fifo_tx_full),
-//		.tx_wrreq(usb_fifo_tx_wrreq),
-//		.tx_wrreq((~usb_fifo_tx_full) & (state1 == 3'd5)),
 		.tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
 		.tx_data(usb_fifo_tx_data),
-//		.tx_data(osc_counter),
 
 		.rx_empty(usb_fifo_rx_empty),
 		.rx_rdreq(usb_fifo_rx_rdreq),
-		.rx_q(usb_fifo_rx_data),
-		
-		.led(usb_fifo_led)
+		.rx_q(usb_fifo_rx_data)
 	);
 	
-	reg		[10:0]	osc_counter;	
+	reg		[10:0]	tst_counter;	
+
+	reg		[9:0]	osc_counter;	
 	reg 			osc_reset;
 	reg 			osc_byte_num;
@@ -129,5 +124,5 @@
 	wire	[31:0]	hst_q;
 
-	reg		[2:0]	state0, state1, state2;
+	reg		[3:0]	state0, state1, state2;
 	reg				adc_fifo_rdreq;
 	wire			adc_fifo_rdempty;
@@ -194,5 +189,5 @@
 					adc_fifo_rdreq <= 1'b1;
 					adc_data_ready <= 1'b1;
-					state0 <= 3'd2;
+					state0 <= 4'd2;
 				end
 			end
@@ -202,17 +197,17 @@
 				adc_fifo_rdreq <= 1'b0;
 				adc_data_ready <= 1'b0;
-				state0 <= 3'd1;
+				state0 <= 4'd1;
 			end
 
 			default:
 			begin
-				state0 <= 3'd1;
+				state0 <= 4'd1;
 			end
 		endcase
 	end
-/*
+
 	always @(posedge CLK_50MHz)
 	begin
-		case (state1)
+		case(state1)
 			1:
 			begin
@@ -221,5 +216,5 @@
 				hst_reset <= 1'b0;
 				osc_reset <= 1'b0;
-				state1 <= 3'd2;
+				state1 <= 4'd2;
 			end
 
@@ -233,17 +228,17 @@
 						begin
 							hst_reset <= 1'b1;
-							state1 <= 3'd1;
+							state1 <= 4'd1;
 						end
 						8'h31:
 						begin
-							led_reg <= 1'b1;
 							hst_addr <= 12'd0;
 							hst_byte_num <= 2'd0;	
-							state1 <= 3'd3;
+							state1 <= 4'd3;
 						end
 						8'h32:
 						begin
+							led_reg <= 1'b1;
 							osc_reset <= 1'b1;
-							state1 <= 3'd1;
+							state1 <= 4'd1;
 						end
 						8'h33:
@@ -253,16 +248,31 @@
 							osc_counter <= 10'd0;
 							osc_byte_num <= 1'd0;	
-							state1 <= 3'd4;
-						end
-
+							state1 <= 4'd6;
+						end
+						8'h34:
+						begin
+							led_reg <= 1'b1;
+							state1 <= 4'd1;
+						end
+						8'h35:
+						begin
+							led_reg <= 1'b0;
+							tst_counter <= 11'd0;	
+							state1 <= 4'd9;
+						end
 					endcase
 				end
 			end
 
+			// hst transfer
 			3:
 			begin
-				// hst transfer
-				usb_fifo_rx_rdreq <= 1'b0;
-				usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
+				usb_fifo_tx_data <= hst_q[7:0];
+				usb_fifo_tx_wrreq <= 1'b1;
+				hst_byte_num <= 2'd1;
+				state1 <= 4'd4;
+			end
+			4:
+			begin
 				if (~usb_fifo_tx_full)
 				begin
@@ -273,169 +283,102 @@
 						2'd3: usb_fifo_tx_data <= hst_q[31:24];
 					endcase
-					
 					if ((&hst_byte_num) & (&hst_addr))
 					begin
-						state1 <= 3'd1;
-					end
-					else if (&hst_byte_num)
-					begin
-						hst_addr <= hst_addr + 12'd1;
-					end
-
-					hst_byte_num <= hst_byte_num + 2'd1;				
-				end
-			end
-
-			4:
-			begin
-				usb_fifo_rx_rdreq <= 1'b0;
-				usb_fifo_tx_wrreq <= 1'b0;
-				usb_fifo_tx_data <= osc_counter;
-			    state1 <= 3'd5;
-			end
-
+						state1 <= 4'd5;
+					end
+					else
+					begin
+						if (&hst_byte_num)
+						begin
+							hst_addr <= hst_addr + 12'd1;
+						end
+						hst_byte_num <= hst_byte_num + 2'd1;
+					end
+				end
+			end
 			5:
 			begin
 				if (~usb_fifo_tx_full)
 				begin
-					usb_fifo_tx_wrreq <= 1'b1;
-					state1 <= 3'd6;
-				end
-			end
-
+					usb_fifo_tx_wrreq <= 1'b0;
+					state1 <= 4'd1;
+				end
+			end
+
+			// osc transfer
 			6:
 			begin
-				usb_fifo_tx_wrreq <= 1'b0;
-				if (&osc_counter)
-				begin
-					state1 <= 3'd1;
-				end
-				else
-				begin
-					osc_counter <= osc_counter + 11'd1;
-					state1 <= 3'd4;
-				end
-			end
-
-			4:
-			begin
-				// osc transfer
-				usb_fifo_rx_rdreq <= 1'b0;
-				usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
-				if(~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_data <= osc_counter;
-					osc_counter <= osc_counter + 11'd1;
-					if (&osc_counter) state1 <= 3'd1;
-
+				usb_fifo_tx_data <= osc_q[7:0];
+				usb_fifo_tx_wrreq <= 1'b1;
+				osc_byte_num <= 1'd1;
+				state1 <= 4'd7;
+			end
+			7:
+			begin
+				if (~usb_fifo_tx_full)
+				begin
 					case (osc_byte_num)
 						1'd0: usb_fifo_tx_data <= osc_q[7:0];
 						1'd1: usb_fifo_tx_data <= osc_q[15:8];
 					endcase
-
-					if ((osc_byte_num) & (&osc_counter))
-					begin
-						state1 <= 3'd1;
-					end
-					else if (osc_byte_num)
-					begin
-						osc_addr <= osc_addr + 10'd1;
-						osc_counter <= osc_counter + 10'd1;
-					end
-
-					osc_byte_num <= ~osc_byte_num;				
-
-				end
-			end
-
+					if ((&osc_byte_num) & (&osc_counter))
+					begin
+						state1 <= 4'd8;
+					end
+					else
+					begin
+						if (&osc_byte_num)
+						begin
+							osc_addr <= osc_addr + 10'd1;
+							osc_counter <= osc_counter + 10'd1;
+						end
+						osc_byte_num <= osc_byte_num + 1'd1;
+					end
+				end
+			end
+			8:
+			begin
+				if (~usb_fifo_tx_full)
+				begin
+					usb_fifo_tx_wrreq <= 1'b0;
+					state1 <= 4'd1;
+				end
+			end
+			// tst transfer
+			9:
+			begin
+				usb_fifo_tx_data <= tst_counter;
+				usb_fifo_tx_wrreq <= 1'b1;
+				tst_counter <= tst_counter + 11'd1;
+				state1 <= 4'd10;
+			end
+			10:
+			begin
+				if (~usb_fifo_tx_full)
+				begin
+					usb_fifo_tx_data <= tst_counter;
+					if (tst_counter == 11'd0) //(&osc_counter)
+					begin
+						state1 <= 4'd11;
+					end
+					else
+					begin
+						tst_counter <= tst_counter + 11'd1;
+					end
+				end
+			end
+			11:
+			begin
+				if (~usb_fifo_tx_full)
+				begin
+					usb_fifo_tx_wrreq <= 1'b0;
+					state1 <= 4'd1;
+				end
+			end
+						
 			default:
 			begin
-				// default state is the first one
-				state1 <= 3'd1;
-			end
-		endcase
-	end
-
-*/
-	always @(posedge CLK_50MHz)
-	begin
-		case(state1)
-			1:
-			begin
-				usb_fifo_rx_rdreq <= 1'b0;
-				usb_fifo_tx_wrreq <= 1'b0;
-				hst_reset <= 1'b0;
-				osc_reset <= 1'b0;
-				state1 <= 3'd2;
-			end
-
-			2: 
-			begin
-				usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
-				if (~usb_fifo_rx_empty)
-				begin
-					case (usb_fifo_rx_data)
-						8'h30:
-						begin
-							hst_reset <= 1'b1;
-							state1 <= 3'd1;
-						end
-						8'h31:
-						begin
-							hst_addr <= 12'd0;
-							hst_byte_num <= 2'd0;	
-							state1 <= 3'd3;
-						end
-						8'h32:
-						begin
-							led_reg <= 1'b1;
-							osc_reset <= 1'b1;
-							state1 <= 3'd1;
-						end
-						8'h33:
-						begin
-							led_reg <= 1'b0;
-							osc_addr <= osc_start_addr;
-							osc_counter <= 11'd0;
-							osc_byte_num <= 1'd0;	
-							state1 <= 3'd4;
-						end
-
-					endcase
-				end
-			end
-			4:
-			begin
-				usb_fifo_tx_data <= osc_counter;
-				usb_fifo_tx_wrreq <= 1'b1;
-				osc_counter <= osc_counter + 11'd1;
-				state1 <= 3'd5;
-			end
-			5:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_data <= osc_counter;
-					if (osc_counter == 11'd0) //(&osc_counter)
-					begin
-						state1 <= 3'd6;
-					end
-					else
-					begin
-						osc_counter <= osc_counter + 11'd1;
-					end
-				end
-			end
-			6:
-			begin
-				if (~usb_fifo_tx_full)
-				begin
-					usb_fifo_tx_wrreq <= 1'b0;
-					state1 <= 3'd1;
-				end
-			end
-
-										
-			default: state1 <= 3'd1;
+				state1 <= 4'd1;
+			end
 		endcase
 	end
@@ -447,5 +390,5 @@
 			begin
 				adc_data <= 12'd0;
-				state2 <= 3'd2;
+				state2 <= 4'd2;
 			end
 			
@@ -453,5 +396,5 @@
 			begin
 				adc_data <= 12'd1024;
-				state2 <= 3'd3;
+				state2 <= 4'd3;
 			end
 
@@ -459,5 +402,5 @@
 			begin
 				adc_data <= 12'd2048;
-				state2 <= 3'd4;
+				state2 <= 4'd4;
 			end
 
@@ -465,5 +408,5 @@
 			begin
 				adc_data <= 12'd3072;
-				state2 <= 3'd5;
+				state2 <= 4'd5;
 			end
 
@@ -471,10 +414,10 @@
 			begin
 				adc_data <= 12'd4095;
-				state2 <= 3'd1;
+				state2 <= 4'd1;
 			end
 
 			default:
 			begin
-				state2 <= 3'd1;
+				state2 <= 4'd1;
 			end
 		endcase