Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 30)
+++ trunk/MultiChannelUSB/Paella.v	(revision 31)
@@ -70,6 +70,9 @@
 
 	reg		[31:0]	counter;	
+	reg				led_reg;	
 //	assign	LED			=	counter[24];
-	assign	LED			=	usb_fifo_rx_empty;
+//	assign	LED			=	~usb_fifo_rx_empty;
+	assign	LED			=	led_reg;
+//	assign	LED			=	usb_fifo_led;
 
 	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
@@ -103,6 +106,6 @@
 		.tx_full(usb_fifo_tx_full),
 		.rx_empty(usb_fifo_rx_empty),
-//		.led(usb_fifo_led),
-		.rx_data(usb_fifo_rx_data)
+		.rx_data(usb_fifo_rx_data),
+		.led(usb_fifo_led)
 	);
 	
@@ -216,7 +219,7 @@
 			2: 
 			begin
+				usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
 				if (~usb_fifo_rx_empty)
 				begin
-					usb_fifo_rx_rdreq <= 1'b1;
 					case (usb_fifo_rx_data)
 						8'h30:
@@ -227,4 +230,5 @@
 						8'h31:
 						begin
+							led_reg <= 1'b1;
 							hst_addr <= 12'd0;
 							hst_byte_num <= 2'd0;	
@@ -238,4 +242,5 @@
 						8'h33:
 						begin
+							led_reg <= 1'b0;
 							osc_addr <= osc_start_addr;
 							osc_counter <= 10'd0;
@@ -243,10 +248,7 @@
 							state1 <= 3'd4;
 						end
+
 					endcase
 				end
-				else
-				begin
-					usb_fifo_rx_rdreq <= 1'b0;
-				end				
 			end
 
@@ -254,8 +256,8 @@
 			begin
 				// hst transfer
+				usb_fifo_rx_rdreq <= 1'b0;
+				usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
 				if (~usb_fifo_tx_full)
 				begin
-					usb_fifo_tx_wrreq <= 1'b1;
-
 					case (hst_byte_num)
 						2'd0: usb_fifo_tx_data <= hst_q[7:0];
@@ -267,5 +269,4 @@
 					if (&hst_byte_num)
 					begin
-						hst_byte_num <= 2'd0;				
 						if (&hst_addr)
 						begin
@@ -277,12 +278,6 @@
 						end
 					end
-					else
-					begin
-						hst_byte_num <= hst_byte_num + 2'd1;				
-					end				
-				end
-				else
-				begin
-					usb_fifo_tx_wrreq <= 1'b0;
+
+					hst_byte_num <= hst_byte_num + 2'd1;				
 				end
 			end
@@ -291,8 +286,8 @@
 			begin
 				// osc transfer
+				usb_fifo_rx_rdreq <= 1'b0;
+				usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
 				if(~usb_fifo_tx_full)
 				begin
-					usb_fifo_tx_wrreq <= 1'b1;
-
 					case (osc_byte_num)
 						1'd0: usb_fifo_tx_data <= osc_q[7:0];
@@ -302,5 +297,4 @@
 					if (osc_byte_num)
 					begin
-						osc_byte_num <= 1'd0;				
 						if (&osc_counter)
 						begin
@@ -313,12 +307,6 @@
 						end
 					end
-					else
-					begin
-						osc_byte_num <= 1'd1;				
-					end										
-				end
-				else
-				begin
-					usb_fifo_tx_wrreq <= 1'b0;
+
+					osc_byte_num <= ~osc_byte_num;				
 				end
 			end
@@ -331,4 +319,5 @@
 		endcase
 	end
+
 /*
 	always @(posedge CLK_50MHz)
Index: trunk/MultiChannelUSB/usb_fifo.v
===================================================================
--- trunk/MultiChannelUSB/usb_fifo.v	(revision 30)
+++ trunk/MultiChannelUSB/usb_fifo.v	(revision 31)
@@ -11,17 +11,21 @@
 		input	wire	[7:0]	tx_data,
 		output	wire			tx_full, rx_empty,
-		output	wire	[7:0]	rx_data
+		output	wire	[7:0]	rx_data,
+		output	wire			led
 	);
 
 	// bidirectional data bus
-	wire			usb_wren;
-	wire	[7:0]	usb_datain = usb_data;
-	wire	[7:0]	usb_dataout;
+	reg				int_addr, int_wren, int_rden, int_wrreq, int_rdreq;
+	wire	[7:0]	int_datain = usb_data;
+	wire	[7:0]	int_dataout;
 
-	assign	usb_data = usb_wren ? usb_dataout : 8'bz;
+	assign	usb_data = int_wren ? int_dataout : 8'bz;
 
 	wire			rx_full, tx_empty;
+	wire			rx_ready, tx_ready;
 	reg		[8:0]	byte_counter;
 	reg		[4:0]	idle_counter;
+
+	assign	led = ~usb_empty;
 
 	fifo32x8 fifo_tx_unit (
@@ -29,8 +33,8 @@
 		.data(tx_data),
 		.rdclk(usb_clk),
-		.rdreq(usb_wrreq),
+		.rdreq(int_wrreq),
 		.wrclk(clk),
 		.wrreq(tx_wrreq),
-		.q(usb_dataout),
+		.q(int_dataout),
 		.rdempty(tx_empty),
 		.wrfull(tx_full));
@@ -38,15 +42,77 @@
 	fifo32x8 fifo_rx_unit (
 		.aclr(aclr),
-		.data(usb_datain),
+		.data(int_datain),
 		.rdclk(clk),
 		.rdreq(rx_rdreq),
 		.wrclk(usb_clk),
-		.wrreq(usb_rdreq),
+		.wrreq(int_rdreq),
 		.q(rx_data),
 		.rdempty(rx_empty),
 		.wrfull(rx_full));
+
+	assign	rx_ready = (~usb_empty) & (~rx_full);
+	assign	tx_ready = (~usb_full) & (~tx_empty);
 		
 	always @ (posedge usb_clk)
 	begin
+		casez ({rx_ready, tx_ready, int_addr, int_rden})
+			4'b00??: // idle
+			begin
+				int_addr <= 1'b0;
+				int_rden <= 1'b0;
+				int_wren <= 1'b0;
+				int_rdreq <= 1'b0;
+				int_wrreq <= 1'b0;
+			end
+			4'b1?1?: // set read addr
+			begin
+				int_addr <= 1'b0;
+				int_rden <= 1'b0;
+				int_wren <= 1'b0;
+				int_rdreq <= 1'b0;
+				int_wrreq <= 1'b0;
+			end
+			4'b1?00: // enable reads
+			begin
+				int_addr <= 1'b0;
+				int_rden <= 1'b1;
+				int_wren <= 1'b0;
+				int_rdreq <= 1'b0;
+				int_wrreq <= 1'b0;
+			end
+			4'b1?01: // read
+			begin
+				int_addr <= 1'b0;
+				int_rden <= 1'b1;
+				int_wren <= 1'b0;
+				int_rdreq <= 1'b1;
+				int_wrreq <= 1'b0;
+			end
+			4'b0101: // disable reads
+			begin
+				int_addr <= 1'b0;
+				int_rden <= 1'b0;
+				int_wren <= 1'b0;
+				int_rdreq <= 1'b0;
+				int_wrreq <= 1'b0;
+			end
+			4'b0100: // set write addr
+			begin
+				int_addr <= 1'b1;
+				int_rden <= 1'b0;
+				int_wren <= 1'b1;
+				int_rdreq <= 1'b0;
+				int_wrreq <= 1'b0;
+			end
+			4'b011?: // write
+			begin
+				int_addr <= 1'b1;
+				int_rden <= 1'b0;
+				int_wren <= 1'b1;
+				int_rdreq <= 1'b0;
+				int_wrreq <= 1'b1;
+			end
+		endcase
+/*
 		if (usb_pktend)
 		begin
@@ -64,13 +130,13 @@
 			idle_counter <= idle_counter + 5'd1;
 		end
+*/
 	end
 
-	assign	usb_pktend = (&idle_counter);
-//	assign	usb_pktend = 1'b0;
-	assign	usb_rdreq = (~usb_empty) & (~rx_full);
-	assign	usb_wrreq = (~usb_rdreq) & (~usb_full) & (~tx_empty);
-	assign	usb_rden = usb_rdreq;
-	assign	usb_wren = usb_wrreq;
-	assign	usb_addr = usb_empty ? 2'b11 : 2'b10; 
+	assign	usb_addr = {1'b1, int_addr}; 
+	assign	usb_rden = int_rden;
+	assign	usb_rdreq = int_rdreq;
+	assign	usb_wrreq = int_wrreq;
+//	assign	usb_pktend = (&idle_counter);
+	assign	usb_pktend = 1'b0;
 
 endmodule