Index: /trunk/MultiChannelUSB/Paella.v
===================================================================
--- /trunk/MultiChannelUSB/Paella.v	(revision 29)
+++ /trunk/MultiChannelUSB/Paella.v	(revision 30)
@@ -23,5 +23,12 @@
 		input	wire			USB_FLAGB, // FULL flag for EP8
 		input	wire			USB_FLAGC,
-		inout	wire	[7:0]	USB_PA,
+		inout	wire			USB_PA0,
+		inout	wire			USB_PA1,
+		output	wire			USB_PA2,
+		inout	wire			USB_PA3,
+		output	wire			USB_PA4,
+		output	wire			USB_PA5,
+		output	wire			USB_PA6,
+		inout	wire			USB_PA7,
 		inout	wire	[7:0]	USB_PB,
 
@@ -47,5 +54,8 @@
 	assign	CON_B		=	16'bz;
 	assign	CON_C		=	13'bz;
-	assign	USB_PA		=	{1'bz, ~usb_pktend, usb_addr, 1'bz, ~usb_rden, 2'bz};
+	assign	USB_PA0		=	1'bz;
+	assign	USB_PA1		=	1'bz;
+	assign	USB_PA3		=	1'bz;
+	assign	USB_PA7		=	1'bz;
 	assign	RAM_DQAP	=	1'bz;
 	assign	RAM_DQA		=	8'bz;
@@ -53,13 +63,21 @@
 	assign	RAM_DQB		=	8'bz;
 
+
+	assign	USB_PA2		=	~usb_rden;
+	assign	USB_PA4		=	usb_addr[0];
+	assign	USB_PA5		=	usb_addr[1];
+	assign	USB_PA6		=	~usb_pktend;
+
 	reg		[31:0]	counter;	
-	assign	LED			=	counter[24];
-//	assign	LED			=	usb_fifo_led;
+//	assign	LED			=	counter[24];
+	assign	LED			=	usb_fifo_rx_empty;
 
 	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
 	wire			usb_fifo_aclr, usb_fifo_led;
-	wire			usb_fifo_tx_wrreq, usb_fifo_rx_rdreq;
+	reg				usb_fifo_tx_wrreq;
+	reg				usb_fifo_rx_rdreq;
 	wire			usb_fifo_tx_full, usb_fifo_rx_empty;
-	wire	[7:0]	usb_fifo_tx_data, usb_fifo_rx_data;
+	reg		[7:0]	usb_fifo_tx_data;
+	wire	[7:0]	usb_fifo_rx_data;
 	wire	[1:0]	usb_addr;
 
@@ -91,5 +109,5 @@
 	reg		[9:0]	osc_counter;	
 	reg 			osc_reset;
-	reg 			osc_bit_num;
+	reg 			osc_byte_num;
 	wire	[9:0]	osc_start_addr;
 	reg 	[9:0]	osc_addr;
@@ -97,9 +115,9 @@
 
 	reg 			hst_reset;
-	reg 	[1:0]	hst_bit_num;
+	reg 	[1:0]	hst_byte_num;
 	reg 	[11:0]	hst_addr;
 	wire	[31:0]	hst_q;
 
-	reg		[3:0]	state0, state1, state2;
+	reg		[2:0]	state0, state1, state2;
 	reg				adc_fifo_rdreq;
 	wire			adc_fifo_rdempty;
@@ -149,9 +167,10 @@
 	);
 
-
+/*
 	always @ (posedge adc_clk)
 	begin
 		counter <= counter + 32'd1;
 	end
+*/
 
 	always @ (posedge CLK_50MHz)
@@ -162,8 +181,8 @@
 				if (~adc_fifo_rdempty)
 				begin
-					adc_counter <= adc_counter + 32'd1;
+//					adc_counter <= adc_counter + 32'd1;
 					adc_fifo_rdreq <= 1'b1;
 					adc_data_ready <= 1'b1;
-					state0 <= 4'd2;
+					state0 <= 3'd2;
 				end
 			end
@@ -173,14 +192,187 @@
 				adc_fifo_rdreq <= 1'b0;
 				adc_data_ready <= 1'b0;
-				state0 <= 4'd1;
+				state0 <= 3'd1;
 			end
 
 			default:
 			begin
-				state0 <= 4'd1;
+				state0 <= 3'd1;
 			end
 		endcase
 	end
 
+	always @(posedge CLK_50MHz)
+	begin
+		case (state1)
+			1:
+			begin
+				usb_fifo_rx_rdreq <= 1'b0;
+				usb_fifo_tx_wrreq <= 1'b0;
+				hst_reset <= 1'b0;
+				osc_reset <= 1'b0;
+				state1 <= 3'd2;
+			end
+
+			2: 
+			begin
+				if (~usb_fifo_rx_empty)
+				begin
+					usb_fifo_rx_rdreq <= 1'b1;
+					case (usb_fifo_rx_data)
+						8'h30:
+						begin
+							hst_reset <= 1'b1;
+							state1 <= 3'd1;
+						end
+						8'h31:
+						begin
+							hst_addr <= 12'd0;
+							hst_byte_num <= 2'd0;	
+							state1 <= 3'd3;
+						end
+						8'h32:
+						begin
+							osc_reset <= 1'b1;
+							state1 <= 3'd1;
+						end
+						8'h33:
+						begin
+							osc_addr <= osc_start_addr;
+							osc_counter <= 10'd0;
+							osc_byte_num <= 1'd0;	
+							state1 <= 3'd4;
+						end
+					endcase
+				end
+				else
+				begin
+					usb_fifo_rx_rdreq <= 1'b0;
+				end				
+			end
+
+			3:
+			begin
+				// hst transfer
+				if (~usb_fifo_tx_full)
+				begin
+					usb_fifo_tx_wrreq <= 1'b1;
+
+					case (hst_byte_num)
+						2'd0: usb_fifo_tx_data <= hst_q[7:0];
+						2'd1: usb_fifo_tx_data <= hst_q[15:8];
+						2'd2: usb_fifo_tx_data <= hst_q[23:16];
+						2'd3: usb_fifo_tx_data <= hst_q[31:24];
+					endcase
+					
+					if (&hst_byte_num)
+					begin
+						hst_byte_num <= 2'd0;				
+						if (&hst_addr)
+						begin
+							state1 <= 3'd1;
+						end
+						else
+						begin
+							hst_addr <= hst_addr + 12'd1;
+						end
+					end
+					else
+					begin
+						hst_byte_num <= hst_byte_num + 2'd1;				
+					end				
+				end
+				else
+				begin
+					usb_fifo_tx_wrreq <= 1'b0;
+				end
+			end
+
+			4:
+			begin
+				// osc transfer
+				if(~usb_fifo_tx_full)
+				begin
+					usb_fifo_tx_wrreq <= 1'b1;
+
+					case (osc_byte_num)
+						1'd0: usb_fifo_tx_data <= osc_q[7:0];
+						1'd1: usb_fifo_tx_data <= osc_q[15:8];
+					endcase
+	
+					if (osc_byte_num)
+					begin
+						osc_byte_num <= 1'd0;				
+						if (&osc_counter)
+						begin
+							state1 <= 3'd1;
+						end
+						else
+						begin
+							osc_addr <= osc_addr + 10'd1;
+							osc_counter <= osc_counter + 10'd1;
+						end
+					end
+					else
+					begin
+						osc_byte_num <= 1'd1;				
+					end										
+				end
+				else
+				begin
+					usb_fifo_tx_wrreq <= 1'b0;
+				end
+			end
+
+			default:
+			begin
+				// default state is the first one
+				state1 <= 3'd1;
+			end
+		endcase
+	end
+/*
+	always @(posedge CLK_50MHz)
+	begin
+		case(state1)
+			0:
+			begin
+				usb_fifo_tx_wrreq <= 1'b0;
+				counter <= 32'd0;
+				state1 <= 3'd1;
+			end
+			1:
+			begin
+				if((~usb_fifo_tx_full) & (counter < 32'd512))
+				begin
+					counter <= counter + 32'd1;
+					state1 <= 3'd2;
+					usb_fifo_tx_data <= 1;
+					usb_fifo_tx_wrreq <= 1'b1;
+				end
+				else
+				begin
+					usb_fifo_tx_wrreq <= 1'b0;
+				end
+			end
+				
+			2:
+			begin
+				if((~usb_fifo_tx_full) & (counter < 32'd512))
+				begin
+					counter <= counter + 32'd1;
+					state1 <= 3'd1;
+					usb_fifo_tx_data <= 0;
+					usb_fifo_tx_wrreq <= 1'b1;
+				end
+				else
+				begin
+					usb_fifo_tx_wrreq <= 1'b0;
+				end
+			end
+						
+			default: state1 <= 3'd0;
+		endcase
+	end
+*/
 	always @ (posedge adc_clk)
 	begin
@@ -189,5 +381,5 @@
 			begin
 				adc_data <= 12'd0;
-				state2 <= 4'd2;
+				state2 <= 3'd2;
 			end
 			
@@ -195,5 +387,5 @@
 			begin
 				adc_data <= 12'd1024;
-				state2 <= 4'd3;
+				state2 <= 3'd3;
 			end
 
@@ -201,5 +393,5 @@
 			begin
 				adc_data <= 12'd2048;
-				state2 <= 4'd4;
+				state2 <= 3'd4;
 			end
 
@@ -207,5 +399,5 @@
 			begin
 				adc_data <= 12'd3072;
-				state2 <= 4'd5;
+				state2 <= 3'd5;
 			end
 
@@ -213,10 +405,10 @@
 			begin
 				adc_data <= 12'd4095;
-				state2 <= 4'd1;
+				state2 <= 3'd1;
 			end
 
 			default:
 			begin
-				state2 <= 4'd1;
+				state2 <= 3'd1;
 			end
 		endcase
Index: /trunk/MultiChannelUSB/usb_fifo.v
===================================================================
--- /trunk/MultiChannelUSB/usb_fifo.v	(revision 29)
+++ /trunk/MultiChannelUSB/usb_fifo.v	(revision 30)
@@ -13,7 +13,4 @@
 		output	wire	[7:0]	rx_data
 	);
-	
-	localparam EPRD_ADDR	=	2'b10;  // 6
-	localparam EPWR_ADDR	=	2'b11;  // 8
 
 	// bidirectional data bus
@@ -24,6 +21,7 @@
 	assign	usb_data = usb_wren ? usb_dataout : 8'bz;
 
-	wire			tx_rdreq, tx_empty;
-	wire			rx_wrreq, rx_full;
+	wire			rx_full, tx_empty;
+	reg		[8:0]	byte_counter;
+	reg		[4:0]	idle_counter;
 
 	fifo32x8 fifo_tx_unit (
@@ -31,8 +29,8 @@
 		.data(tx_data),
 		.rdclk(usb_clk),
-		.rdreq(tx_rdreq),
+		.rdreq(usb_wrreq),
 		.wrclk(clk),
 		.wrreq(tx_wrreq),
-		.q(usb_dataout_bis),
+		.q(usb_dataout),
 		.rdempty(tx_empty),
 		.wrfull(tx_full));
@@ -44,65 +42,35 @@
 		.rdreq(rx_rdreq),
 		.wrclk(usb_clk),
-		.wrreq(rx_wrreq),
+		.wrreq(usb_rdreq),
 		.q(rx_data),
 		.rdempty(rx_empty),
 		.wrfull(rx_full));
-
-	reg		[31:0]	counter;	
-	
-	reg		[2:0]	state;
-	reg				tx;
-	reg		[7:0]	dout;
-
-	always @(posedge usb_clk)
+		
+	always @ (posedge usb_clk)
 	begin
-		case(state)
-			0:
-			begin
-				tx <= 1'b0;
-				counter <= 32'd0;
-				state <= 3'd1;
-			end
-			1:
-			begin
-				if((~usb_full) & (counter < 32'd512))
-				begin
-					counter <= counter + 32'd1;
-					state <= 3'd2;
-					dout <= 1;
-					tx <= 1'b1;
-				end
-				else
-				begin
-					tx <= 1'b0;
-				end
-			end
-				
-			2:
-			begin
-				if((~usb_full) & (counter < 32'd512))
-				begin
-					counter <= counter + 32'd1;
-					state <= 3'd1;
-					dout <= 0;
-					tx <= 1'b1;
-				end
-				else
-				begin
-					tx <= 1'b0;
-				end
-			end
-						
-			default: state <= 3'd0;
-		endcase
+		if (usb_pktend)
+		begin
+			byte_counter <= 9'd0;
+			idle_counter <= 5'd0;
+		end
+		else if (usb_wrreq)
+		begin
+			byte_counter <= byte_counter + 9'd1;
+			idle_counter <= 5'd0;
+		end
+		else if ((|byte_counter) & (tx_empty))
+		begin
+			byte_counter <= byte_counter;
+			idle_counter <= idle_counter + 5'd1;
+		end
 	end
 
-	assign	usb_addr = 2'b11; // FIFO8
-	assign	usb_rdreq = 1'b0; // always TX for now
-	assign	usb_dataout = dout;
-	assign	usb_wrreq = tx;
-	assign	usb_pktend = 1'b0;
-	assign	usb_rden = 1'b0;
-	assign	usb_wren = tx;
+	assign	usb_pktend = (&idle_counter);
+//	assign	usb_pktend = 1'b0;
+	assign	usb_rdreq = (~usb_empty) & (~rx_full);
+	assign	usb_wrreq = (~usb_rdreq) & (~usb_full) & (~tx_empty);
+	assign	usb_rden = usb_rdreq;
+	assign	usb_wren = usb_wrreq;
+	assign	usb_addr = usb_empty ? 2'b11 : 2'b10; 
 
 endmodule