Index: /trunk/MultiChannelCOM/CII_Starter_TOP.v
===================================================================
--- /trunk/MultiChannelCOM/CII_Starter_TOP.v	(revision 2)
+++ /trunk/MultiChannelCOM/CII_Starter_TOP.v	(revision 2)
@@ -0,0 +1,511 @@
+//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+
+module CII_Starter_TOP
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_24,						//	24 MHz
+		CLOCK_27,						//	27 MHz
+		CLOCK_50,						//	50 MHz
+		EXT_CLOCK,						//	External Clock
+		////////////////////	Push Button		////////////////////
+		KEY,							//	Pushbutton[3:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,							//	Seven Segment Digit 0
+		HEX1,							//	Seven Segment Digit 1
+		HEX2,							//	Seven Segment Digit 2
+		HEX3,							//	Seven Segment Digit 3
+		////////////////////////	LED		////////////////////////
+		LEDG,							//	LED Green[7:0]
+		LEDR,							//	LED Red[9:0]
+		////////////////////////	UART	////////////////////////
+		UART_TXD,						//	UART Transmitter
+		UART_RXD,						//	UART Receiver
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,						//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	Flash Interface		////////////////
+		FL_DQ,							//	FLASH Data bus 8 Bits
+		FL_ADDR,						//	FLASH Address bus 22 Bits
+		FL_WE_N,						//	FLASH Write Enable
+		FL_RST_N,						//	FLASH Reset
+		FL_OE_N,						//	FLASH Output Enable
+		FL_CE_N,						//	FLASH Chip Enable
+		////////////////////	SRAM Interface		////////////////
+		SRAM_DQ,						//	SRAM Data bus 16 Bits
+		SRAM_ADDR,						//	SRAM Address bus 18 Bits
+		SRAM_UB_N,						//	SRAM High-byte Data Mask 
+		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
+		SRAM_WE_N,						//	SRAM Write Enable
+		SRAM_CE_N,						//	SRAM Chip Enable
+		SRAM_OE_N,						//	SRAM Output Enable
+		////////////////////	SD_Card Interface	////////////////
+		SD_DAT,							//	SD Card Data
+		SD_DAT3,						//	SD Card Data 3
+		SD_CMD,							//	SD Card Command Signal
+		SD_CLK,							//	SD Card Clock
+		////////////////////	USB JTAG link	////////////////////
+		TDI,  							// CPLD -> FPGA (data in)
+		TCK,  							// CPLD -> FPGA (clk)
+		TCS,  							// CPLD -> FPGA (CS)
+	    TDO,  							// FPGA -> CPLD (data out)
+		////////////////////	I2C		////////////////////////////
+		I2C_SDAT,						//	I2C Data
+		I2C_SCLK,						//	I2C Clock
+		////////////////////	PS2		////////////////////////////
+		PS2_DAT,						//	PS2 Data
+		PS2_CLK,						//	PS2 Clock
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  						//	VGA Blue[3:0]
+		////////////////	Audio CODEC		////////////////////////
+		AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
+		AUD_ADCDAT,						//	Audio CODEC ADC Data
+		AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
+		AUD_DACDAT,						//	Audio CODEC DAC Data
+		AUD_BCLK,						//	Audio CODEC Bit-Stream Clock
+		AUD_XCK,						//	Audio CODEC Chip Clock
+		////////////////////	GPIO	////////////////////////////
+		GPIO_0,							//	GPIO Connection 0
+		GPIO_1							//	GPIO Connection 1
+	);
+
+	////////////////////////	Clock Input	 	////////////////////////
+	input	[1:0]	CLOCK_24;				//	24 MHz
+	input	[1:0]	CLOCK_27;				//	27 MHz
+	input			CLOCK_50;				//	50 MHz
+	input			EXT_CLOCK;				//	External Clock
+	////////////////////////	Push Button		////////////////////////
+	input	[3:0]	KEY;					//	Pushbutton[3:0]
+	////////////////////////	DPDT Switch		////////////////////////
+	input	[9:0]	SW;						//	Toggle Switch[9:0]
+	////////////////////////	7-SEG Dispaly	////////////////////////
+	output	[6:0]	HEX0;					//	Seven Segment Digit 0
+	output	[6:0]	HEX1;					//	Seven Segment Digit 1
+	output	[6:0]	HEX2;					//	Seven Segment Digit 2
+	output	[6:0]	HEX3;					//	Seven Segment Digit 3
+	////////////////////////////	LED		////////////////////////////
+	output	[7:0]	LEDG;					//	LED Green[7:0]
+	output	[9:0]	LEDR;					//	LED Red[9:0]
+	////////////////////////////	UART	////////////////////////////
+	output			UART_TXD;				//	UART Transmitter
+	input			UART_RXD;				//	UART Receiver
+	///////////////////////		SDRAM Interface	////////////////////////
+	inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+	output	[11:0]	DRAM_ADDR;				//	SDRAM Address bus 12 Bits
+	output			DRAM_LDQM;				//	SDRAM Low-byte Data Mask 
+	output			DRAM_UDQM;				//	SDRAM High-byte Data Mask
+	output			DRAM_WE_N;				//	SDRAM Write Enable
+	output			DRAM_CAS_N;				//	SDRAM Column Address Strobe
+	output			DRAM_RAS_N;				//	SDRAM Row Address Strobe
+	output			DRAM_CS_N;				//	SDRAM Chip Select
+	output			DRAM_BA_0;				//	SDRAM Bank Address 0
+	output			DRAM_BA_1;				//	SDRAM Bank Address 0
+	output			DRAM_CLK;				//	SDRAM Clock
+	output			DRAM_CKE;				//	SDRAM Clock Enable
+	////////////////////////	Flash Interface	////////////////////////
+	inout	[7:0]	FL_DQ;					//	FLASH Data bus 8 Bits
+	output	[21:0]	FL_ADDR;				//	FLASH Address bus 22 Bits
+	output			FL_WE_N;				//	FLASH Write Enable
+	output			FL_RST_N;				//	FLASH Reset
+	output			FL_OE_N;				//	FLASH Output Enable
+	output			FL_CE_N;				//	FLASH Chip Enable
+	////////////////////////	SRAM Interface	////////////////////////
+	inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
+	output	[17:0]	SRAM_ADDR;				//	SRAM Address bus 18 Bits
+	output			SRAM_UB_N;				//	SRAM High-byte Data Mask 
+	output			SRAM_LB_N;				//	SRAM Low-byte Data Mask 
+	output			SRAM_WE_N;				//	SRAM Write Enable
+	output			SRAM_CE_N;				//	SRAM Chip Enable
+	output			SRAM_OE_N;				//	SRAM Output Enable
+	////////////////////	SD Card Interface	////////////////////////
+	inout			SD_DAT;					//	SD Card Data
+	inout			SD_DAT3;				//	SD Card Data 3
+	inout			SD_CMD;					//	SD Card Command Signal
+	output			SD_CLK;					//	SD Card Clock
+	////////////////////////	I2C		////////////////////////////////
+	inout			I2C_SDAT;				//	I2C Data
+	output			I2C_SCLK;				//	I2C Clock
+	////////////////////////	PS2		////////////////////////////////
+	input		 	PS2_DAT;				//	PS2 Data
+	input			PS2_CLK;				//	PS2 Clock
+	////////////////////	USB JTAG link	////////////////////////////
+	input  			TDI;					// CPLD -> FPGA (data in)
+	input  			TCK;					// CPLD -> FPGA (clk)
+	input  			TCS;					// CPLD -> FPGA (CS)
+	output 			TDO;					// FPGA -> CPLD (data out)
+	////////////////////////	VGA			////////////////////////////
+	output			VGA_HS;					//	VGA H_SYNC
+	output			VGA_VS;					//	VGA V_SYNC
+	output	[3:0]	VGA_R;   				//	VGA Red[3:0]
+	output	[3:0]	VGA_G;	 				//	VGA Green[3:0]
+	output	[3:0]	VGA_B;   				//	VGA Blue[3:0]
+	////////////////////	Audio CODEC		////////////////////////////
+	inout			AUD_ADCLRCK;			//	Audio CODEC ADC LR Clock
+	input			AUD_ADCDAT;				//	Audio CODEC ADC Data
+	inout			AUD_DACLRCK;			//	Audio CODEC DAC LR Clock
+	output			AUD_DACDAT;				//	Audio CODEC DAC Data
+	inout			AUD_BCLK;				//	Audio CODEC Bit-Stream Clock
+	output			AUD_XCK;				//	Audio CODEC Chip Clock
+	////////////////////////	GPIO	////////////////////////////////
+	inout	[35:0]	GPIO_0;					//	GPIO Connection 0
+	inout	[35:0]	GPIO_1;					//	GPIO Connection 1
+	
+	//	Turn off all display
+	assign	HEX0		=	7'h7F;
+	assign	HEX1		=	7'h7F;
+	assign	HEX2		=	7'h7F;
+	assign	HEX3		=	7'h7F;
+//	assign	LEDG		=	8'h00;
+	assign	LEDR		=	10'h000;
+	
+	//	All inout port turn to tri-state
+	assign	DRAM_DQ		=	16'bz;
+	assign	FL_DQ		=	8'bz;
+	assign	SRAM_DQ		=	16'bz;
+	assign	SD_DAT		=	1'bz;
+	assign	I2C_SDAT	=	1'bz;
+	assign	AUD_ADCLRCK	=	1'bz;
+	assign	AUD_DACLRCK	=	1'bz;
+	assign	AUD_BCLK	=	1'bz;
+	assign	GPIO_0		=	36'bz;
+//	assign	GPIO_1		=	36'bz;
+	
+
+	reg		[9:0]	osc_counter;
+	reg		[25:0]	hst_counter;
+	
+	reg 			osc_reset;
+	reg 			osc_bit_num;
+	wire	[9:0]	osc_start_addr;
+	reg 	[9:0]	osc_addr;
+	wire	[15:0]	osc_q;
+
+	reg 			hst_reset;
+	reg 	[1:0]	hst_bit_num;
+	reg 	[11:0]	hst_addr;
+	wire	[31:0]	hst_q;
+
+	reg		[3:0]	state0, state1, state2;
+	reg				adc_fifo_rdreq;
+	wire			adc_fifo_rdempty;
+	reg				adc_fifo_aclr;
+	reg				rd_uart, wr_uart;
+	wire			tx_full, rx_empty;
+
+	wire	[7:0]	RxD_data;
+	reg		[7:0]	TxD_data;
+
+	wire	[4:0]	led;
+
+	reg				adc_data_ready;
+	wire			adc_dr, adc_or;
+//	wire 	[11:0]	adc_data;
+	reg 	[11:0]	adc_data;
+    wire	[11:0]	raw_data;
+    wire	[11:0]	uwt_data;
+    wire	[1:0]	uwt_flag;
+ 
+	assign 	GPIO_1[21:0]=	22'bz;
+	assign 	adc_or		=	GPIO_1[35];
+//	assign 	adc_data	=	GPIO_1[34:23];
+//	assign 	adc_dr		=	GPIO_1[22];
+	assign	adc_dr		=	CLOCK_24[0];
+
+	assign	LEDG		=	{3'h0, led};
+
+	assign	led[4]		=	hst_counter[23];
+
+    uart uart_unit (
+		.clk(CLOCK_50),
+		.reset(1'b0),
+		.rd_uart(rd_uart),
+		.wr_uart(wr_uart),
+		.rx(UART_RXD),
+		.w_data(TxD_data),
+		.tx_full(tx_full),
+		.rx_empty(rx_empty),
+		.r_data(RxD_data),
+		.tx(UART_TXD));
+
+	adc_fifo adc_fifo_unit (
+		.adc_dr(adc_dr),
+		.adc_or(adc_or),
+		.adc_data(adc_data),
+		.aclr(adc_fifo_aclr),
+		.rdclk(CLOCK_50),
+		.rdreq(adc_fifo_rdreq),
+		.rdempty(adc_fifo_rdempty),
+		.raw_data(raw_data),
+		.uwt_data({uwt_flag, uwt_data}));
+
+	histogram histogram_unit (
+		.clk(CLOCK_50),
+		.reset(hst_reset),
+		.data_ready(adc_data_ready),
+		.data(raw_data),
+		.address(hst_addr),
+		.q(hst_q),
+		.led(led[3:0])
+	);
+	
+	oscilloscope oscilloscope_unit (
+		.clk(CLOCK_50),
+		.reset(osc_reset),
+		.data_ready(adc_data_ready),
+		.raw_data(raw_data),
+		.uwt_data(uwt_data),
+		.threshold(16'd100),
+		.address(osc_addr),
+		.start_address(osc_start_addr),
+		.q(osc_q)
+	);
+
+
+	always @ (posedge CLOCK_50)
+	begin
+
+		case (state0)
+			1:
+			begin
+				if (~adc_fifo_rdempty)
+				begin
+					adc_fifo_rdreq <= 1'b1;
+					adc_data_ready <= 1'b1;
+					state0 <= 4'd2;
+				end
+			end
+
+			2:
+			begin
+				adc_fifo_rdreq <= 1'b0;
+				adc_data_ready <= 1'b0;
+				state0 <= 4'd1;
+			end
+
+			default:
+			begin
+				state0 <= 4'd1;
+			end
+		endcase
+
+		case (state1)
+			1:
+			begin
+				rd_uart <= 1'b0;
+				hst_reset <= 1'b0;
+				osc_reset <= 1'b0;
+				state1 <= 4'd2;
+			end
+
+			2: 
+			begin
+				if (~rx_empty)
+				begin
+					rd_uart <= 1'b1;
+					case (RxD_data)
+						8'h30:
+						begin
+							hst_reset <= 1'b1;
+							state1 <= 4'd1;
+						end
+						8'h31: state1 <= 4'd3;
+						8'h32:
+						begin
+							osc_reset <= 1'b1;
+							state1 <= 4'd1;
+						end
+						8'h33: state1 <= 4'd7;
+					endcase
+				end
+				else
+				begin
+					rd_uart <= 1'b0;
+				end				
+			end
+
+			3:
+			begin
+				// start hst transfer
+				rd_uart <= 1'b0;
+				hst_addr <= 12'h0;
+				hst_bit_num <= 2'd0;	
+				state1 <= 4'd4;
+			end
+
+			4:
+			begin
+				case (hst_bit_num)
+					2'd0: TxD_data <= hst_q[7:0];
+					2'd1: TxD_data <= hst_q[15:8];
+					2'd2: TxD_data <= hst_q[23:16];
+					2'd3: TxD_data <= hst_q[31:24];
+//					2'd0: TxD_data <= 8'd255;
+//					2'd1: TxD_data <= 8'd0;
+//					2'd2: TxD_data <= 8'd0;
+//					2'd3: TxD_data <= 8'd0;
+				endcase
+				wr_uart <= 0;
+			    state1 <= 4'd5;
+			end
+
+			5:
+			begin
+				if (~tx_full)
+				begin
+					wr_uart <= 1;
+					state1 <= 4'd6;
+				end
+			end
+
+			6:
+			begin
+				wr_uart <= 0;
+				if (&hst_bit_num)
+				begin
+					hst_bit_num <= 2'd0;				
+					if (&hst_addr)
+					begin
+						state1 <= 4'd1;
+					end
+					else
+					begin
+						hst_addr <= hst_addr + 12'd1;
+						state1 <= 4'd4;
+					end
+				end
+				else
+				begin
+					hst_bit_num <= hst_bit_num + 2'd1;				
+					state1 <= 4'd4;
+				end
+			end
+
+
+			7:
+			begin
+				// start osc transfer
+				rd_uart <= 1'b0;
+				osc_addr <= osc_start_addr;
+				osc_bit_num <= 1'd0;
+				osc_counter <= 10'd0;	
+				state1 <= 4'd8;
+			end
+
+			8:
+			begin
+				case(osc_bit_num)
+					1'd0: TxD_data <= osc_q[7:0];
+					1'd1: TxD_data <= osc_q[15:8];
+				endcase
+				wr_uart <= 0;
+			    state1 <= 4'd9;
+			end
+
+			9:
+			begin
+				if (~tx_full)
+				begin
+					wr_uart <= 1;
+					state1 <= 4'd10;
+				end
+			end
+
+			10:
+			begin
+				wr_uart <= 0;
+				if (osc_bit_num)
+				begin
+					osc_bit_num <= 1'd0;				
+					if (&osc_counter)
+					begin
+						state1 <= 4'd1;
+					end
+					else
+					begin
+						osc_addr <= osc_addr + 10'd1;
+						osc_counter <= osc_counter + 10'd1;
+						state1 <= 4'd8;
+					end
+				end
+				else
+				begin
+					osc_bit_num <= osc_bit_num + 1'd1;				
+					state1 <= 4'd8;
+				end
+			end
+
+			default:
+			begin
+				// default state is the first one
+				state1 <= 4'd1;
+			end
+		endcase
+	end
+
+	always @ (posedge adc_dr)
+	begin
+		case (state2)
+			1: 
+			begin
+				adc_data <= 12'd0;
+				state2 <= 4'd2;
+			end
+			
+			2:
+			begin
+				adc_data <= 12'd1024;
+				state2 <= 4'd3;
+			end
+
+			3:
+			begin
+				adc_data <= 12'd2048;
+				state2 <= 4'd4;
+			end
+
+			4:
+			begin
+				adc_data <= 12'd3072;
+				state2 <= 4'd5;
+			end
+
+			5:
+			begin
+				adc_data <= 12'd4095;
+				state2 <= 4'd1;
+			end
+
+			default:
+			begin
+				state2 <= 4'd1;
+			end
+		endcase
+	end
+	
+endmodule
Index: /trunk/MultiChannelCOM/adc_fifo.v
===================================================================
--- /trunk/MultiChannelCOM/adc_fifo.v	(revision 2)
+++ /trunk/MultiChannelCOM/adc_fifo.v	(revision 2)
@@ -0,0 +1,69 @@
+module adc_fifo
+	(
+		input	wire			adc_dr,
+		input	wire			adc_or,
+		input	wire	[11:0]	adc_data,
+
+		input	wire			aclr,
+		input	wire			rdclk,
+		input	wire			rdreq,
+		output	wire			rdempty,
+		output	wire	[11:0]	raw_data,
+		output	wire	[13:0]	uwt_data
+	);
+
+	wire 	[31:0]	uwt_d1, uwt_a1, uwt_peak1;
+	wire 	[31:0]	uwt_d2, uwt_a2, uwt_peak2;
+	wire 	[31:0]	uwt_d3, uwt_a3, uwt_peak3;
+	wire 	[1:0]	uwt_flag1, uwt_flag2, uwt_flag3;
+
+	wire	[1:0]	wrfull;
+
+	uwt_bior31 #(.L(1)) uwt_1_unit (
+		.clk(adc_dr),
+		.x(adc_data),
+		.d(uwt_d1),
+		.a(uwt_a1),
+		.peak(uwt_peak1),
+		.flag(uwt_flag1));
+
+	uwt_bior31 #(.L(2)) uwt_2_unit (
+		.clk(adc_dr),
+		.x(uwt_a1),
+		.d(uwt_d2),
+		.a(uwt_a2),
+		.peak(uwt_peak2),
+		.flag(uwt_flag2));
+
+	uwt_bior31 #(.L(3)) uwt_3_unit (
+		.clk(adc_dr),
+		.x(uwt_a2),
+		.d(uwt_d3),
+		.a(uwt_a3),
+		.peak(uwt_peak3),
+		.flag(uwt_flag3));
+
+
+	fifo32x12 fifo0 (
+		.aclr(aclr),
+		.data(adc_data),
+		.rdclk(rdclk),
+		.rdreq(rdreq),
+		.wrclk(adc_dr),
+		.wrreq(~wrfull[0]),
+		.q(raw_data),
+		.rdempty(rdempty),
+		.wrfull(wrfull[0]));
+
+	fifo32x14 fifo1 (
+		.aclr(aclr),
+		.data({uwt_flag3, uwt_peak3[11:0]}),
+		.rdclk(rdclk),
+		.rdreq(rdreq),
+		.wrclk(adc_dr),
+		.wrreq(~wrfull[1]),
+		.q(uwt_data),
+		.rdempty(),
+		.wrfull(wrfull[1]));
+
+endmodule
Index: /trunk/MultiChannelCOM/baud_gen.v
===================================================================
--- /trunk/MultiChannelCOM/baud_gen.v	(revision 2)
+++ /trunk/MultiChannelCOM/baud_gen.v	(revision 2)
@@ -0,0 +1,36 @@
+module baud_gen
+	#(
+		parameter	INC=1208,	// counter increment (115200*16*32768/F_clk)
+					DIV=1		// divider (baud rate = 115200/D)
+	)
+	(
+		input wire clk, reset,
+		output wire max_tick
+	);
+	
+	//signal declaration
+	reg [15:0] acc_reg;
+	reg [7:0] div_reg;
+	 
+	wire div_reg_max = (div_reg == (DIV-1));
+
+	// body
+	always @(posedge clk, posedge reset)
+	begin
+		if (reset)
+			begin
+				acc_reg <= 0;
+				div_reg <= 0;
+			end
+		else
+			begin
+				acc_reg <= acc_reg[14:0] + INC;
+				if (acc_reg[15])
+					div_reg <= div_reg_max ? 0 : div_reg + 16'd1;
+			end
+	end
+
+   // output logic
+   assign max_tick = acc_reg[15] & div_reg_max;
+
+endmodule
Index: /trunk/MultiChannelCOM/fifo.v
===================================================================
--- /trunk/MultiChannelCOM/fifo.v	(revision 2)
+++ /trunk/MultiChannelCOM/fifo.v	(revision 2)
@@ -0,0 +1,92 @@
+// Listing 4.20
+module fifo
+   #(
+    parameter B=8, // number of bits in a word
+              W=4  // number of address bits
+   )
+   (
+    input wire clk, reset,
+    input wire rd, wr,
+    input wire [B-1:0] w_data,
+    output wire empty, full,
+    output wire [B-1:0] r_data
+   );
+
+   //signal declaration
+   reg [B-1:0] array_reg [2**W-1:0];  // register array
+   reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
+   reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
+   reg full_reg, empty_reg, full_next, empty_next;
+   wire wr_en;
+
+   // body
+   // register file write operation
+   always @(posedge clk)
+      if (wr_en)
+         array_reg[w_ptr_reg] <= w_data;
+   // register file read operation
+   assign r_data = array_reg[r_ptr_reg];
+   // write enabled only when FIFO is not full
+   assign wr_en = wr & ~full_reg;
+
+   // fifo control logic
+   // register for read and write pointers
+   always @(posedge clk, posedge reset)
+      if (reset)
+         begin
+            w_ptr_reg <= 0;
+            r_ptr_reg <= 0;
+            full_reg <= 1'b0;
+            empty_reg <= 1'b1;
+         end
+      else
+         begin
+            w_ptr_reg <= w_ptr_next;
+            r_ptr_reg <= r_ptr_next;
+            full_reg <= full_next;
+            empty_reg <= empty_next;
+         end
+
+   // next-state logic for read and write pointers
+   always @*
+   begin
+      // successive pointer values
+      w_ptr_succ = w_ptr_reg + 1;
+      r_ptr_succ = r_ptr_reg + 1;
+      // default: keep old values
+      w_ptr_next = w_ptr_reg;
+      r_ptr_next = r_ptr_reg;
+      full_next = full_reg;
+      empty_next = empty_reg;
+      case ({wr, rd})
+         // 2'b00:  no op
+         2'b01: // read
+            if (~empty_reg) // not empty
+               begin
+                  r_ptr_next = r_ptr_succ;
+                  full_next = 1'b0;
+                  if (r_ptr_succ==w_ptr_reg)
+                     empty_next = 1'b1;
+               end
+         2'b10: // write
+            if (~full_reg) // not full
+               begin
+                  w_ptr_next = w_ptr_succ;
+                  empty_next = 1'b0;
+                  if (w_ptr_succ==r_ptr_reg)
+                     full_next = 1'b1;
+               end
+         2'b11: // write and read
+            begin
+               w_ptr_next = w_ptr_succ;
+               r_ptr_next = r_ptr_succ;
+            end
+      endcase
+   end
+
+   // output
+   assign full = full_reg;
+   assign empty = empty_reg;
+
+endmodule
+
Index: /trunk/MultiChannelCOM/fifo32x12.v
===================================================================
--- /trunk/MultiChannelCOM/fifo32x12.v	(revision 2)
+++ /trunk/MultiChannelCOM/fifo32x12.v	(revision 2)
@@ -0,0 +1,183 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo32x12.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo32x12 (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	wrfull);
+
+	input	  aclr;
+	input	[11:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[11:0]  q;
+	output	  rdempty;
+	output	  wrfull;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire  sub_wire1;
+	wire [11:0] sub_wire2;
+	wire  rdempty = sub_wire0;
+	wire  wrfull = sub_wire1;
+	wire [11:0] q = sub_wire2[11:0];
+
+	dcfifo	dcfifo_component (
+				.wrclk (wrclk),
+				.rdreq (rdreq),
+				.aclr (aclr),
+				.rdclk (rdclk),
+				.wrreq (wrreq),
+				.data (data),
+				.rdempty (sub_wire0),
+				.wrfull (sub_wire1),
+				.q (sub_wire2)
+				// synopsys translate_off
+				,
+				.rdfull (),
+				.rdusedw (),
+				.wrempty (),
+				.wrusedw ()
+				// synopsys translate_on
+				);
+	defparam
+		dcfifo_component.intended_device_family = "Cyclone II",
+		dcfifo_component.lpm_numwords = 32,
+		dcfifo_component.lpm_showahead = "ON",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 12,
+		dcfifo_component.lpm_widthu = 5,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.rdsync_delaypipe = 4,
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON",
+		dcfifo_component.write_aclr_synch = "OFF",
+		dcfifo_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "32"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "12"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "12"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL data[11..0]
+// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
+// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x12_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Index: /trunk/MultiChannelCOM/fifo32x14.v
===================================================================
--- /trunk/MultiChannelCOM/fifo32x14.v	(revision 2)
+++ /trunk/MultiChannelCOM/fifo32x14.v	(revision 2)
@@ -0,0 +1,183 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo32x14.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo32x14 (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	wrfull);
+
+	input	  aclr;
+	input	[13:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[13:0]  q;
+	output	  rdempty;
+	output	  wrfull;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire  sub_wire1;
+	wire [13:0] sub_wire2;
+	wire  rdempty = sub_wire0;
+	wire  wrfull = sub_wire1;
+	wire [13:0] q = sub_wire2[13:0];
+
+	dcfifo	dcfifo_component (
+				.wrclk (wrclk),
+				.rdreq (rdreq),
+				.aclr (aclr),
+				.rdclk (rdclk),
+				.wrreq (wrreq),
+				.data (data),
+				.rdempty (sub_wire0),
+				.wrfull (sub_wire1),
+				.q (sub_wire2)
+				// synopsys translate_off
+				,
+				.rdfull (),
+				.rdusedw (),
+				.wrempty (),
+				.wrusedw ()
+				// synopsys translate_on
+				);
+	defparam
+		dcfifo_component.intended_device_family = "Cyclone II",
+		dcfifo_component.lpm_numwords = 32,
+		dcfifo_component.lpm_showahead = "ON",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 14,
+		dcfifo_component.lpm_widthu = 5,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.rdsync_delaypipe = 4,
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON",
+		dcfifo_component.write_aclr_synch = "OFF",
+		dcfifo_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "32"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "14"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "14"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 14 0 INPUT NODEFVAL data[13..0]
+// Retrieval info: USED_PORT: q 0 0 14 0 OUTPUT NODEFVAL q[13..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 14 0 data 0 0 14 0
+// Retrieval info: CONNECT: q 0 0 14 0 @q 0 0 14 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Index: /trunk/MultiChannelCOM/histogram.v
===================================================================
--- /trunk/MultiChannelCOM/histogram.v	(revision 2)
+++ /trunk/MultiChannelCOM/histogram.v	(revision 2)
@@ -0,0 +1,130 @@
+module histogram
+	(
+		input	wire			clk, reset,
+		input	wire			data_ready,
+		input	wire	[11:0]  data, address,
+		output	wire	[31:0]  q,
+		output	wire	[3:0]	led
+	);
+	
+	// signal declaration
+	reg		[3:0]	state_reg, state_next;
+
+	reg		[31:0]	led_data_reg [3:0];
+	reg		[31:0]  led_data_next [3:0];
+
+	reg				wren_reg, wren_next;
+	reg		[11:0]	addr_reg, addr_next;
+	reg		[31:0]	data_reg, data_next;
+
+	wire	[31:0]	q_a_wire, q_b_wire;
+
+	ram4096x32 ram4096x32_unit (
+		.address_a(addr_reg),
+		.address_b(address),
+		.clock(~clk),
+		.data_a(data_reg),
+		.data_b(),
+		.wren_a(wren_reg),
+		.wren_b(1'b0),
+		.q_a(q_a_wire),
+		.q_b(q_b_wire));
+
+	// body
+	always @(posedge clk)
+	begin
+		if (reset)
+        begin
+			state_reg <= 4'b1;
+		end
+		else
+		begin
+			state_reg <= state_next;
+			wren_reg <= wren_next;
+			addr_reg <= addr_next;
+			data_reg <= data_next;
+			led_data_reg[0] <= led_data_next[0];
+			led_data_reg[1] <= led_data_next[1];
+			led_data_reg[2] <= led_data_next[2];
+			led_data_reg[3] <= led_data_next[3];
+		end
+	end
+
+	always @*
+	begin
+		state_next = state_reg;
+		wren_next = wren_reg;
+		addr_next = addr_reg;
+		data_next = data_reg;
+		led_data_next[0] = led_data_reg[0];
+		led_data_next[1] = led_data_reg[1];
+		led_data_next[2] = led_data_reg[2];
+		led_data_next[3] = led_data_reg[3];
+		case (state_reg)
+			0: ; // nothing to do
+			1: 
+			begin
+				// start reset
+				wren_next = 1'b1;
+				addr_next = 0;
+				data_next = 0;
+				led_data_next[0] = 0;
+				led_data_next[1] = 0;
+				led_data_next[2] = 0;
+				led_data_next[3] = 0;
+				state_next = 4'd2;
+			end
+			
+			2:
+			begin
+				// write zeros
+				if (&addr_reg)
+				begin
+					state_next = 4'd3;
+				end
+				else
+				begin
+					addr_next = addr_reg + 12'd1;
+				end
+			end
+	
+			3:
+			begin
+				// read
+				wren_next = 1'b0;
+				if (&data_reg)
+				begin
+					state_next = 4'd0;
+				end
+				else if (data_ready)
+				begin
+					// set addr
+					addr_next = data;
+					state_next = 4'd4;
+				end
+			end
+
+			4:
+			begin
+				// increment and write
+				wren_next = 1'b1;
+				data_next = q_a_wire + 32'd1;
+				led_data_next[addr_reg>>10] = q_a_wire;
+				state_next = 4'd3;
+			end
+
+			default:
+			begin
+				state_next = 4'd0;
+			end
+		endcase
+	end
+
+	// output logic
+	assign	q			=	q_b_wire;
+	assign	led[0]		=	led_data_reg[0][23];
+	assign	led[1]		=	led_data_reg[1][23];
+	assign	led[2]		=	led_data_reg[2][23];
+	assign	led[3]		=	led_data_reg[3][23];
+
+endmodule
Index: /trunk/MultiChannelCOM/oscilloscope.v
===================================================================
--- /trunk/MultiChannelCOM/oscilloscope.v	(revision 2)
+++ /trunk/MultiChannelCOM/oscilloscope.v	(revision 2)
@@ -0,0 +1,135 @@
+module oscilloscope
+	(
+		input	wire			clk, reset,
+		input	wire			data_ready,
+		input	wire	[15:0]  raw_data, uwt_data, threshold,
+		input	wire	[9:0]	address,
+		output	wire	[9:0]	start_address,
+		output	wire	[15:0]  q
+	);
+	
+	// signal declaration
+	reg		[3:0]	state_reg, state_next;
+
+	reg				wren_reg, wren_next;
+	reg		[9:0]	addr_reg, addr_next;
+	reg		[15:0]	data_reg, data_next;
+
+	reg				trig_reg, trig_next;
+	reg		[9:0]	trig_addr_reg, trig_addr_next;
+	reg		[9:0]	counter_reg, counter_next;
+
+	wire	[15:0]	q_wire;
+
+	ram1024x16 ram1024x16_unit (
+		.clock(~clk),
+		.data(data_reg),
+		.rdaddress(address),
+		.wraddress(addr_reg),
+		.wren(wren_reg),
+		.q(q_wire));
+
+	// body
+	always @(posedge clk)
+	begin
+		if (reset)
+        begin
+			state_reg <= 4'b1;
+		end
+		else
+		begin
+			state_reg <= state_next;
+			wren_reg <= wren_next;
+			addr_reg <= addr_next;
+			data_reg <= data_next;
+			trig_reg <= trig_next;
+			trig_addr_reg <= trig_addr_next;
+			counter_reg <= counter_next;
+		end
+	end
+
+	always @*
+	begin
+		state_next = state_reg;
+		wren_next = wren_reg;
+		addr_next = addr_reg;
+		data_next = data_reg;
+		trig_next = trig_reg;
+		trig_addr_next = trig_addr_reg;
+		counter_next = counter_reg;
+
+		case (state_reg)
+			0: ; // nothing to do  
+			1: 
+			begin
+				// start reset
+				wren_next = 1'b1;
+				addr_next = 0;
+				data_next = 0;
+				trig_next = 0;
+				trig_addr_next = 0;
+				counter_next = 0;
+				state_next = 4'd2;
+			end
+			
+			2:
+			begin
+				// write zeros
+				if (&addr_reg)
+				begin
+					wren_next = 1'b0;
+					state_next = 4'd3;
+				end
+				else
+				begin
+					addr_next = addr_reg + 10'd1;
+				end
+			end
+	
+			3:
+			begin
+				if (&counter_reg)
+				begin
+					state_next = 4'd0;
+				end
+				else if (data_ready)
+				begin
+					// start write
+					wren_next = 1'b1;
+					data_next = raw_data;
+					if ((~trig_reg)
+						& (counter_reg == 10'd512)
+						& (uwt_data >= threshold))
+					begin
+						// trigger
+						trig_next = 1'b1;
+						trig_addr_next = addr_reg;
+					end
+					state_next <= 4'd4;
+				end
+			end
+
+			4:
+			begin
+				// stop write
+				wren_next <= 1'b0;
+				addr_next = addr_reg + 10'd1;
+				if (trig_reg | (counter_reg < 10'd512))
+				begin
+					counter_next = counter_reg + 10'd1;
+				end
+				state_next = 4'd3;
+			end
+
+			default:
+			begin
+				state_next = 4'd0;
+			end
+		endcase
+	end
+
+	// output logic
+	assign	q				=	q_wire;
+	assign	start_address	=	trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;
+
+endmodule
Index: /trunk/MultiChannelCOM/ram1024x16.v
===================================================================
--- /trunk/MultiChannelCOM/ram1024x16.v	(revision 2)
+++ /trunk/MultiChannelCOM/ram1024x16.v	(revision 2)
@@ -0,0 +1,215 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram1024x16.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram1024x16 (
+	clock,
+	data,
+	rdaddress,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[15:0]  data;
+	input	[9:0]  rdaddress;
+	input	[9:0]  wraddress;
+	input	  wren;
+	output	[15:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [15:0] sub_wire0;
+	wire [15:0] q = sub_wire0[15:0];
+
+	altsyncram	altsyncram_component (
+				.wren_a (wren),
+				.clock0 (clock),
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.data_a (data),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({16{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone II",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.numwords_b = 1024,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.widthad_b = 10,
+		altsyncram_component.width_a = 16,
+		altsyncram_component.width_b = 16,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: ECC NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL rdaddress[9..0]
+// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL wraddress[9..0]
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Index: /trunk/MultiChannelCOM/ram4096x32.v
===================================================================
--- /trunk/MultiChannelCOM/ram4096x32.v	(revision 2)
+++ /trunk/MultiChannelCOM/ram4096x32.v	(revision 2)
@@ -0,0 +1,240 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ram4096x32.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ram4096x32 (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[11:0]  address_a;
+	input	[11:0]  address_b;
+	input	  clock;
+	input	[31:0]  data_a;
+	input	[31:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[31:0]  q_a;
+	output	[31:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  wren_a;
+	tri1	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [31:0] sub_wire0;
+	wire [31:0] sub_wire1;
+	wire [31:0] q_a = sub_wire0[31:0];
+	wire [31:0] q_b = sub_wire1[31:0];
+
+	altsyncram	altsyncram_component (
+				.wren_a (wren_a),
+				.clock0 (clock),
+				.wren_b (wren_b),
+				.address_a (address_a),
+				.address_b (address_b),
+				.data_a (data_a),
+				.data_b (data_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "Cyclone II",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 4096,
+		altsyncram_component.numwords_b = 4096,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
+		altsyncram_component.widthad_a = 12,
+		altsyncram_component.widthad_b = 12,
+		altsyncram_component.width_a = 32,
+		altsyncram_component.width_b = 32,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: ECC NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
+// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL data_a[31..0]
+// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL data_b[31..0]
+// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL q_a[31..0]
+// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL q_b[31..0]
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
+// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
+// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
+// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
+// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Index: /trunk/MultiChannelCOM/uart.v
===================================================================
--- /trunk/MultiChannelCOM/uart.v	(revision 2)
+++ /trunk/MultiChannelCOM/uart.v	(revision 2)
@@ -0,0 +1,54 @@
+//Listing 8.4
+module uart
+   #( // Default setting:
+      // 19,200 baud, 8 data bits, 1 stop bit, 2^2 FIFO
+      parameter DBIT = 8,     // # data bits
+                SB_TICK = 16, // # ticks for stop bits, 16/24/32
+                              // for 1/1.5/2 stop bits
+                DVSR = 163,   // baud rate divisor
+                              // DVSR = 50M/(16*baud rate)
+                DVSR_BIT = 8, // # bits of DVSR
+                FIFO_W = 2    // # addr bits of FIFO
+                              // # words in FIFO=2^FIFO_W
+   )
+   (
+    input wire clk, reset,
+    input wire rd_uart, wr_uart, rx,
+    input wire [7:0] w_data,
+    output wire tx_full, rx_empty, tx,
+    output wire [7:0] r_data
+   );
+
+   // signal declaration
+   wire tick, rx_done_tick, tx_done_tick;
+   wire tx_empty, tx_fifo_not_empty;
+   wire [7:0] tx_fifo_out, rx_data_out;
+
+   // body
+//   mod_m_counter #(.M(DVSR), .N(DVSR_BIT)) baud_gen_unit
+//      (.clk(clk), .reset(reset), .q(), .max_tick(tick));
+   baud_gen #(.INC(1208), .DIV(2)) baud_gen_unit
+      (.clk(clk), .reset(reset), .max_tick(tick));
+
+   uart_rx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_rx_unit
+      (.clk(clk), .reset(reset), .rx(rx), .s_tick(tick),
+       .rx_done_tick(rx_done_tick), .dout(rx_data_out));
+
+   fifo #(.B(DBIT), .W(FIFO_W)) fifo_rx_unit
+      (.clk(clk), .reset(reset), .rd(rd_uart),
+       .wr(rx_done_tick), .w_data(rx_data_out),
+       .empty(rx_empty), .full(), .r_data(r_data));
+
+   fifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit
+      (.clk(clk), .reset(reset), .rd(tx_done_tick),
+       .wr(wr_uart), .w_data(w_data), .empty(tx_empty),
+       .full(tx_full), .r_data(tx_fifo_out));
+
+   uart_tx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_tx_unit
+      (.clk(clk), .reset(reset), .tx_start(tx_fifo_not_empty),
+       .s_tick(tick), .din(tx_fifo_out),
+       .tx_done_tick(tx_done_tick), .tx(tx));
+
+   assign tx_fifo_not_empty = ~tx_empty;
+
+endmodule
Index: /trunk/MultiChannelCOM/uart_rx.v
===================================================================
--- /trunk/MultiChannelCOM/uart_rx.v	(revision 2)
+++ /trunk/MultiChannelCOM/uart_rx.v	(revision 2)
@@ -0,0 +1,97 @@
+//Listing 8.1
+module uart_rx
+   #(
+     parameter DBIT = 8,     // # data bits
+               SB_TICK = 16  // # ticks for stop bits
+   )
+   (
+    input wire clk, reset,
+    input wire rx, s_tick,
+    output reg rx_done_tick,
+    output wire [7:0] dout
+   );
+
+   // symbolic state declaration
+   localparam [1:0]
+      idle  = 2'b00,
+      start = 2'b01,
+      data  = 2'b10,
+      stop  = 2'b11;
+
+   // signal declaration
+   reg [1:0] state_reg, state_next;
+   reg [3:0] s_reg, s_next;
+   reg [2:0] n_reg, n_next;
+   reg [7:0] b_reg, b_next;
+
+   // body
+   // FSMD state & data registers
+   always @(posedge clk, posedge reset)
+      if (reset)
+         begin
+            state_reg <= idle;
+            s_reg <= 0;
+            n_reg <= 0;
+            b_reg <= 0;
+         end
+      else
+         begin
+            state_reg <= state_next;
+            s_reg <= s_next;
+            n_reg <= n_next;
+            b_reg <= b_next;
+         end
+
+   // FSMD next-state logic
+   always @*
+   begin
+      state_next = state_reg;
+      rx_done_tick = 1'b0;
+      s_next = s_reg;
+      n_next = n_reg;
+      b_next = b_reg;
+      case (state_reg)
+         idle:
+            if (~rx)
+               begin
+                  state_next = start;
+                  s_next = 0;
+               end
+         start:
+            if (s_tick)
+               if (s_reg==7)
+                  begin
+                     state_next = data;
+                     s_next = 0;
+                     n_next = 0;
+                  end
+               else
+                  s_next = s_reg + 1;
+         data:
+            if (s_tick)
+               if (s_reg==15)
+                  begin
+                     s_next = 0;
+                     b_next = {rx, b_reg[7:1]};
+                     if (n_reg==(DBIT-1))
+                        state_next = stop ;
+                      else
+                        n_next = n_reg + 1;
+                   end
+               else
+                  s_next = s_reg + 1;
+         stop:
+            if (s_tick)
+               if (s_reg==(SB_TICK-1))
+                  begin
+                     state_next = idle;
+                     rx_done_tick =1'b1;
+                  end
+               else
+                  s_next = s_reg + 1;
+      endcase
+   end
+   // output
+   assign dout = b_reg;
+
+endmodule
Index: /trunk/MultiChannelCOM/uart_tx.v
===================================================================
--- /trunk/MultiChannelCOM/uart_tx.v	(revision 2)
+++ /trunk/MultiChannelCOM/uart_tx.v	(revision 2)
@@ -0,0 +1,115 @@
+//Listing 8.3
+module uart_tx
+   #(
+     parameter DBIT = 8,     // # data bits
+               SB_TICK = 16  // # ticks for stop bits
+   )
+   (
+    input wire clk, reset,
+    input wire tx_start, s_tick,
+    input wire [7:0] din,
+    output reg tx_done_tick,
+    output wire tx
+   );
+
+   // symbolic state declaration
+   localparam [1:0]
+      idle  = 2'b00,
+      start = 2'b01,
+      data  = 2'b10,
+      stop  = 2'b11;
+
+   // signal declaration
+   reg [1:0] state_reg, state_next;
+   reg [3:0] s_reg, s_next;
+   reg [2:0] n_reg, n_next;
+   reg [7:0] b_reg, b_next;
+   reg tx_reg, tx_next;
+
+   // body
+   // FSMD state & data registers
+   always @(posedge clk, posedge reset)
+      if (reset)
+         begin
+            state_reg <= idle;
+            s_reg <= 0;
+            n_reg <= 0;
+            b_reg <= 0;
+            tx_reg <= 1'b1;
+         end
+      else
+         begin
+            state_reg <= state_next;
+            s_reg <= s_next;
+            n_reg <= n_next;
+            b_reg <= b_next;
+            tx_reg <= tx_next;
+         end
+
+   // FSMD next-state logic & functional units
+   always @*
+   begin
+      state_next = state_reg;
+      tx_done_tick = 1'b0;
+      s_next = s_reg;
+      n_next = n_reg;
+      b_next = b_reg;
+      tx_next = tx_reg ;
+      case (state_reg)
+         idle:
+            begin
+               tx_next = 1'b1;
+               if (tx_start)
+                  begin
+                     state_next = start;
+                     s_next = 0;
+                     b_next = din;
+                  end
+            end
+         start:
+            begin
+               tx_next = 1'b0;
+               if (s_tick)
+                  if (s_reg==15)
+                     begin
+                        state_next = data;
+                        s_next = 0;
+                        n_next = 0;
+                     end
+                  else
+                     s_next = s_reg + 1;
+            end
+         data:
+            begin
+               tx_next = b_reg[0];
+               if (s_tick)
+                  if (s_reg==15)
+                     begin
+                        s_next = 0;
+                        b_next = b_reg >> 1;
+                        if (n_reg==(DBIT-1))
+                           state_next = stop ;
+                        else
+                           n_next = n_reg + 1;
+                     end
+                  else
+                     s_next = s_reg + 1;
+            end
+         stop:
+            begin
+               tx_next = 1'b1;
+               if (s_tick)
+                  if (s_reg==(SB_TICK-1))
+                     begin
+                        state_next = idle;
+                        tx_done_tick = 1'b1;
+                     end
+                  else
+                     s_next = s_reg + 1;
+            end
+      endcase
+   end
+   // output
+   assign tx = tx_reg;
+
+endmodule
Index: /trunk/MultiChannelCOM/uwt_bior31.v
===================================================================
--- /trunk/MultiChannelCOM/uwt_bior31.v	(revision 2)
+++ /trunk/MultiChannelCOM/uwt_bior31.v	(revision 2)
@@ -0,0 +1,90 @@
+module uwt_bior31
+	#(
+		parameter	L	=	1 // transform level
+	)
+	(
+		input	wire			clk, reset,
+		input	wire	[31:0]	x,
+		output	wire	[31:0]	d,
+		output	wire	[31:0]	a,
+		output	wire	[31:0]	peak,
+		output	wire	[1:0]	flag
+	);
+
+	localparam	index1		=	1 << (L - 1);
+	localparam	index2		=	2 << (L - 1);
+	localparam	index3		=	3 << (L - 1);
+	localparam	peak_index	=	((3 << (L - 1)) + 1) >> 1;
+	localparam	peak_shift	=	((L - 1) << 1) + (L - 1);
+	localparam	zero		=	32'h80000000;
+	
+	// Tapped delay line
+	reg		[31:0]	tap [index3:0];
+	
+	reg		[31:0]	d_reg, d_next;
+	reg		[31:0]	a_reg, a_next;
+	reg		[31:0]	peak_reg, peak_next;
+
+	reg		[1:0]	flag_reg;
+
+	integer			i;
+	
+	always @(posedge clk, posedge reset)
+	begin
+		if (reset)
+		begin
+			d_reg <= 0;
+			a_reg <= 0;
+			peak_reg <= 0;
+			flag_reg <= 0;
+
+			for(i = 0; i <= index3; i = i + 1)
+			begin
+				tap[i] <= 0;
+			end
+		end
+		else
+		begin
+			d_reg <= d_next;
+			a_reg <= a_next;
+			peak_reg <= peak_next;
+			
+			flag_reg[0] <= (d_reg > zero) & (d_next <= zero);
+			flag_reg[1] <= (d_reg < zero) & (d_next >= zero);
+	
+			// Tapped delay line: shift one
+			for(i = 0; i < index3; i = i + 1)
+			begin
+				tap[i+1] <= tap[i];
+			end
+			
+			// Input in register 0
+			tap[0] <= x;
+		end
+	end
+	
+	always @*
+	begin
+		// Compute d and a with the filter coefficients.
+		// The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1]
+
+		d_next = zero - (tap[index3])
+			   - (tap[index2] << 1) - tap[index2]
+			   + (tap[index1] << 1) + tap[index1]
+			   + (tap[0]);
+		
+		a_next = (tap[index3])
+			   + (tap[index2] << 1) + tap[index2]
+			   + (tap[index1] << 1) + tap[index1]
+			   + (tap[0]);
+
+		peak_next = (tap[peak_index] >> peak_shift);
+	end
+
+	// output logic
+	assign	d		=	d_reg;
+	assign	a		=	a_reg;
+	assign	peak	=	peak_reg;
+	assign	flag	=	flag_reg;
+
+endmodule