Index: trunk/MultiChannelUSB/Paella.dpf =================================================================== --- trunk/MultiChannelUSB/Paella.dpf (revision 27) +++ trunk/MultiChannelUSB/Paella.dpf (revision 27) @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/MultiChannelUSB/Paella.qpf =================================================================== --- trunk/MultiChannelUSB/Paella.qpf (revision 27) +++ trunk/MultiChannelUSB/Paella.qpf (revision 27) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Web Edition +# Date created = 14:14:14 August 28, 2009 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "14:14:14 August 28, 2009" + +# Revisions + +PROJECT_REVISION = "Paella" Index: trunk/MultiChannelUSB/Paella.qsf =================================================================== --- trunk/MultiChannelUSB/Paella.qsf (revision 27) +++ trunk/MultiChannelUSB/Paella.qsf (revision 27) @@ -0,0 +1,317 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Web Edition +# Date created = 14:14:14 August 28, 2009 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Paella_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY Paella +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 9.0 +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VERILOG_FILE adc_fifo.v +set_global_assignment -name VERILOG_FILE fifo32x8.v +set_global_assignment -name VERILOG_FILE fifo32x12.v +set_global_assignment -name VERILOG_FILE fifo32x14.v +set_global_assignment -name VERILOG_FILE histogram.v +set_global_assignment -name VERILOG_FILE oscilloscope.v +set_global_assignment -name VERILOG_FILE pll.v +set_global_assignment -name VERILOG_FILE ram1024x16.v +set_global_assignment -name VERILOG_FILE ram4096x32.v +set_global_assignment -name VERILOG_FILE usb_fifo.v +set_global_assignment -name VERILOG_FILE uwt_bior31.v +set_global_assignment -name VERILOG_FILE Paella.v +set_global_assignment -name MISC_FILE Paella.dpf +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3 +set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 4 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 5 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8 +set_location_assignment PIN_21 -to LED +set_location_assignment PIN_33 -to CLK_50MHz +set_location_assignment PIN_37 -to USB_PA[7] +set_location_assignment PIN_38 -to USB_PA[6] +set_location_assignment PIN_39 -to USB_PA[5] +set_location_assignment PIN_41 -to USB_PA[4] +set_location_assignment PIN_43 -to USB_PA[3] +set_location_assignment PIN_44 -to USB_PA[2] +set_location_assignment PIN_45 -to USB_PA[1] +set_location_assignment PIN_46 -to USB_PA[0] +set_location_assignment PIN_49 -to USB_FLAGC +set_location_assignment PIN_50 -to USB_FLAGB +set_location_assignment PIN_51 -to USB_FLAGA +set_location_assignment PIN_52 -to USB_PB[7] +set_location_assignment PIN_55 -to USB_PB[6] +set_location_assignment PIN_56 -to USB_PB[5] +set_location_assignment PIN_57 -to USB_PB[4] +set_location_assignment PIN_63 -to USB_SLRD +set_location_assignment PIN_64 -to USB_SLWR +set_location_assignment PIN_65 -to USB_IFCLK +set_location_assignment PIN_68 -to USB_PB[0] +set_location_assignment PIN_69 -to USB_PB[1] +set_location_assignment PIN_70 -to USB_PB[2] +set_location_assignment PIN_71 -to USB_PB[3] +set_location_assignment PIN_72 -to CON_A[0] +set_location_assignment PIN_73 -to CON_A[1] +set_location_assignment PIN_76 -to CON_A[2] +set_location_assignment PIN_78 -to CON_A[3] +set_location_assignment PIN_80 -to CON_A[4] +set_location_assignment PIN_81 -to CON_A[5] +set_location_assignment PIN_82 -to CON_A[6] +set_location_assignment PIN_83 -to TRG[0] +set_location_assignment PIN_84 -to TRG[1] +set_location_assignment PIN_87 -to TRG[2] +set_location_assignment PIN_88 -to TRG[3] +set_location_assignment PIN_91 -to ADC_DCO +set_location_assignment PIN_92 -to "ADC_DCO(n)" +set_instance_assignment -name IO_STANDARD LVDS -to ADC_DCO +set_location_assignment PIN_93 -to ADC_FCO +set_location_assignment PIN_94 -to "ADC_FCO(n)" +set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO +set_location_assignment PIN_98 -to ADC_DB +set_location_assignment PIN_99 -to "ADC_DB(n)" +set_instance_assignment -name IO_STANDARD LVDS -to ADC_DB +set_location_assignment PIN_108 -to ADC_DC +set_location_assignment PIN_109 -to "ADC_DC(n)" +set_instance_assignment -name IO_STANDARD LVDS -to ADC_DC +set_location_assignment PIN_119 -to ADC_DD +set_location_assignment PIN_120 -to "ADC_DD(n)" +set_instance_assignment -name IO_STANDARD LVDS -to ADC_DD +set_location_assignment PIN_126 -to CON_B[0] +set_location_assignment PIN_127 -to CON_B[1] +set_location_assignment PIN_128 -to CON_B[2] +set_location_assignment PIN_131 -to CON_B[3] +set_location_assignment PIN_132 -to CON_B[4] +set_location_assignment PIN_133 -to CON_B[5] +set_location_assignment PIN_134 -to CON_B[6] +set_location_assignment PIN_135 -to CON_B[7] +set_location_assignment PIN_137 -to CON_B[8] +set_location_assignment PIN_139 -to CON_B[9] +set_location_assignment PIN_142 -to CON_B[10] +set_location_assignment PIN_143 -to CON_B[11] +set_location_assignment PIN_144 -to CON_B[12] +set_location_assignment PIN_145 -to CON_B[13] +set_location_assignment PIN_146 -to CON_B[14] +set_location_assignment PIN_147 -to CON_B[15] +set_location_assignment PIN_149 -to CON_BCLK[0] +set_location_assignment PIN_150 -to CON_BCLK[1] +set_location_assignment PIN_151 -to CON_CCLK[0] +set_location_assignment PIN_152 -to CON_CCLK[1] +set_location_assignment PIN_159 -to CON_C[0] +set_location_assignment PIN_160 -to CON_C[1] +set_location_assignment PIN_161 -to CON_C[2] +set_location_assignment PIN_162 -to CON_C[3] +set_location_assignment PIN_164 -to CON_C[4] +set_location_assignment PIN_166 -to CON_C[5] +set_location_assignment PIN_167 -to CON_C[6] +set_location_assignment PIN_168 -to CON_C[7] +set_location_assignment PIN_169 -to CON_C[8] +set_location_assignment PIN_171 -to CON_C[9] +set_location_assignment PIN_173 -to CON_C[10] +set_location_assignment PIN_176 -to CON_C[11] +set_location_assignment PIN_177 -to CON_C[12] +set_location_assignment PIN_181 -to RAM_DQB[7] +set_location_assignment PIN_182 -to RAM_ADDR[6] +set_location_assignment PIN_183 -to RAM_ADDR[7] +set_location_assignment PIN_184 -to RAM_CE1 +set_location_assignment PIN_186 -to RAM_CLK +set_location_assignment PIN_187 -to RAM_WE +set_location_assignment PIN_188 -to RAM_ADDR[8] +set_location_assignment PIN_189 -to RAM_ADDR[9] +set_location_assignment PIN_194 -to RAM_ADDR[10] +set_location_assignment PIN_195 -to RAM_ADDR[11] +set_location_assignment PIN_196 -to RAM_ADDR[12] +set_location_assignment PIN_197 -to RAM_DQAP +set_location_assignment PIN_200 -to RAM_DQA[0] +set_location_assignment PIN_201 -to RAM_DQA[1] +set_location_assignment PIN_202 -to RAM_DQA[2] +set_location_assignment PIN_203 -to RAM_DQA[3] +set_location_assignment PIN_207 -to RAM_DQA[4] +set_location_assignment PIN_214 -to RAM_DQA[5] +set_location_assignment PIN_216 -to RAM_DQA[6] +set_location_assignment PIN_217 -to RAM_DQA[7] +set_location_assignment PIN_218 -to RAM_ADDR[13] +set_location_assignment PIN_219 -to RAM_ADDR[14] +set_location_assignment PIN_221 -to RAM_ADDR[15] +set_location_assignment PIN_223 -to RAM_ADDR[16] +set_location_assignment PIN_224 -to RAM_ADDR[17] +set_location_assignment PIN_226 -to RAM_ADDR[18] +set_location_assignment PIN_230 -to RAM_ADDR[19] +set_location_assignment PIN_231 -to RAM_ADDR[0] +set_location_assignment PIN_232 -to RAM_ADDR[1] +set_location_assignment PIN_233 -to RAM_ADDR[2] +set_location_assignment PIN_234 -to RAM_ADDR[3] +set_location_assignment PIN_235 -to RAM_ADDR[4] +set_location_assignment PIN_236 -to RAM_ADDR[5] +set_location_assignment PIN_237 -to RAM_DQBP +set_location_assignment PIN_238 -to RAM_DQB[0] +set_location_assignment PIN_239 -to RAM_DQB[1] +set_location_assignment PIN_240 -to RAM_DQB[2] +set_location_assignment PIN_4 -to RAM_DQB[3] +set_location_assignment PIN_5 -to RAM_DQB[4] +set_location_assignment PIN_6 -to RAM_DQB[5] +set_location_assignment PIN_9 -to RAM_DQB[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_50MHz +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_CCLK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_CCLK[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CE1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7] Index: trunk/MultiChannelUSB/Paella.v =================================================================== --- trunk/MultiChannelUSB/Paella.v (revision 27) +++ trunk/MultiChannelUSB/Paella.v (revision 27) @@ -0,0 +1,225 @@ +module Paella + ( + input wire CLK_50MHz, + output wire LED, + + inout wire [3:0] TRG, + inout wire [6:0] CON_A, + inout wire [15:0] CON_B, + inout wire [12:0] CON_C, + input wire [1:0] CON_BCLK, + input wire [1:0] CON_CCLK, + + input wire ADC_DCO, + input wire ADC_FCO, + input wire ADC_DB, + input wire ADC_DC, + input wire ADC_DD, + + output wire USB_SLRD, + output wire USB_SLWR, + input wire USB_IFCLK, + input wire USB_FLAGA, // EMPTY flag for EP6 + input wire USB_FLAGB, // FULL flag for EP8 + input wire USB_FLAGC, + inout wire [7:0] USB_PA, + inout wire [7:0] USB_PB, + + output wire RAM_CLK, + output wire RAM_CE1, + output wire RAM_WE, + output wire [19:0] RAM_ADDR, + inout wire RAM_DQAP, + inout wire [7:0] RAM_DQA, + inout wire RAM_DQBP, + inout wire [7:0] RAM_DQB + ); + + // Turn output ports off + assign RAM_CLK = 1'b0; + assign RAM_CE1 = 1'b0; + assign RAM_WE = 1'b0; + assign RAM_ADDR = 20'h00000; + + // Turn inout ports to tri-state + assign TRG = 4'bz; + assign CON_A = 7'bz; + assign CON_B = 16'bz; + assign CON_C = 13'bz; + assign USB_PA = {1'bz, ~usb_pktend, usb_addr, 1'bz, ~usb_rden, 2'bz}; + assign RAM_DQAP = 1'bz; + assign RAM_DQA = 8'bz; + assign RAM_DQBP = 1'bz; + assign RAM_DQB = 8'bz; + + reg [31:0] counter; + assign LED = counter[24]; +// assign LED = usb_fifo_led; + + wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend; + wire usb_fifo_aclr, usb_fifo_led; + wire usb_fifo_tx_wrreq, usb_fifo_rx_rdreq; + wire usb_fifo_tx_full, usb_fifo_rx_empty; + wire [7:0] usb_fifo_tx_data, usb_fifo_rx_data; + wire [1:0] usb_addr; + + assign USB_SLRD = ~usb_rdreq; + assign USB_SLWR = ~usb_wrreq; + + usb_fifo usb_fifo_unit + ( + .usb_clk(USB_IFCLK), + .usb_data(USB_PB), + .usb_full(~USB_FLAGB), + .usb_empty(~USB_FLAGA), + .usb_wrreq(usb_wrreq), + .usb_rdreq(usb_rdreq), + .usb_rden(usb_rden), + .usb_pktend(usb_pktend), + .usb_addr(usb_addr), + .clk(CLK_50MHz), + .aclr(usb_fifo_aclr), + .tx_wrreq(usb_fifo_tx_wrreq), + .rx_rdreq(usb_fifo_rx_rdreq), + .tx_data(usb_fifo_tx_data), + .tx_full(usb_fifo_tx_full), + .rx_empty(usb_fifo_rx_empty), +// .led(usb_fifo_led), + .rx_data(usb_fifo_rx_data) + ); + + reg [9:0] osc_counter; + reg osc_reset; + reg osc_bit_num; + wire [9:0] osc_start_addr; + reg [9:0] osc_addr; + wire [15:0] osc_q; + + reg hst_reset; + reg [1:0] hst_bit_num; + reg [11:0] hst_addr; + wire [31:0] hst_q; + + reg [3:0] state0, state1, state2; + reg adc_fifo_rdreq; + wire adc_fifo_rdempty; + reg adc_fifo_aclr; + + reg [31:0] adc_counter; + reg adc_data_ready; + wire adc_clk; + reg [11:0] adc_data; + wire [11:0] raw_data; + wire [11:0] uwt_data; + wire [1:0] uwt_flag; + + pll pll_unit( + .inclk0(CLK_50MHz), + .c0(adc_clk)); + + adc_fifo adc_fifo_unit ( + .adc_clk(adc_clk), + .adc_data(adc_data), + .aclr(adc_fifo_aclr), + .rdclk(CLK_50MHz), + .rdreq(adc_fifo_rdreq), + .rdempty(adc_fifo_rdempty), + .raw_data(raw_data), + .uwt_data({uwt_flag, uwt_data})); + + histogram histogram_unit ( + .clk(CLK_50MHz), + .reset(hst_reset), + .data_ready(adc_data_ready), + .data(raw_data), + .address(hst_addr), + .q(hst_q) + ); + + oscilloscope oscilloscope_unit ( + .clk(CLK_50MHz), + .reset(osc_reset), + .data_ready(adc_data_ready), + .raw_data(raw_data), + .uwt_data(uwt_data), + .threshold(16'd100), + .address(osc_addr), + .start_address(osc_start_addr), + .q(osc_q) + ); + + + always @ (posedge adc_clk) + begin + counter <= counter + 32'd1; + end + + always @ (posedge CLK_50MHz) + begin + case (state0) + 1: + begin + if (~adc_fifo_rdempty) + begin + adc_counter <= adc_counter + 32'd1; + adc_fifo_rdreq <= 1'b1; + adc_data_ready <= 1'b1; + state0 <= 4'd2; + end + end + + 2: + begin + adc_fifo_rdreq <= 1'b0; + adc_data_ready <= 1'b0; + state0 <= 4'd1; + end + + default: + begin + state0 <= 4'd1; + end + endcase + end + + always @ (posedge adc_clk) + begin + case (state2) + 1: + begin + adc_data <= 12'd0; + state2 <= 4'd2; + end + + 2: + begin + adc_data <= 12'd1024; + state2 <= 4'd3; + end + + 3: + begin + adc_data <= 12'd2048; + state2 <= 4'd4; + end + + 4: + begin + adc_data <= 12'd3072; + state2 <= 4'd5; + end + + 5: + begin + adc_data <= 12'd4095; + state2 <= 4'd1; + end + + default: + begin + state2 <= 4'd1; + end + endcase + end + +endmodule Index: trunk/MultiChannelUSB/adc_fifo.v =================================================================== --- trunk/MultiChannelUSB/adc_fifo.v (revision 27) +++ trunk/MultiChannelUSB/adc_fifo.v (revision 27) @@ -0,0 +1,68 @@ +module adc_fifo + ( + input wire adc_clk, + input wire [11:0] adc_data, + + input wire aclr, + input wire rdclk, + input wire rdreq, + output wire rdempty, + output wire [11:0] raw_data, + output wire [13:0] uwt_data + ); + + wire [31:0] uwt_d1, uwt_a1, uwt_peak1; + wire [31:0] uwt_d2, uwt_a2, uwt_peak2; + wire [31:0] uwt_d3, uwt_a3, uwt_peak3; + wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3; + + wire [1:0] wrfull; + + uwt_bior31 #(.L(1)) uwt_1_unit ( + .clk(adc_clk), + .x(adc_data), + .d(uwt_d1), + .a(uwt_a1), + .peak(uwt_peak1), + .flag(uwt_flag1)); + + uwt_bior31 #(.L(2)) uwt_2_unit ( + .clk(adc_clk), + .x(uwt_a1), + .d(uwt_d2), + .a(uwt_a2), + .peak(uwt_peak2), + .flag(uwt_flag2)); + + uwt_bior31 #(.L(3)) uwt_3_unit ( + .clk(adc_clk), + .x(uwt_a2), + .d(uwt_d3), + .a(uwt_a3), + .peak(uwt_peak3), + .flag(uwt_flag3)); + + + fifo32x12 fifo0 ( + .aclr(aclr), + .data(adc_data), + .rdclk(rdclk), + .rdreq(rdreq), + .wrclk(adc_clk), + .wrreq(~wrfull[0]), + .q(raw_data), + .rdempty(rdempty), + .wrfull(wrfull[0])); + + fifo32x14 fifo1 ( + .aclr(aclr), + .data({uwt_flag3, uwt_peak3[11:0]}), + .rdclk(rdclk), + .rdreq(rdreq), + .wrclk(adc_clk), + .wrreq(~wrfull[1]), + .q(uwt_data), + .rdempty(), + .wrfull(wrfull[1])); + +endmodule Index: trunk/MultiChannelUSB/fifo.v =================================================================== --- trunk/MultiChannelUSB/fifo.v (revision 27) +++ trunk/MultiChannelUSB/fifo.v (revision 27) @@ -0,0 +1,92 @@ +// Listing 4.20 +module fifo + #( + parameter B=8, // number of bits in a word + W=4 // number of address bits + ) + ( + input wire clk, reset, + input wire rd, wr, + input wire [B-1:0] w_data, + output wire empty, full, + output wire [B-1:0] r_data + ); + + //signal declaration + reg [B-1:0] array_reg [2**W-1:0]; // register array + reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ; + reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ; + reg full_reg, empty_reg, full_next, empty_next; + wire wr_en; + + // body + // register file write operation + always @(posedge clk) + if (wr_en) + array_reg[w_ptr_reg] <= w_data; + // register file read operation + assign r_data = array_reg[r_ptr_reg]; + // write enabled only when FIFO is not full + assign wr_en = wr & ~full_reg; + + // fifo control logic + // register for read and write pointers + always @(posedge clk, posedge reset) + if (reset) + begin + w_ptr_reg <= 0; + r_ptr_reg <= 0; + full_reg <= 1'b0; + empty_reg <= 1'b1; + end + else + begin + w_ptr_reg <= w_ptr_next; + r_ptr_reg <= r_ptr_next; + full_reg <= full_next; + empty_reg <= empty_next; + end + + // next-state logic for read and write pointers + always @* + begin + // successive pointer values + w_ptr_succ = w_ptr_reg + 1; + r_ptr_succ = r_ptr_reg + 1; + // default: keep old values + w_ptr_next = w_ptr_reg; + r_ptr_next = r_ptr_reg; + full_next = full_reg; + empty_next = empty_reg; + case ({wr, rd}) + // 2'b00: no op + 2'b01: // read + if (~empty_reg) // not empty + begin + r_ptr_next = r_ptr_succ; + full_next = 1'b0; + if (r_ptr_succ==w_ptr_reg) + empty_next = 1'b1; + end + 2'b10: // write + if (~full_reg) // not full + begin + w_ptr_next = w_ptr_succ; + empty_next = 1'b0; + if (w_ptr_succ==r_ptr_reg) + full_next = 1'b1; + end + 2'b11: // write and read + begin + w_ptr_next = w_ptr_succ; + r_ptr_next = r_ptr_succ; + end + endcase + end + + // output + assign full = full_reg; + assign empty = empty_reg; + +endmodule + Index: trunk/MultiChannelUSB/fifo32x12.v =================================================================== --- trunk/MultiChannelUSB/fifo32x12.v (revision 27) +++ trunk/MultiChannelUSB/fifo32x12.v (revision 27) @@ -0,0 +1,107 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo32x12.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo32x12 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + wrfull); + + input aclr; + input [11:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [11:0] q; + output rdempty; + output wrfull; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire sub_wire1; + wire [11:0] sub_wire2; + wire rdempty = sub_wire0; + wire wrfull = sub_wire1; + wire [11:0] q = sub_wire2[11:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrfull (sub_wire1), + .q (sub_wire2) + // synopsys translate_off + , + .rdfull (), + .rdusedw (), + .wrempty (), + .wrusedw () + // synopsys translate_on + ); + defparam + dcfifo_component.intended_device_family = "Cyclone III", + dcfifo_component.lpm_numwords = 32, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 12, + dcfifo_component.lpm_widthu = 5, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.rdsync_delaypipe = 4, + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON", + dcfifo_component.write_aclr_synch = "OFF", + dcfifo_component.wrsync_delaypipe = 4; + + +endmodule Index: trunk/MultiChannelUSB/fifo32x14.v =================================================================== --- trunk/MultiChannelUSB/fifo32x14.v (revision 27) +++ trunk/MultiChannelUSB/fifo32x14.v (revision 27) @@ -0,0 +1,107 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo32x14.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo32x14 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + wrfull); + + input aclr; + input [13:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [13:0] q; + output rdempty; + output wrfull; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire sub_wire1; + wire [13:0] sub_wire2; + wire rdempty = sub_wire0; + wire wrfull = sub_wire1; + wire [13:0] q = sub_wire2[13:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrfull (sub_wire1), + .q (sub_wire2) + // synopsys translate_off + , + .rdfull (), + .rdusedw (), + .wrempty (), + .wrusedw () + // synopsys translate_on + ); + defparam + dcfifo_component.intended_device_family = "Cyclone III", + dcfifo_component.lpm_numwords = 32, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 14, + dcfifo_component.lpm_widthu = 5, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.rdsync_delaypipe = 4, + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON", + dcfifo_component.write_aclr_synch = "OFF", + dcfifo_component.wrsync_delaypipe = 4; + + +endmodule Index: trunk/MultiChannelUSB/fifo32x8.v =================================================================== --- trunk/MultiChannelUSB/fifo32x8.v (revision 27) +++ trunk/MultiChannelUSB/fifo32x8.v (revision 27) @@ -0,0 +1,107 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo32x8.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo32x8 ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + wrfull); + + input aclr; + input [7:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [7:0] q; + output rdempty; + output wrfull; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire sub_wire1; + wire [7:0] sub_wire2; + wire rdempty = sub_wire0; + wire wrfull = sub_wire1; + wire [7:0] q = sub_wire2[7:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrfull (sub_wire1), + .q (sub_wire2) + // synopsys translate_off + , + .rdfull (), + .rdusedw (), + .wrempty (), + .wrusedw () + // synopsys translate_on + ); + defparam + dcfifo_component.intended_device_family = "Cyclone III", + dcfifo_component.lpm_numwords = 32, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 8, + dcfifo_component.lpm_widthu = 5, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.rdsync_delaypipe = 4, + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON", + dcfifo_component.write_aclr_synch = "OFF", + dcfifo_component.wrsync_delaypipe = 4; + + +endmodule Index: trunk/MultiChannelUSB/histogram.v =================================================================== --- trunk/MultiChannelUSB/histogram.v (revision 27) +++ trunk/MultiChannelUSB/histogram.v (revision 27) @@ -0,0 +1,107 @@ +module histogram + ( + input wire clk, reset, + input wire data_ready, + input wire [11:0] data, address, + output wire [31:0] q + ); + + // signal declaration + reg [3:0] state_reg, state_next; + reg wren_reg, wren_next; + reg [11:0] addr_reg, addr_next; + reg [31:0] data_reg, data_next; + + wire [31:0] q_a_wire, q_b_wire; + + ram4096x32 ram4096x32_unit ( + .address_a(addr_reg), + .address_b(address), + .clock(~clk), + .data_a(data_reg), + .data_b(), + .wren_a(wren_reg), + .wren_b(1'b0), + .q_a(q_a_wire), + .q_b(q_b_wire)); + + // body + always @(posedge clk) + begin + if (reset) + begin + state_reg <= 4'b1; + end + else + begin + state_reg <= state_next; + wren_reg <= wren_next; + addr_reg <= addr_next; + data_reg <= data_next; + end + end + + always @* + begin + state_next = state_reg; + wren_next = wren_reg; + addr_next = addr_reg; + data_next = data_reg; + case (state_reg) + 0: ; // nothing to do + 1: + begin + // start reset + wren_next = 1'b1; + addr_next = 0; + data_next = 0; + state_next = 4'd2; + end + + 2: + begin + // write zeros + if (&addr_reg) + begin + state_next = 4'd3; + end + else + begin + addr_next = addr_reg + 12'd1; + end + end + + 3: + begin + // read + wren_next = 1'b0; + if (&data_reg) + begin + state_next = 4'd0; + end + else if (data_ready) + begin + // set addr + addr_next = data; + state_next = 4'd4; + end + end + + 4: + begin + // increment and write + wren_next = 1'b1; + data_next = q_a_wire + 32'd1; + state_next = 4'd3; + end + + default: + begin + state_next = 4'd0; + end + endcase + end + + // output logic + assign q = q_b_wire; +endmodule Index: trunk/MultiChannelUSB/oscilloscope.v =================================================================== --- trunk/MultiChannelUSB/oscilloscope.v (revision 27) +++ trunk/MultiChannelUSB/oscilloscope.v (revision 27) @@ -0,0 +1,135 @@ +module oscilloscope + ( + input wire clk, reset, + input wire data_ready, + input wire [15:0] raw_data, uwt_data, threshold, + input wire [9:0] address, + output wire [9:0] start_address, + output wire [15:0] q + ); + + // signal declaration + reg [3:0] state_reg, state_next; + + reg wren_reg, wren_next; + reg [9:0] addr_reg, addr_next; + reg [15:0] data_reg, data_next; + + reg trig_reg, trig_next; + reg [9:0] trig_addr_reg, trig_addr_next; + reg [9:0] counter_reg, counter_next; + + wire [15:0] q_wire; + + ram1024x16 ram1024x16_unit ( + .clock(~clk), + .data(data_reg), + .rdaddress(address), + .wraddress(addr_reg), + .wren(wren_reg), + .q(q_wire)); + + // body + always @(posedge clk) + begin + if (reset) + begin + state_reg <= 4'b1; + end + else + begin + state_reg <= state_next; + wren_reg <= wren_next; + addr_reg <= addr_next; + data_reg <= data_next; + trig_reg <= trig_next; + trig_addr_reg <= trig_addr_next; + counter_reg <= counter_next; + end + end + + always @* + begin + state_next = state_reg; + wren_next = wren_reg; + addr_next = addr_reg; + data_next = data_reg; + trig_next = trig_reg; + trig_addr_next = trig_addr_reg; + counter_next = counter_reg; + + case (state_reg) + 0: ; // nothing to do + 1: + begin + // start reset + wren_next = 1'b1; + addr_next = 0; + data_next = 0; + trig_next = 0; + trig_addr_next = 0; + counter_next = 0; + state_next = 4'd2; + end + + 2: + begin + // write zeros + if (&addr_reg) + begin + wren_next = 1'b0; + state_next = 4'd3; + end + else + begin + addr_next = addr_reg + 10'd1; + end + end + + 3: + begin + if (&counter_reg) + begin + state_next = 4'd0; + end + else if (data_ready) + begin + // start write + wren_next = 1'b1; + data_next = raw_data; + if ((~trig_reg) + & (counter_reg == 10'd512) + & (uwt_data >= threshold)) + begin + // trigger + trig_next = 1'b1; + trig_addr_next = addr_reg; + end + state_next <= 4'd4; + end + end + + 4: + begin + // stop write + wren_next <= 1'b0; + addr_next = addr_reg + 10'd1; + if (trig_reg | (counter_reg < 10'd512)) + begin + counter_next = counter_reg + 10'd1; + end + state_next = 4'd3; + end + + default: + begin + state_next = 4'd0; + end + endcase + end + + // output logic + assign q = q_wire; + assign start_address = trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1; + +endmodule Index: trunk/MultiChannelUSB/pll.v =================================================================== --- trunk/MultiChannelUSB/pll.v (revision 27) +++ trunk/MultiChannelUSB/pll.v (revision 27) @@ -0,0 +1,146 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [4:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 5, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule Index: trunk/MultiChannelUSB/ram1024x16.v =================================================================== --- trunk/MultiChannelUSB/ram1024x16.v (revision 27) +++ trunk/MultiChannelUSB/ram1024x16.v (revision 27) @@ -0,0 +1,110 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram1024x16.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram1024x16 ( + clock, + data, + rdaddress, + wraddress, + wren, + q); + + input clock; + input [15:0] data; + input [9:0] rdaddress; + input [9:0] wraddress; + input wren; + output [15:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [15:0] q = sub_wire0[15:0]; + + altsyncram altsyncram_component ( + .wren_a (wren), + .clock0 (clock), + .address_a (wraddress), + .address_b (rdaddress), + .data_a (data), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({16{1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.numwords_b = 1024, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", + altsyncram_component.widthad_a = 10, + altsyncram_component.widthad_b = 10, + altsyncram_component.width_a = 16, + altsyncram_component.width_b = 16, + altsyncram_component.width_byteena_a = 1; + + +endmodule Index: trunk/MultiChannelUSB/ram4096x32.v =================================================================== --- trunk/MultiChannelUSB/ram4096x32.v (revision 27) +++ trunk/MultiChannelUSB/ram4096x32.v (revision 27) @@ -0,0 +1,124 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram4096x32.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 132 02/25/2009 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram4096x32 ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [11:0] address_a; + input [11:0] address_b; + input clock; + input [31:0] data_a; + input [31:0] data_b; + input wren_a; + input wren_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 wren_a; + tri1 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire [31:0] q_a = sub_wire0[31:0]; + wire [31:0] q_b = sub_wire1[31:0]; + + altsyncram altsyncram_component ( + .wren_a (wren_a), + .clock0 (clock), + .wren_b (wren_b), + .address_a (address_a), + .address_b (address_b), + .data_a (data_a), + .data_b (data_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.numwords_b = 4096, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", + altsyncram_component.widthad_a = 12, + altsyncram_component.widthad_b = 12, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule Index: trunk/MultiChannelUSB/usb_fifo.v =================================================================== --- trunk/MultiChannelUSB/usb_fifo.v (revision 27) +++ trunk/MultiChannelUSB/usb_fifo.v (revision 27) @@ -0,0 +1,108 @@ +module usb_fifo + ( + input wire usb_clk, + inout wire [7:0] usb_data, + input wire usb_full, usb_empty, + output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend, + output wire [1:0] usb_addr, + + input wire clk, aclr, + input wire tx_wrreq, rx_rdreq, + input wire [7:0] tx_data, + output wire tx_full, rx_empty, + output wire [7:0] rx_data + ); + + localparam EPRD_ADDR = 2'b10; // 6 + localparam EPWR_ADDR = 2'b11; // 8 + + // bidirectional data bus + wire usb_wren; + wire [7:0] usb_datain = usb_data; + wire [7:0] usb_dataout; + + assign usb_data = usb_wren ? usb_dataout : 8'bz; + + wire tx_rdreq, tx_empty; + wire rx_wrreq, rx_full; + + fifo32x8 fifo_tx_unit ( + .aclr(aclr), + .data(tx_data), + .rdclk(usb_clk), + .rdreq(tx_rdreq), + .wrclk(clk), + .wrreq(tx_wrreq), + .q(usb_dataout_bis), + .rdempty(tx_empty), + .wrfull(tx_full)); + + fifo32x8 fifo_rx_unit ( + .aclr(aclr), + .data(usb_datain), + .rdclk(clk), + .rdreq(rx_rdreq), + .wrclk(usb_clk), + .wrreq(rx_wrreq), + .q(rx_data), + .rdempty(rx_empty), + .wrfull(rx_full)); + + reg [31:0] counter; + + reg [2:0] state; + reg tx; + reg [7:0] dout; + + always @(posedge usb_clk) + begin + case(state) + 0: + begin + tx <= 1'b0; + counter <= 32'd0; + state <= 3'd1; + end + 1: + begin + if((~usb_full) & (counter < 32'd512)) + begin + counter <= counter + 32'd1; + state <= 3'd2; + dout <= 1; + tx <= 1'b1; + end + else + begin + tx <= 1'b0; + end + end + + 2: + begin + if((~usb_full) & (counter < 32'd512)) + begin + counter <= counter + 32'd1; + state <= 3'd1; + dout <= 0; + tx <= 1'b1; + end + else + begin + tx <= 1'b0; + end + end + + default: state <= 3'd0; + endcase + end + + assign usb_addr = 2'b11; // FIFO8 + assign usb_rdreq = 1'b0; // always TX for now + assign usb_dataout = dout; + assign usb_wrreq = tx; + assign usb_pktend = 1'b0; + assign usb_rden = 1'b0; + assign usb_wren = tx; + +endmodule Index: trunk/MultiChannelUSB/uwt_bior31.v =================================================================== --- trunk/MultiChannelUSB/uwt_bior31.v (revision 27) +++ trunk/MultiChannelUSB/uwt_bior31.v (revision 27) @@ -0,0 +1,90 @@ +module uwt_bior31 + #( + parameter L = 1 // transform level + ) + ( + input wire clk, reset, + input wire [31:0] x, + output wire [31:0] d, + output wire [31:0] a, + output wire [31:0] peak, + output wire [1:0] flag + ); + + localparam index1 = 1 << (L - 1); + localparam index2 = 2 << (L - 1); + localparam index3 = 3 << (L - 1); + localparam peak_index = ((3 << (L - 1)) + 1) >> 1; + localparam peak_shift = ((L - 1) << 1) + (L - 1); + localparam zero = 32'h80000000; + + // Tapped delay line + reg [31:0] tap [index3:0]; + + reg [31:0] d_reg, d_next; + reg [31:0] a_reg, a_next; + reg [31:0] peak_reg, peak_next; + + reg [1:0] flag_reg; + + integer i; + + always @(posedge clk, posedge reset) + begin + if (reset) + begin + d_reg <= 0; + a_reg <= 0; + peak_reg <= 0; + flag_reg <= 0; + + for(i = 0; i <= index3; i = i + 1) + begin + tap[i] <= 0; + end + end + else + begin + d_reg <= d_next; + a_reg <= a_next; + peak_reg <= peak_next; + + flag_reg[0] <= (d_reg > zero) & (d_next <= zero); + flag_reg[1] <= (d_reg < zero) & (d_next >= zero); + + // Tapped delay line: shift one + for(i = 0; i < index3; i = i + 1) + begin + tap[i+1] <= tap[i]; + end + + // Input in register 0 + tap[0] <= x; + end + end + + always @* + begin + // Compute d and a with the filter coefficients. + // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1] + + d_next = zero - (tap[index3]) + - (tap[index2] << 1) - tap[index2] + + (tap[index1] << 1) + tap[index1] + + (tap[0]); + + a_next = (tap[index3]) + + (tap[index2] << 1) + tap[index2] + + (tap[index1] << 1) + tap[index1] + + (tap[0]); + + peak_next = (tap[peak_index] >> peak_shift); + end + + // output logic + assign d = d_reg; + assign a = a_reg; + assign peak = peak_reg; + assign flag = flag_reg; + +endmodule