Index: trunk/BandeCosmique/BandeCosmique.cof
===================================================================
--- trunk/BandeCosmique/BandeCosmique.cof (revision 200)
+++ trunk/BandeCosmique/BandeCosmique.cof (revision 200)
@@ -0,0 +1,18 @@
+
+
+ EPCS16
+ EP3C25
+ BandeCosmique.jic
+ 1
+ 1
+ 7
+
+ 1
+
+ BandeCosmique.sof
+
+
+ 4
+
+
+
Index: trunk/BandeCosmique/BandeCosmique.dpf
===================================================================
--- trunk/BandeCosmique/BandeCosmique.dpf (revision 200)
+++ trunk/BandeCosmique/BandeCosmique.dpf (revision 200)
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: trunk/BandeCosmique/BandeCosmique.qpf
===================================================================
--- trunk/BandeCosmique/BandeCosmique.qpf (revision 200)
+++ trunk/BandeCosmique/BandeCosmique.qpf (revision 200)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 March 09, 2015
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "14:14:14 March 09, 2015"
+
+# Revisions
+
+PROJECT_REVISION = "BandeCosmique"
Index: trunk/BandeCosmique/BandeCosmique.qsf
===================================================================
--- trunk/BandeCosmique/BandeCosmique.qsf (revision 200)
+++ trunk/BandeCosmique/BandeCosmique.qsf (revision 200)
@@ -0,0 +1,233 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# BandeCosmique_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY main
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name MISC_FILE BandeCosmique.dpf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name FMAX_REQUIREMENT "240 MHz" -section_id "LVDS Data Clock"
+set_instance_assignment -name CLOCK_SETTINGS "LVDS Data Clock" -to ADC_DCO
+set_global_assignment -name FMAX_REQUIREMENT "20 MHz" -section_id "LVDS Frame Clock"
+set_instance_assignment -name CLOCK_SETTINGS "LVDS Frame Clock" -to ADC_FCO
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id "USB Clock"
+set_instance_assignment -name CLOCK_SETTINGS "USB Clock" -to USB_IFCLK
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 6
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
+set_location_assignment PIN_21 -to LED
+set_location_assignment PIN_33 -to USB_IFCLK
+set_location_assignment PIN_37 -to USB_PA6
+set_location_assignment PIN_38 -to USB_PA4
+set_location_assignment PIN_39 -to USB_PA2
+set_location_assignment PIN_41 -to USB_FLAGB
+set_location_assignment PIN_43 -to USB_FLAGA
+set_location_assignment PIN_44 -to USB_PB[4]
+set_location_assignment PIN_45 -to USB_PB[5]
+set_location_assignment PIN_46 -to USB_PB[6]
+set_location_assignment PIN_49 -to USB_PB[7]
+set_location_assignment PIN_50 -to USB_SLRD
+set_location_assignment PIN_51 -to USB_SLWR
+set_location_assignment PIN_52 -to USB_PB[0]
+set_location_assignment PIN_55 -to USB_PB[1]
+set_location_assignment PIN_56 -to USB_PB[2]
+set_location_assignment PIN_57 -to USB_PB[3]
+set_location_assignment PIN_137 -to "ADC_D[0](n)"
+set_location_assignment PIN_139 -to ADC_D[0]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0]
+set_location_assignment PIN_142 -to "ADC_D[1](n)"
+set_location_assignment PIN_143 -to ADC_D[1]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1]
+set_location_assignment PIN_144 -to "ADC_D[2](n)"
+set_location_assignment PIN_145 -to ADC_D[2]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2]
+set_location_assignment PIN_147 -to "ADC_D[3](n)"
+set_location_assignment PIN_148 -to ADC_D[3]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[3]
+set_location_assignment PIN_149 -to "ADC_DCO(n)"
+set_location_assignment PIN_150 -to ADC_DCO
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_DCO
+set_location_assignment PIN_151 -to "ADC_FCO(n)"
+set_location_assignment PIN_152 -to ADC_FCO
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
+set_location_assignment PIN_159 -to "ADC_D[4](n)"
+set_location_assignment PIN_160 -to ADC_D[4]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[4]
+set_location_assignment PIN_162 -to "ADC_D[5](n)"
+set_location_assignment PIN_164 -to ADC_D[5]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[5]
+set_location_assignment PIN_181 -to RAM_ADDR[12]
+set_location_assignment PIN_182 -to RAM_DQAP
+set_location_assignment PIN_183 -to RAM_DQA[0]
+set_location_assignment PIN_184 -to RAM_DQA[1]
+set_location_assignment PIN_185 -to RAM_DQA[2]
+set_location_assignment PIN_186 -to RAM_DQA[3]
+set_location_assignment PIN_187 -to RAM_DQA[4]
+set_location_assignment PIN_188 -to RAM_DQA[5]
+set_location_assignment PIN_189 -to RAM_DQA[6]
+set_location_assignment PIN_194 -to RAM_DQA[7]
+set_location_assignment PIN_195 -to RAM_ADDR[13]
+set_location_assignment PIN_196 -to RAM_ADDR[14]
+set_location_assignment PIN_197 -to RAM_ADDR[15]
+set_location_assignment PIN_200 -to RAM_ADDR[16]
+set_location_assignment PIN_201 -to RAM_ADDR[17]
+set_location_assignment PIN_202 -to RAM_ADDR[18]
+set_location_assignment PIN_203 -to RAM_ADDR[19]
+set_location_assignment PIN_207 -to RAM_ADDR[20]
+set_location_assignment PIN_210 -to CLK_100MHz
+set_location_assignment PIN_214 -to RAM_ADDR[21]
+set_location_assignment PIN_216 -to RAM_ADDR[0]
+set_location_assignment PIN_217 -to RAM_ADDR[1]
+set_location_assignment PIN_218 -to RAM_ADDR[2]
+set_location_assignment PIN_219 -to RAM_ADDR[3]
+set_location_assignment PIN_221 -to RAM_ADDR[4]
+set_location_assignment PIN_223 -to RAM_ADDR[5]
+set_location_assignment PIN_224 -to RAM_DQBP
+set_location_assignment PIN_226 -to RAM_DQB[0]
+set_location_assignment PIN_230 -to RAM_DQB[1]
+set_location_assignment PIN_231 -to RAM_DQB[2]
+set_location_assignment PIN_232 -to RAM_DQB[3]
+set_location_assignment PIN_233 -to RAM_DQB[4]
+set_location_assignment PIN_234 -to RAM_DQB[5]
+set_location_assignment PIN_235 -to RAM_DQB[6]
+set_location_assignment PIN_236 -to RAM_DQB[7]
+set_location_assignment PIN_237 -to RAM_ADDR[6]
+set_location_assignment PIN_238 -to RAM_ADDR[7]
+set_location_assignment PIN_239 -to RAM_CLK
+set_location_assignment PIN_240 -to RAM_WE
+set_location_assignment PIN_4 -to RAM_ADDR[8]
+set_location_assignment PIN_5 -to RAM_ADDR[9]
+set_location_assignment PIN_6 -to RAM_ADDR[10]
+set_location_assignment PIN_9 -to RAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_100MHz
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7]
+
+set_global_assignment -name VERILOG_FILE top.v
+set_global_assignment -name VERILOG_FILE sys_pll.v
+set_global_assignment -name VERILOG_FILE control.v
+set_global_assignment -name VERILOG_FILE configuration.v
+set_global_assignment -name VERILOG_FILE usb_fifo.v
+set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id "100 MHz Clock"
+set_instance_assignment -name CLOCK_SETTINGS "100 MHz Clock" -to CLK_100MHz
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: trunk/BandeCosmique/configuration.v
===================================================================
--- trunk/BandeCosmique/configuration.v (revision 200)
+++ trunk/BandeCosmique/configuration.v (revision 200)
@@ -0,0 +1,82 @@
+module configuration
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [5:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire [1023:0] cfg_bits
+ );
+
+ wire [63:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+ reg [15:0] int_miso_reg;
+
+ wire [1023:0] int_bits_wire;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 64; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(int_bits_wire[j*16+15:j*16]),
+ .aclr(),
+ .aload(),
+ .aset(),
+ .sload(),
+ .sset());
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(64),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(6)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(int_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(64),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(6)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cfg_bits = int_bits_wire;
+
+endmodule
Index: trunk/BandeCosmique/control.v
===================================================================
--- trunk/BandeCosmique/control.v (revision 200)
+++ trunk/BandeCosmique/control.v (revision 200)
@@ -0,0 +1,260 @@
+module control
+ (
+ input wire clock, reset,
+
+ input wire rx_empty, tx_full,
+ input wire [7:0] rx_data,
+
+ output wire rx_rdreq, tx_wrreq,
+ output wire [7:0] tx_data,
+
+ output wire bus_wren,
+ output wire [31:0] bus_addr,
+ output wire [15:0] bus_mosi,
+
+ input wire [15:0] bus_miso,
+ input wire bus_busy,
+
+ output wire led
+ );
+
+ reg [23:0] led_counter;
+
+ reg int_bus_wren;
+ reg [31:0] int_bus_addr;
+ reg [31:0] int_bus_cntr;
+ reg [15:0] int_bus_mosi;
+
+ reg int_rdreq, int_wrreq;
+ reg [7:0] int_data;
+ reg int_led;
+
+ reg [1:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ reg [4:0] state;
+
+ reg [31:0] address, counter;
+
+ reg [15:0] prefix;
+
+ wire [15:0] dest, data;
+
+ reg [7:0] buffer [3:0];
+
+ assign dest = {buffer[0], buffer[1]};
+ assign data = {buffer[2], buffer[3]};
+
+ always @(posedge clock)
+ begin
+ if (~rx_empty)
+ begin
+ int_led <= 1'b0;
+ led_counter <= 24'd0;
+ end
+ else
+ begin
+ if (&led_counter)
+ begin
+ int_led <= 1'b1;
+ end
+ else
+ begin
+ led_counter <= led_counter + 24'd1;
+ end
+ end
+
+ case(state)
+ 0:
+ begin
+ int_rdreq <= 1'b1;
+ int_wrreq <= 1'b0;
+ idle_counter <= 5'd0;
+ byte_counter <= 2'd0;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ // read 4 bytes
+ if (~rx_empty)
+ begin
+ idle_counter <= 5'd0;
+ byte_counter <= byte_counter + 2'd1;
+ buffer[byte_counter] <= rx_data;
+ if (&byte_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+ else if(|byte_counter)
+ begin
+ idle_counter <= idle_counter + 5'd1;
+ if (&idle_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+ end
+
+ 2:
+ begin
+ case (dest)
+ 16'h0000:
+ begin
+ // reset
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+
+ 16'h0001:
+ begin
+ // prefix register
+ prefix <= data;
+ state <= 5'd0;
+ end
+
+
+ 16'h0002:
+ begin
+ // address register
+ address <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0003:
+ begin
+ // counter register
+ counter <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0004:
+ begin
+ // single write
+ int_bus_addr <= address;
+ int_bus_mosi <= data;
+ int_bus_wren <= 1'b1;
+ prefix <= 16'd0;
+ state <= 5'd3;
+ end
+
+ 16'h0005:
+ begin
+ // multi read
+ int_bus_addr <= address;
+ int_bus_cntr <= counter;
+ int_bus_wren <= 1'b0;
+ prefix <= 16'd0;
+ state <= 5'd4;
+ end
+
+ default:
+ begin
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ // single write
+ 3:
+ begin
+ if (~bus_busy)
+ begin
+ int_bus_addr <= 32'd0;
+ int_bus_mosi <= 16'd0;
+ int_bus_wren <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+
+ // multi read
+ 4:
+ begin
+ if (bus_busy)
+ begin
+ buffer[0] <= 8'd1;
+ buffer[1] <= 8'd0;
+ int_bus_cntr <= 32'd0;
+ end
+ else
+ begin
+ buffer[0] <= 8'd0;
+ buffer[1] <= 8'd0;
+ end
+ state <= 5'd7;
+ end
+
+ 5:
+ begin
+ buffer[0] <= bus_miso[7:0];
+ buffer[1] <= bus_miso[15:8];
+ int_bus_addr <= int_bus_addr + 32'd1;
+ int_bus_cntr <= int_bus_cntr - 32'd1;
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_data <= buffer[0];
+ int_wrreq <= 1'b1;
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ if (~tx_full)
+ begin
+ int_data <= buffer[1];
+ state <= 5'd9;
+ end
+ end
+
+ 9:
+ begin
+ if (~tx_full)
+ begin
+ int_wrreq <= 1'b0;
+ state <= 5'd10;
+ end
+ end
+
+ 10:
+ begin
+ if (|int_bus_cntr)
+ begin
+ state <= 5'd5;
+ end
+ else
+ begin
+ state <= 5'd0;
+ end
+ end
+
+ default:
+ begin
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ assign bus_wren = int_bus_wren;
+ assign bus_addr = int_bus_addr;
+ assign bus_mosi = int_bus_mosi;
+ assign rx_rdreq = int_rdreq & (~rx_empty);
+ assign tx_wrreq = int_wrreq & (~tx_full);
+ assign tx_data = int_data;
+ assign led = int_led;
+
+endmodule
Index: trunk/BandeCosmique/sys_pll.v
===================================================================
--- trunk/BandeCosmique/sys_pll.v (revision 200)
+++ trunk/BandeCosmique/sys_pll.v (revision 200)
@@ -0,0 +1,163 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: sys_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sys_pll (
+ inclk0,
+ c0,
+ c1,
+ c2);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 10,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 9,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 10,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 6,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 10,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 10000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+endmodule
Index: trunk/BandeCosmique/top.v
===================================================================
--- trunk/BandeCosmique/top.v (revision 200)
+++ trunk/BandeCosmique/top.v (revision 200)
@@ -0,0 +1,431 @@
+module top
+ (
+ input wire CLK_100MHz,
+ output wire LED,
+
+ input wire ADC_DCO,
+ input wire ADC_FCO,
+ input wire [5:0] ADC_D,
+
+ output wire USB_SLRD,
+ output wire USB_SLWR,
+ input wire USB_IFCLK,
+ input wire USB_FLAGA, // EMPTY flag for EP6
+ input wire USB_FLAGB, // FULL flag for EP8
+ output wire USB_PA2,
+ output wire USB_PA4,
+ output wire USB_PA6,
+ inout wire [7:0] USB_PB,
+
+ output wire RAM_CLK,
+ output wire RAM_WE,
+ output wire [21:0] RAM_ADDR,
+ inout wire RAM_DQAP,
+ inout wire [7:0] RAM_DQA,
+ inout wire RAM_DQBP,
+ inout wire [7:0] RAM_DQB
+ );
+
+ localparam N = 6;
+
+ // Turn output ports off
+/*
+ assign RAM_CLK = 1'b0;
+ assign RAM_CE1 = 1'b0;
+ assign RAM_WE = 1'b0;
+ assign RAM_ADDR = 20'h00000;
+*/
+
+ assign RAM_CLK = sys_clock;
+
+ assign USB_PA2 = ~usb_rden;
+ assign USB_PA4 = usb_addr;
+ assign USB_PA6 = ~usb_pktend;
+
+ wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
+ wire usb_tx_wrreq, usb_rx_rdreq;
+ wire usb_tx_full, usb_rx_empty;
+ wire [7:0] usb_tx_data, usb_rx_data;
+ wire usb_addr;
+
+ assign USB_SLRD = ~usb_rdreq;
+ assign USB_SLWR = ~usb_wrreq;
+
+ usb_fifo usb_unit
+ (
+ .usb_clock(USB_IFCLK),
+ .usb_data(USB_PB),
+ .usb_full(~USB_FLAGB),
+ .usb_empty(~USB_FLAGA),
+ .usb_wrreq(usb_wrreq),
+ .usb_rdreq(usb_rdreq),
+ .usb_rden(usb_rden),
+ .usb_pktend(usb_pktend),
+ .usb_addr(usb_addr),
+
+ .clock(sys_clock),
+
+ .tx_full(usb_tx_full),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+
+ .rx_empty(usb_rx_empty),
+ .rx_rdreq(usb_rx_rdreq),
+ .rx_q(usb_rx_data)
+ );
+
+/*
+ reg [31:0] led_counter;
+ always @(posedge CLK_50MHz)
+ begin
+ led_counter = led_counter + 32'd1;
+ end
+ assign LED = led_counter[28];
+*/
+ wire [11:0] osc_mux_data [4:0];
+
+ wire [11:0] trg_mux_data;
+ wire trg_flag;
+
+ wire [6*12-1:0] int_mux_data [N-1:0];
+
+ wire [1:0] amp_flag [3*N-1:0];
+ wire [12:0] amp_data [3*N-1:0];
+
+ wire cls_flag;
+ wire [6:0] cls_data;
+
+ wire [1:0] amp_mux_flag [2:0];
+ wire [11:0] amp_mux_data [2:0];
+
+ wire cnt_good [3:0];
+ wire [15:0] cnt_bits_wire;
+
+ wire sys_clock, sys_frame;
+
+ wire [11:0] adc_data [N-1:0];
+ wire [11:0] sys_data [N-1:0];
+ wire [11:0] tst_data;
+
+ wire [3:0] cmp_data;
+ wire [1:0] del_data;
+
+ wire [19:0] cic_data [N-1:0];
+
+ wire [11:0] dec_data [N-1:0];
+ wire [12:0] clp_data [N-1:0];
+ wire [11:0] tmp_data;
+
+
+ wire i2c_reset;
+
+ assign tmp_data = 12'd0;
+/*
+ assign sys_clock = CLK_100MHz;
+*/
+ sys_pll sys_pll_unit(
+ .inclk0(CLK_100MHz),
+ .c0(sys_clock));
+
+/*
+ sys_pll sys_pll_unit(
+ .inclk0(CLK_100MHz),
+ .c0(sys_clock),
+ .c1(ADC_DCO),
+ .c2(ADC_FCO));
+
+ wire ADC_DCO, ADC_FCO;
+
+
+ test test_unit(
+ .clock(ADC_FCO),
+ .data(tst_data));
+*/
+
+ adc_lvds #(
+ .size(6),
+ .width(12)) adc_lvds_unit (
+ .clock(sys_clock),
+ .lvds_dco(ADC_DCO),
+ .lvds_fco(ADC_FCO),
+ .lvds_d(ADC_D),
+// .test(tst_data),
+ .adc_frame(sys_frame),
+ .adc_data({
+ adc_data[5], adc_data[3], adc_data[4], // D3, D1, D2
+ adc_data[2], adc_data[1], adc_data[0]})); // S2, S1_S, S1_F
+
+ wire [15:0] cfg_bits [63:0];
+ wire [1023:0] int_cfg_bits;
+
+ wire [39:0] cfg_mux_selector;
+
+ wire cfg_reset;
+
+ wire [2:0] bus_ssel;
+ wire bus_wren;
+ wire [31:0] bus_addr;
+ wire [15:0] bus_mosi;
+ wire [15:0] bus_miso [2:0];
+ wire [2:0] bus_busy;
+
+ wire [15:0] mrg_bus_miso;
+ wire mrg_bus_busy;
+
+ wire [3*16-1:0] int_bus_miso;
+
+ genvar j;
+
+ generate
+ for (j = 0; j < 64; j = j + 1)
+ begin : CONFIGURATION_OUTPUT
+ assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
+ end
+ endgenerate
+
+ configuration configuration_unit (
+ .clock(sys_clock),
+ .reset(cfg_reset),
+ .bus_ssel(bus_ssel[0]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[5:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[0]),
+ .bus_busy(bus_busy[0]),
+ .cfg_bits(int_cfg_bits));
+
+ generate
+ for (j = 0; j < 6; j = j + 1)
+ begin : MUX_DATA
+ assign int_mux_data[j] = {
+ {4'd0, cls_flag, 7'd0},
+ {5'd0, cls_data},
+ {4'd0, amp_flag[j][0], 7'd0},
+ amp_data[j][11:0],
+ clp_data[j][11:0],
+ sys_data[j]
+ };
+ end
+ endgenerate
+
+ assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
+
+ lpm_mux #(
+ .lpm_size(6*6),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(6)) trg_mux_unit (
+ .sel(cfg_bits[4][13:8]),
+ .data({
+ int_mux_data[5], int_mux_data[4], int_mux_data[3],
+ int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ .result(trg_mux_data));
+
+ generate
+ for (j = 0; j < 5; j = j + 1)
+ begin : OSC_CHAIN
+
+ lpm_mux #(
+ .lpm_size(6*6),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(6)) osc_mux_unit (
+ .sel(cfg_mux_selector[j*8+5:j*8]),
+ .data({
+ int_mux_data[5], int_mux_data[4], int_mux_data[3],
+ int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ .result(osc_mux_data[j]));
+ end
+ endgenerate
+
+ trigger trigger_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][0]),
+ .cfg_data(cfg_bits[5][11:0]),
+ .trg_data(trg_mux_data),
+ .trg_flag(trg_flag));
+
+ oscilloscope oscilloscope_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][1]),
+ .cfg_data(cfg_bits[5][12]),
+ .trg_flag(trg_flag),
+ .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+ .ram_wren(RAM_WE),
+ .ram_addr(RAM_ADDR),
+ .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
+ .bus_ssel(bus_ssel[1]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[19:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[1]),
+ .bus_busy(bus_busy[1]));
+
+ filter #(.size(6), .width(12)) filter_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .inp_data({sys_data[5], sys_data[4], sys_data[3],
+ sys_data[2], sys_data[1], sys_data[0]}),
+ .out_data({cic_data[5], cic_data[4], cic_data[3],
+ cic_data[2], cic_data[1], cic_data[0]}));
+/*
+ new_filter #(.size(6), .width(12)) filter_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .inp_data({sys_data[5], sys_data[4], sys_data[3],
+ sys_data[2], sys_data[1], sys_data[0]}),
+ .out_data({cic_data[5], cic_data[4], cic_data[3],
+ cic_data[2], cic_data[1], cic_data[0]}));
+*/
+
+ generate
+ for (j = 0; j < 2; j = j + 1)
+ begin : DECONV_CHAIN
+
+ clip #(.shift(21), .width(19), .widthr(13)) clip_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+// .del_data({6'd0, 6'd32, 6'd32, 6'd32}),
+ .del_data({6'd0, cfg_bits[43+6*j][5:0], cfg_bits[41+6*j][5:0], cfg_bits[39+6*j][5:0]}),
+ .amp_data({6'd0, 6'd20, 6'd20, 6'd20}),
+// .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}),
+// exp(-32/1000)*1024*20
+ .tau_data({16'd0, cfg_bits[42+6*j], cfg_bits[40+6*j], cfg_bits[38+6*j]}),
+ .inp_data({
+ 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}),
+ .out_data({
+ tmp_data, clp_data[j*3+2], clp_data[j*3+1], clp_data[j*3+0]}));
+
+ end
+ endgenerate
+
+ generate
+ for (j = 0; j < 6; j = j + 1)
+ begin : MCA_CHAIN
+/*
+ shift #(.shift(11), .width(19), .widthr(13)) shift_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .amp_data(6'd21),
+ .inp_data(cic_data[j][18:0]),
+ .out_data(clp_data[j]));
+*/
+ assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+
+ amplitude #(.width(13)) amplitude_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+// .min_data(13'd20),
+ .min_data(cfg_bits[10+j][12:0]),
+ .max_data(13'd4095),
+ .inp_data(clp_data[j]),
+ .out_flag(amp_flag[j]),
+ .out_data(amp_data[j]));
+ end
+ endgenerate
+
+// {D3, D2, D1, S2, S1_S, S1_F}
+ classifier #(.width(12)) classifier_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+// .cfg_data({12'd20, 12'd20,
+// 12'd20, 12'd20, 12'd20, 12'd20, 12'd2000, 12'd20,
+// 12'd20, 12'd2000, 12'd2000, 12'd20, 12'd1000, 12'd1000}),
+ .cfg_data({cfg_bits[37][11:0], cfg_bits[36][11:0],
+ cfg_bits[35][11:0], cfg_bits[34][11:0], cfg_bits[33][11:0], cfg_bits[32][11:0],
+ cfg_bits[31][11:0], cfg_bits[30][11:0], cfg_bits[29][11:0], cfg_bits[28][11:0],
+ cfg_bits[27][11:0], cfg_bits[26][11:0], cfg_bits[25][11:0], cfg_bits[24][11:0],
+ cfg_bits[23][11:0], cfg_bits[22][11:0], cfg_bits[21][11:0], cfg_bits[20][11:0],
+ cfg_bits[19][11:0], cfg_bits[18][11:0], cfg_bits[17][11:0], cfg_bits[16][11:0]}),
+ .inp_data({amp_data[5][11:0], amp_data[4][11:0], amp_data[3][11:0],
+ amp_data[2][11:0], amp_data[1][11:0], amp_data[0][11:0]}),
+ .inp_flag({amp_flag[5][0], amp_flag[4][0], amp_flag[3][0],
+ amp_flag[2][0], amp_flag[1][0], amp_flag[0][0]}),
+ .out_flag(cls_flag),
+ .out_data(cls_data));
+
+ histogram32 histogram32_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][5]),
+ .hst_good(cls_flag & cfg_bits[6][0]),
+ .hst_data(cls_data),
+ .bus_ssel(bus_ssel[2]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[7:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[2]),
+ .bus_busy(bus_busy[2]));
+
+
+ generate
+ for (j = 0; j < 3; j = j + 1)
+ begin : BUS_OUTPUT
+ assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(3),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(2)) bus_miso_mux_unit (
+ .sel(bus_addr[29:28]),
+ .data(int_bus_miso),
+ .result(mrg_bus_miso));
+
+ lpm_mux #(
+ .lpm_size(3),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(1),
+ .lpm_widths(2)) bus_busy_mux_unit (
+ .sel(bus_addr[29:28]),
+ .data(bus_busy),
+ .result(mrg_bus_busy));
+
+ lpm_decode #(
+ .lpm_decodes(3),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(2)) lpm_decode_unit (
+ .data(bus_addr[29:28]),
+ .eq(bus_ssel));
+
+
+ control control_unit (
+ .clock(sys_clock),
+ .rx_empty(usb_rx_empty),
+ .tx_full(usb_tx_full),
+ .rx_data(usb_rx_data),
+ .rx_rdreq(usb_rx_rdreq),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr),
+ .bus_mosi(bus_mosi),
+ .bus_miso(mrg_bus_miso),
+ .bus_busy(mrg_bus_busy),
+ .led(LED));
+
+/*
+ altserial_flash_loader #(
+ .enable_shared_access("OFF"),
+ .enhanced_mode(1),
+ .intended_device_family("Cyclone III")) sfl_unit (
+ .noe(1'b0),
+ .asmi_access_granted(),
+ .asmi_access_request(),
+ .data0out(),
+ .dclkin(),
+ .scein(),
+ .sdoin());
+*/
+
+endmodule
Index: trunk/BandeCosmique/usb_fifo.v
===================================================================
--- trunk/BandeCosmique/usb_fifo.v (revision 200)
+++ trunk/BandeCosmique/usb_fifo.v (revision 200)
@@ -0,0 +1,121 @@
+module usb_fifo
+ (
+ input wire usb_clock,
+ inout wire [7:0] usb_data,
+ input wire usb_full, usb_empty,
+ output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
+ output wire usb_addr,
+
+ input wire clock,
+ input wire tx_wrreq, rx_rdreq,
+ input wire [7:0] tx_data,
+ output wire tx_full, rx_empty,
+ output wire [7:0] rx_q
+ );
+
+ wire int_rx_full, int_tx_empty;
+ wire rx_ready, tx_ready;
+ wire int_rdreq, int_wrreq, int_pktend;
+ reg is_rx_addr_ok;
+ reg [8:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ wire [7:0] int_rx_data = usb_data;
+ wire [7:0] int_tx_q;
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF"),
+ .write_aclr_synch("OFF")) fifo_tx (
+ .aclr(1'b0),
+ .data(tx_data),
+ .rdclk(usb_clock),
+ .rdreq(int_wrreq),
+ .wrclk(clock),
+ .wrreq(tx_wrreq),
+ .q(int_tx_q),
+ .rdempty(int_tx_empty),
+ .wrfull(tx_full),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF"),
+ .write_aclr_synch("OFF")) fifo_rx (
+ .aclr(1'b0),
+ .data(int_rx_data),
+ .rdclk(clock),
+ .rdreq(rx_rdreq),
+ .wrclk(usb_clock),
+ .wrreq(int_rdreq),
+ .q(rx_q),
+ .rdempty(rx_empty),
+ .wrfull(int_rx_full),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ assign rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);
+ assign tx_ready = (~rx_ready) & (~usb_full) & (~int_tx_empty) & (~int_pktend);
+
+ assign int_rdreq = (rx_ready) & (is_rx_addr_ok);
+ assign int_wrreq = (tx_ready) & (~is_rx_addr_ok);
+
+ assign int_pktend = (&idle_counter);
+
+ always @ (posedge usb_clock)
+ begin
+ // respect 1 clock delay between fifo selection
+ // and data transfer operations
+ is_rx_addr_ok <= rx_ready;
+
+ // assert pktend if buffer contains unsent data
+ // and fifo_tx_unit stays empty for more than 30 clocks
+ if (int_pktend)
+ begin
+ byte_counter <= 9'd0;
+ idle_counter <= 5'd0;
+ end
+ else if (int_wrreq)
+ begin
+ byte_counter <= byte_counter + 9'd1;
+ idle_counter <= 5'd0;
+ end
+ else if ((|byte_counter) & (int_tx_empty) & (~rx_ready))
+ begin
+ byte_counter <= byte_counter;
+ idle_counter <= idle_counter + 5'd1;
+ end
+
+ end
+
+ assign usb_pktend = int_pktend;
+ assign usb_rdreq = int_rdreq;
+ assign usb_wrreq = int_wrreq;
+ assign usb_rden = int_rdreq;
+ assign usb_addr = rx_ready;
+ assign usb_data = int_wrreq ? int_tx_q : 8'bz;
+
+endmodule