- Location:
- /trunk
- Files:
-
- 1 deleted
- 7 edited
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- Unmodified
- Added
- Removed
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/trunk/FirmwareFX2/dscr.a51
r30 r20 315 315 .db <str1, >str1 316 316 .db <str2, >str2 317 .db <str3, >str3318 317 _string_descriptors_end: 319 318 -
/trunk/FirmwareFX2/fx2/usb_common.c
r30 r20 52 52 current_config_descr = high_speed_config_descr; 53 53 other_config_descr = full_speed_config_descr; 54 55 54 EP8AUTOINLENH = 0x02; SYNCDELAY; // Size in bytes of the IN data automatically commited (512 bytes here) 55 EP8AUTOINLENL = 0x00; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet 56 56 } 57 57 else { … … 60 60 current_config_descr = full_speed_config_descr; 61 61 other_config_descr = high_speed_config_descr; 62 63 62 EP8AUTOINLENH = 0x00; SYNCDELAY; // Size in bytes of the IN data automatically commited (64 bytes here) 63 EP8AUTOINLENL = 0x40; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet 64 64 } 65 65 … … 289 289 290 290 case RQ_SET_CONFIG: 291 IOE &= ~(1 << 6); 291 292 _usb_config = wValueL; // FIXME app should handle 292 293 break; -
/trunk/FirmwareFX2/hw_basic.c
r30 r20 88 88 CPUCS = bmCLKOE | bmCLKSPD1; 89 89 90 // put the system in FIFO mode by default 91 // internal clock source at 48Mhz, drive output pin, synchronous mode 92 // NOTE: Altera USB-Blaster does not work in another mode 90 // Use internal 48 MHz, enable output, use "Port" mode for all pins 93 91 IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFCFG1 | bmIFCFG0; 94 92 -
/trunk/FirmwareFX2/usbjtag.c
r30 r20 94 94 95 95 // Make Timer2 reload at 100 Hz to trigger Keepalive packets 96 97 96 tmp = 65536 - ( 48000000 / 12 / 100 ); 98 97 RCAP2H = tmp >> 8; … … 102 101 103 102 // Enable Autopointer 104 105 EXTACC = 1; // Enable 106 APTR1FZ = 1; // Don't freeze 107 APTR2FZ = 1; // Don't freeze 103 EXTACC = 1; // Enable 104 APTR1FZ = 1; // Don't freeze 105 APTR2FZ = 1; // Don't freeze 108 106 109 107 // define endpoint configuration … … 130 128 EP6CFG = 0xA2; SYNCDELAY; // Out endpoint, Bulk, Double buffering 131 129 EP6FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming 132 EP6FIFOCFG = bmAUTOOUT ; SYNCDELAY; // Endpoint 6 used for user communicationn, auto commitment, 8bits data bus130 EP6FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; // Endpoint 6 used for user communicationn, auto commitment, 16 bits data bus 133 131 134 132 EP8CFG = 0xE0; SYNCDELAY; // In endpoint, Bulk 135 133 EP8FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming 136 EP8FIFOCFG = bmAUTOIN ; SYNCDELAY; // Endpoint 8 used for user communication, auto commitment, 8bits data bus134 EP8FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY; // Endpoint 8 used for user communication, auto commitment, 16 bits data bus 137 135 138 136 EP8AUTOINLENH = 0x00; SYNCDELAY; // Size in bytes of the IN data automatically commited (64 bytes here, but changed dynamically depending on the connection) … … 145 143 EP2BCL = 0x80; SYNCDELAY; // Arm EP4OUT by writing byte count w/skip.= 146 144 EP4BCL = 0x80; SYNCDELAY; 147 148 PINFLAGSAB = 0xFA; SYNCDELAY; // 1111_1010 => FLAGA = EMPTY flag for EP6; FLAGB = FULL flag for EP8 149 145 146 // JTAG from FX2 enabled by default 147 IOC |= (1 << 7); 148 150 149 // Put the system in high speed by default (REM: USB-Blaster is in full speed) 151 150 // This can be changed by vendor commands … … 399 398 } 400 399 400 // change JTAG enable 401 if (bRequest == 0x92) 402 { 403 if (wIndexL == 0) // FX2 is master of JTAG 404 { 405 IOC |= (1 << 7); 406 } 407 else // external connector is master of JTAG 408 { 409 IOC &= ~(1 << 7); 410 } 411 } 401 412 // change synchronous/asynchronous mode 402 if (bRequest == 0x9 2)413 if (bRequest == 0x93) 403 414 { 404 415 if(IFCONFIG & bmASYNC) … … 411 422 } 412 423 } 413 414 if (bRequest == 0x9 3) // change to synchronous mode424 425 if (bRequest == 0x94) // change to synchronous mode 415 426 { 416 427 IFCONFIG &= ~bmASYNC; … … 434 445 EP0BCH = 0; 435 446 EP0BCL = wLengthL; 447 // EP0CS |= bmHSNAK; // Bram 436 448 return 1; 437 449 } … … 448 460 } 449 461 462 if (bRequest == 0x95) // For debugging purposes 463 { 464 465 SPI &= ~bmSS; // enable slave select 466 467 spi_write_byte_msb(wValueL); // address 468 spi_write_byte_msb(wIndexL); // header 469 EP0BUF[0] = spi_read_byte_msb(); // read back value from slave 470 471 SPI |= bmSS; /* active low, disable slave */ 472 473 EP0BCH = 0; 474 EP0BCL = 1; // Arm the EP 475 return 1; 476 477 /*static xdata unsigned char buf[2]; 478 buf[0] = 0xFF; 479 buf[1] = 0x10; 480 spi_read(0x00, wValueL, SPI_FMT_HDR_1, wValueH, buf, 0); 481 //spi_write_byte_msb(wValueL); 482 EP0BUF[0] = 0x51; 483 EP0BUF[1] = wValueL; 484 EP0BCH = 0; 485 EP0BCL = wLengthL; 486 return 1;*/ 487 } 488 450 489 if(bRequest == 0x90) 451 490 { … … 463 502 EP0BCH = 0; 464 503 EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer 504 //EP0CS |= bmHSNAK; // Bram 465 505 466 506 return 1; … … 486 526 usb_jtag_init(); 487 527 eeprom_init(); 488 setup_autovectors ();489 usb_install_handlers ();528 setup_autovectors (); 529 usb_install_handlers (); 490 530 491 531 -
/trunk/FirmwareFX2/usbjtag.hex
r30 r20 150 150 :10E18400810240000007050202400000090401006A 151 151 :10E1940002FFFFFF02070506024000000705880290 152 :10E1A4004000000 3AEE1B4E1C2E10603000009044B153 :10E1B4000 E0341006C0074006500720061001803D6154 :10E1C4005 500530042002D0042006C0061007300B2155 :10E1D400 740065007200120330003000300030001B156 :0 8E1E400300030003000300073152 :10E1A40040000004B0E1B6E1C0E1D8E1060300009C 153 :10E1B40009040A03460059004E005500180355008F 154 :10E1C400530042002D0042006C0061007300740093 155 :10E1D400650072001203300030003000300030005F 156 :06E1E400300030003000A5 157 157 :10085A00AA82E50D54FEFBB50D0280298A048C0597 158 158 :10086A00E4620EED620FEB2400F582E43418F5839E … … 168 168 :10090A00825017EA2402F582E434E1F583E0F582A5 169 169 :10091A00C00212085AD0020A80E17486250DFAF53F 170 :10092A0082C00212085A90E1B 4E0F58212085AD045171 :10093A000290E1B 4E02AFAF582C00212085A90E164172 :10094A00C 2E0F58212085AD00290E1C2E02AF5828A173 :10095A0012085A90E1D AE0F58212085A7A0090E118174 :10096A00B 4E0FBC3EA64808BF063F08095F0501723175 :10097A00EA24B 4F582E434E1F583E0F582C0021298176 :10098A00085AD0020A80D77A0090E1C 2E0FBC3EA93177 :10099A0064808BF063F08095F05017EA24C 2F582E8170 :10092A0082C00212085A90E1B6E0F58212085AD043 171 :10093A000290E1B6E02AFAF582C00212085A90E162 172 :10094A00C0E0F58212085AD00290E1C0E02AF5828E 173 :10095A0012085A90E1D8E0F58212085A7A0090E11A 174 :10096A00B6E0FBC3EA64808BF063F08095F0501721 175 :10097A00EA24B6F582E434E1F583E0F582C0021296 176 :10098A00085AD0020A80D77A0090E1C0E0FBC3EA95 177 :10099A0064808BF063F08095F05017EA24C0F582EA 178 178 :1009AA00E434E1F583E0F582C00212085AD0020A63 179 :1009BA0080D77A0090E1D AE0FBC3EA64808BF063C7180 :1009CA00F08095F05017EA24D AF582E434E1F583F1179 :1009BA0080D77A0090E1D8E0FBC3EA64808BF063C9 180 :1009CA00F08095F05017EA24D8F582E434E1F583F3 181 181 :1009DA00E0F582C00212085AD0020A80D77A00C310 182 182 :1009EA00EA648094845017EA240EF582E434E1F52F -
/trunk/PaellaBase/Paella.qsf
r30 r20 138 138 set_location_assignment PIN_146 -to CON_B[14] 139 139 set_location_assignment PIN_147 -to CON_B[15] 140 set_location_assignment PIN_148 -to CON_B[16] 140 141 set_location_assignment PIN_149 -to CON_BCLK[0] 141 142 set_location_assignment PIN_150 -to CON_BCLK[1] … … 247 248 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[14] 248 249 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[15] 250 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[16] 249 251 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[0] 250 252 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[1] -
/trunk/PaellaBase/Paella.v
r30 r20 6 6 inout wire [3:0] TRG, 7 7 inout wire [6:0] CON_A, 8 inout wire [1 5:0] CON_B,8 inout wire [16:0] CON_B, 9 9 inout wire [12:0] CON_C, 10 10 input wire [1:0] CON_BCLK, … … 35 35 inout wire [7:0] RAM_DQB 36 36 ); 37 37 38 38 // Turn off all output ports 39 39 assign USB_SLRD = 1'b0;
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