Index: trunk/3DEES/3DEES.cof =================================================================== --- trunk/3DEES/3DEES.cof (revision 191) +++ trunk/3DEES/3DEES.cof (revision 191) @@ -0,0 +1,18 @@ + + + EPCS16 + EP3C25 + 3DEES.jic + 1 + 1 + 7 + + 1 + + 3DEES.sof + + + 4 + + + Index: trunk/3DEES/3DEES.dpf =================================================================== --- trunk/3DEES/3DEES.dpf (revision 191) +++ trunk/3DEES/3DEES.dpf (revision 191) @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/3DEES/3DEES.qpf =================================================================== --- trunk/3DEES/3DEES.qpf (revision 191) +++ trunk/3DEES/3DEES.qpf (revision 191) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Web Edition +# Date created = 14:14:14 August 28, 2009 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "14:14:14 August 28, 2009" + +# Revisions + +PROJECT_REVISION = "3DEES" Index: trunk/3DEES/3DEES.qsf =================================================================== --- trunk/3DEES/3DEES.qsf (revision 191) +++ trunk/3DEES/3DEES.qsf (revision 191) @@ -0,0 +1,251 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 132 02/25/2009 SJ Web Edition +# Date created = 14:14:14 August 28, 2009 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# 3DEES_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY 3DEES +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name MISC_FILE 3DEES.dpf +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF +set_global_assignment -name ENABLE_CLOCK_LATENCY ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name FMAX_REQUIREMENT "240 MHz" -section_id "LVDS Data Clock" +set_instance_assignment -name CLOCK_SETTINGS "LVDS Data Clock" -to ADC_DCO +set_global_assignment -name FMAX_REQUIREMENT "20 MHz" -section_id "LVDS Frame Clock" +set_instance_assignment -name CLOCK_SETTINGS "LVDS Frame Clock" -to ADC_FCO +set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id "USB Clock" +set_instance_assignment -name CLOCK_SETTINGS "USB Clock" -to USB_IFCLK +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4 +set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5 +set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 6 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8 +set_location_assignment PIN_21 -to LED +set_location_assignment PIN_33 -to USB_IFCLK +set_location_assignment PIN_37 -to USB_PA6 +set_location_assignment PIN_38 -to USB_PA4 +set_location_assignment PIN_39 -to USB_PA2 +set_location_assignment PIN_41 -to USB_FLAGB +set_location_assignment PIN_43 -to USB_FLAGA +set_location_assignment PIN_44 -to USB_PB[4] +set_location_assignment PIN_45 -to USB_PB[5] +set_location_assignment PIN_46 -to USB_PB[6] +set_location_assignment PIN_49 -to USB_PB[7] +set_location_assignment PIN_50 -to USB_SLRD +set_location_assignment PIN_51 -to USB_SLWR +set_location_assignment PIN_52 -to USB_PB[0] +set_location_assignment PIN_55 -to USB_PB[1] +set_location_assignment PIN_56 -to USB_PB[2] +set_location_assignment PIN_57 -to USB_PB[3] +set_location_assignment PIN_137 -to "ADC_D[0](n)" +set_location_assignment PIN_139 -to ADC_D[0] +set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0] +set_location_assignment PIN_142 -to "ADC_D[1](n)" +set_location_assignment PIN_143 -to ADC_D[1] +set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1] +set_location_assignment PIN_144 -to "ADC_D[2](n)" +set_location_assignment PIN_145 -to ADC_D[2] +set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2] +set_location_assignment PIN_147 -to "ADC_D[3](n)" +set_location_assignment PIN_148 -to ADC_D[3] +set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[3] +set_location_assignment PIN_149 -to "ADC_DCO(n)" +set_location_assignment PIN_150 -to ADC_DCO +set_instance_assignment -name IO_STANDARD LVDS -to ADC_DCO +set_location_assignment PIN_151 -to "ADC_FCO(n)" +set_location_assignment PIN_152 -to ADC_FCO +set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO +set_location_assignment PIN_159 -to "ADC_D[4](n)" +set_location_assignment PIN_160 -to ADC_D[4] +set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[4] +set_location_assignment PIN_162 -to "ADC_D[5](n)" +set_location_assignment PIN_164 -to ADC_D[5] +set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[5] +set_location_assignment PIN_181 -to RAM_ADDR[12] +set_location_assignment PIN_182 -to RAM_DQAP +set_location_assignment PIN_183 -to RAM_DQA[0] +set_location_assignment PIN_184 -to RAM_DQA[1] +set_location_assignment PIN_185 -to RAM_DQA[2] +set_location_assignment PIN_186 -to RAM_DQA[3] +set_location_assignment PIN_187 -to RAM_DQA[4] +set_location_assignment PIN_188 -to RAM_DQA[5] +set_location_assignment PIN_189 -to RAM_DQA[6] +set_location_assignment PIN_194 -to RAM_DQA[7] +set_location_assignment PIN_195 -to RAM_ADDR[13] +set_location_assignment PIN_196 -to RAM_ADDR[14] +set_location_assignment PIN_197 -to RAM_ADDR[15] +set_location_assignment PIN_200 -to RAM_ADDR[16] +set_location_assignment PIN_201 -to RAM_ADDR[17] +set_location_assignment PIN_202 -to RAM_ADDR[18] +set_location_assignment PIN_203 -to RAM_ADDR[19] +set_location_assignment PIN_207 -to RAM_ADDR[20] +set_location_assignment PIN_210 -to CLK_100MHz +set_location_assignment PIN_214 -to RAM_ADDR[21] +set_location_assignment PIN_216 -to RAM_ADDR[0] +set_location_assignment PIN_217 -to RAM_ADDR[1] +set_location_assignment PIN_218 -to RAM_ADDR[2] +set_location_assignment PIN_219 -to RAM_ADDR[3] +set_location_assignment PIN_221 -to RAM_ADDR[4] +set_location_assignment PIN_223 -to RAM_ADDR[5] +set_location_assignment PIN_224 -to RAM_DQBP +set_location_assignment PIN_226 -to RAM_DQB[0] +set_location_assignment PIN_230 -to RAM_DQB[1] +set_location_assignment PIN_231 -to RAM_DQB[2] +set_location_assignment PIN_232 -to RAM_DQB[3] +set_location_assignment PIN_233 -to RAM_DQB[4] +set_location_assignment PIN_234 -to RAM_DQB[5] +set_location_assignment PIN_235 -to RAM_DQB[6] +set_location_assignment PIN_236 -to RAM_DQB[7] +set_location_assignment PIN_237 -to RAM_ADDR[6] +set_location_assignment PIN_238 -to RAM_ADDR[7] +set_location_assignment PIN_239 -to RAM_CLK +set_location_assignment PIN_240 -to RAM_WE +set_location_assignment PIN_4 -to RAM_ADDR[8] +set_location_assignment PIN_5 -to RAM_ADDR[9] +set_location_assignment PIN_6 -to RAM_ADDR[10] +set_location_assignment PIN_9 -to RAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_100MHz +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA6 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA4 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7] + +set_global_assignment -name VERILOG_FILE 3DEES.v +set_global_assignment -name VERILOG_FILE adc_lvds.v +set_global_assignment -name VERILOG_FILE sys_pll.v +set_global_assignment -name VERILOG_FILE control.v +set_global_assignment -name VERILOG_FILE analyser.v +set_global_assignment -name VERILOG_FILE classifier.v +set_global_assignment -name VERILOG_FILE amplitude.v +set_global_assignment -name VERILOG_FILE deconv.v +set_global_assignment -name VERILOG_FILE shift.v +set_global_assignment -name VERILOG_FILE delay.v +set_global_assignment -name VERILOG_FILE coincidence.v +set_global_assignment -name VERILOG_FILE counter.v +set_global_assignment -name VERILOG_FILE histogram32.v +set_global_assignment -name VERILOG_FILE trigger.v +set_global_assignment -name VERILOG_FILE oscilloscope.v +set_global_assignment -name VERILOG_FILE configuration.v +set_global_assignment -name VERILOG_FILE usb_fifo.v +set_global_assignment -name VERILOG_FILE test.v +set_global_assignment -name MIF_FILE test.mif +set_global_assignment -name VERILOG_FILE average.v +set_global_assignment -name VERILOG_FILE filter.v +set_global_assignment -name VERILOG_FILE new_filter.v +set_global_assignment -name VERILOG_FILE clip.v +set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id "100 MHz Clock" +set_instance_assignment -name CLOCK_SETTINGS "100 MHz Clock" -to CLK_100MHz +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Index: trunk/3DEES/3DEES.v =================================================================== --- trunk/3DEES/3DEES.v (revision 191) +++ trunk/3DEES/3DEES.v (revision 191) @@ -0,0 +1,431 @@ +module 3DEES + ( + input wire CLK_100MHz, + output wire LED, + + input wire ADC_DCO, + input wire ADC_FCO, + input wire [5:0] ADC_D, + + output wire USB_SLRD, + output wire USB_SLWR, + input wire USB_IFCLK, + input wire USB_FLAGA, // EMPTY flag for EP6 + input wire USB_FLAGB, // FULL flag for EP8 + output wire USB_PA2, + output wire USB_PA4, + output wire USB_PA6, + inout wire [7:0] USB_PB, + + output wire RAM_CLK, + output wire RAM_WE, + output wire [21:0] RAM_ADDR, + inout wire RAM_DQAP, + inout wire [7:0] RAM_DQA, + inout wire RAM_DQBP, + inout wire [7:0] RAM_DQB + ); + + localparam N = 6; + + // Turn output ports off +/* + assign RAM_CLK = 1'b0; + assign RAM_CE1 = 1'b0; + assign RAM_WE = 1'b0; + assign RAM_ADDR = 20'h00000; +*/ + + assign RAM_CLK = sys_clock; + + assign USB_PA2 = ~usb_rden; + assign USB_PA4 = usb_addr; + assign USB_PA6 = ~usb_pktend; + + wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend; + wire usb_tx_wrreq, usb_rx_rdreq; + wire usb_tx_full, usb_rx_empty; + wire [7:0] usb_tx_data, usb_rx_data; + wire usb_addr; + + assign USB_SLRD = ~usb_rdreq; + assign USB_SLWR = ~usb_wrreq; + + usb_fifo usb_unit + ( + .usb_clock(USB_IFCLK), + .usb_data(USB_PB), + .usb_full(~USB_FLAGB), + .usb_empty(~USB_FLAGA), + .usb_wrreq(usb_wrreq), + .usb_rdreq(usb_rdreq), + .usb_rden(usb_rden), + .usb_pktend(usb_pktend), + .usb_addr(usb_addr), + + .clock(sys_clock), + + .tx_full(usb_tx_full), + .tx_wrreq(usb_tx_wrreq), + .tx_data(usb_tx_data), + + .rx_empty(usb_rx_empty), + .rx_rdreq(usb_rx_rdreq), + .rx_q(usb_rx_data) + ); + +/* + reg [31:0] led_counter; + always @(posedge CLK_50MHz) + begin + led_counter = led_counter + 32'd1; + end + assign LED = led_counter[28]; +*/ + wire [11:0] osc_mux_data [4:0]; + + wire [11:0] trg_mux_data; + wire trg_flag; + + wire [6*12-1:0] int_mux_data [N-1:0]; + + wire [1:0] amp_flag [3*N-1:0]; + wire [12:0] amp_data [3*N-1:0]; + + wire cls_flag; + wire [6:0] cls_data; + + wire [1:0] amp_mux_flag [2:0]; + wire [11:0] amp_mux_data [2:0]; + + wire cnt_good [3:0]; + wire [15:0] cnt_bits_wire; + + wire sys_clock, sys_frame; + + wire [11:0] adc_data [N-1:0]; + wire [11:0] sys_data [N-1:0]; + wire [11:0] tst_data; + + wire [3:0] cmp_data; + wire [1:0] del_data; + + wire [19:0] cic_data [N-1:0]; + + wire [11:0] dec_data [N-1:0]; + wire [12:0] clp_data [N-1:0]; + wire [11:0] tmp_data; + + + wire i2c_reset; + + assign tmp_data = 12'd0; +/* + assign sys_clock = CLK_100MHz; +*/ + sys_pll sys_pll_unit( + .inclk0(CLK_100MHz), + .c0(sys_clock)); + +/* + sys_pll sys_pll_unit( + .inclk0(CLK_100MHz), + .c0(sys_clock), + .c1(ADC_DCO), + .c2(ADC_FCO)); + + wire ADC_DCO, ADC_FCO; + + + test test_unit( + .clock(ADC_FCO), + .data(tst_data)); +*/ + + adc_lvds #( + .size(6), + .width(12)) adc_lvds_unit ( + .clock(sys_clock), + .lvds_dco(ADC_DCO), + .lvds_fco(ADC_FCO), + .lvds_d(ADC_D), +// .test(tst_data), + .adc_frame(sys_frame), + .adc_data({ + adc_data[5], adc_data[3], adc_data[4], // D3, D1, D2 + adc_data[2], adc_data[1], adc_data[0]})); // S2, S1_S, S1_F + + wire [15:0] cfg_bits [63:0]; + wire [1023:0] int_cfg_bits; + + wire [39:0] cfg_mux_selector; + + wire cfg_reset; + + wire [2:0] bus_ssel; + wire bus_wren; + wire [31:0] bus_addr; + wire [15:0] bus_mosi; + wire [15:0] bus_miso [2:0]; + wire [2:0] bus_busy; + + wire [15:0] mrg_bus_miso; + wire mrg_bus_busy; + + wire [3*16-1:0] int_bus_miso; + + genvar j; + + generate + for (j = 0; j < 64; j = j + 1) + begin : CONFIGURATION_OUTPUT + assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16]; + end + endgenerate + + configuration configuration_unit ( + .clock(sys_clock), + .reset(cfg_reset), + .bus_ssel(bus_ssel[0]), + .bus_wren(bus_wren), + .bus_addr(bus_addr[5:0]), + .bus_mosi(bus_mosi), + .bus_miso(bus_miso[0]), + .bus_busy(bus_busy[0]), + .cfg_bits(int_cfg_bits)); + + generate + for (j = 0; j < 6; j = j + 1) + begin : MUX_DATA + assign int_mux_data[j] = { + {4'd0, cls_flag, 7'd0}, + {5'd0, cls_data}, + {4'd0, amp_flag[j][0], 7'd0}, + amp_data[j][11:0], + clp_data[j][11:0], + sys_data[j] + }; + end + endgenerate + + assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]}; + + lpm_mux #( + .lpm_size(6*6), + .lpm_type("LPM_MUX"), + .lpm_width(12), + .lpm_widths(6)) trg_mux_unit ( + .sel(cfg_bits[4][13:8]), + .data({ + int_mux_data[5], int_mux_data[4], int_mux_data[3], + int_mux_data[2], int_mux_data[1], int_mux_data[0]}), + .result(trg_mux_data)); + + generate + for (j = 0; j < 5; j = j + 1) + begin : OSC_CHAIN + + lpm_mux #( + .lpm_size(6*6), + .lpm_type("LPM_MUX"), + .lpm_width(12), + .lpm_widths(6)) osc_mux_unit ( + .sel(cfg_mux_selector[j*8+5:j*8]), + .data({ + int_mux_data[5], int_mux_data[4], int_mux_data[3], + int_mux_data[2], int_mux_data[1], int_mux_data[0]}), + .result(osc_mux_data[j])); + end + endgenerate + + trigger trigger_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(cfg_bits[0][0]), + .cfg_data(cfg_bits[5][11:0]), + .trg_data(trg_mux_data), + .trg_flag(trg_flag)); + + oscilloscope oscilloscope_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(cfg_bits[0][1]), + .cfg_data(cfg_bits[5][12]), + .trg_flag(trg_flag), + .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), + .ram_wren(RAM_WE), + .ram_addr(RAM_ADDR), + .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), + .bus_ssel(bus_ssel[1]), + .bus_wren(bus_wren), + .bus_addr(bus_addr[19:0]), + .bus_mosi(bus_mosi), + .bus_miso(bus_miso[1]), + .bus_busy(bus_busy[1])); + + filter #(.size(6), .width(12)) filter_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), + .inp_data({sys_data[5], sys_data[4], sys_data[3], + sys_data[2], sys_data[1], sys_data[0]}), + .out_data({cic_data[5], cic_data[4], cic_data[3], + cic_data[2], cic_data[1], cic_data[0]})); +/* + new_filter #(.size(6), .width(12)) filter_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), + .inp_data({sys_data[5], sys_data[4], sys_data[3], + sys_data[2], sys_data[1], sys_data[0]}), + .out_data({cic_data[5], cic_data[4], cic_data[3], + cic_data[2], cic_data[1], cic_data[0]})); +*/ + + generate + for (j = 0; j < 2; j = j + 1) + begin : DECONV_CHAIN + + clip #(.shift(21), .width(19), .widthr(13)) clip_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), +// .del_data({6'd0, 6'd32, 6'd32, 6'd32}), + .del_data({6'd0, cfg_bits[43+6*j][5:0], cfg_bits[41+6*j][5:0], cfg_bits[39+6*j][5:0]}), + .amp_data({6'd0, 6'd20, 6'd20, 6'd20}), +// .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}), +// exp(-32/1000)*1024*20 + .tau_data({16'd0, cfg_bits[42+6*j], cfg_bits[40+6*j], cfg_bits[38+6*j]}), + .inp_data({ + 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}), + .out_data({ + tmp_data, clp_data[j*3+2], clp_data[j*3+1], clp_data[j*3+0]})); + + end + endgenerate + + generate + for (j = 0; j < 6; j = j + 1) + begin : MCA_CHAIN +/* + shift #(.shift(11), .width(19), .widthr(13)) shift_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), + .amp_data(6'd21), + .inp_data(cic_data[j][18:0]), + .out_data(clp_data[j])); +*/ + assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); + + amplitude #(.width(13)) amplitude_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), +// .min_data(13'd20), + .min_data(cfg_bits[10+j][12:0]), + .max_data(13'd4095), + .inp_data(clp_data[j]), + .out_flag(amp_flag[j]), + .out_data(amp_data[j])); + end + endgenerate + +// {D3, D2, D1, S2, S1_S, S1_F} + classifier #(.width(12)) classifier_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), +// .cfg_data({12'd20, 12'd20, +// 12'd20, 12'd20, 12'd20, 12'd20, 12'd2000, 12'd20, +// 12'd20, 12'd2000, 12'd2000, 12'd20, 12'd1000, 12'd1000}), + .cfg_data({cfg_bits[37][11:0], cfg_bits[36][11:0], + cfg_bits[35][11:0], cfg_bits[34][11:0], cfg_bits[33][11:0], cfg_bits[32][11:0], + cfg_bits[31][11:0], cfg_bits[30][11:0], cfg_bits[29][11:0], cfg_bits[28][11:0], + cfg_bits[27][11:0], cfg_bits[26][11:0], cfg_bits[25][11:0], cfg_bits[24][11:0], + cfg_bits[23][11:0], cfg_bits[22][11:0], cfg_bits[21][11:0], cfg_bits[20][11:0], + cfg_bits[19][11:0], cfg_bits[18][11:0], cfg_bits[17][11:0], cfg_bits[16][11:0]}), + .inp_data({amp_data[5][11:0], amp_data[4][11:0], amp_data[3][11:0], + amp_data[2][11:0], amp_data[1][11:0], amp_data[0][11:0]}), + .inp_flag({amp_flag[5][0], amp_flag[4][0], amp_flag[3][0], + amp_flag[2][0], amp_flag[1][0], amp_flag[0][0]}), + .out_flag(cls_flag), + .out_data(cls_data)); + + histogram32 histogram32_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(cfg_bits[0][5]), + .hst_good(cls_flag & cfg_bits[6][0]), + .hst_data(cls_data), + .bus_ssel(bus_ssel[2]), + .bus_wren(bus_wren), + .bus_addr(bus_addr[7:0]), + .bus_mosi(bus_mosi), + .bus_miso(bus_miso[2]), + .bus_busy(bus_busy[2])); + + + generate + for (j = 0; j < 3; j = j + 1) + begin : BUS_OUTPUT + assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; + end + endgenerate + + lpm_mux #( + .lpm_size(3), + .lpm_type("LPM_MUX"), + .lpm_width(16), + .lpm_widths(2)) bus_miso_mux_unit ( + .sel(bus_addr[29:28]), + .data(int_bus_miso), + .result(mrg_bus_miso)); + + lpm_mux #( + .lpm_size(3), + .lpm_type("LPM_MUX"), + .lpm_width(1), + .lpm_widths(2)) bus_busy_mux_unit ( + .sel(bus_addr[29:28]), + .data(bus_busy), + .result(mrg_bus_busy)); + + lpm_decode #( + .lpm_decodes(3), + .lpm_type("LPM_DECODE"), + .lpm_width(2)) lpm_decode_unit ( + .data(bus_addr[29:28]), + .eq(bus_ssel)); + + + control control_unit ( + .clock(sys_clock), + .rx_empty(usb_rx_empty), + .tx_full(usb_tx_full), + .rx_data(usb_rx_data), + .rx_rdreq(usb_rx_rdreq), + .tx_wrreq(usb_tx_wrreq), + .tx_data(usb_tx_data), + .bus_wren(bus_wren), + .bus_addr(bus_addr), + .bus_mosi(bus_mosi), + .bus_miso(mrg_bus_miso), + .bus_busy(mrg_bus_busy), + .led(LED)); + +/* + altserial_flash_loader #( + .enable_shared_access("OFF"), + .enhanced_mode(1), + .intended_device_family("Cyclone III")) sfl_unit ( + .noe(1'b0), + .asmi_access_granted(), + .asmi_access_request(), + .data0out(), + .dclkin(), + .scein(), + .sdoin()); +*/ + +endmodule Index: trunk/3DEES/Paella.cof =================================================================== --- trunk/3DEES/Paella.cof (revision 190) +++ (revision ) @@ -1,18 +1,0 @@ - - - EPCS16 - EP3C25 - Paella.jic - 1 - 1 - 7 - - 1 - - Paella.sof - - - 4 - - - Index: trunk/3DEES/Paella.dpf =================================================================== --- trunk/3DEES/Paella.dpf (revision 190) +++ (revision ) @@ -1,44 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/3DEES/Paella.qpf =================================================================== --- trunk/3DEES/Paella.qpf (revision 190) +++ (revision ) @@ -1,30 +1,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 132 02/25/2009 SJ Web Edition -# Date created = 14:14:14 August 28, 2009 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "9.0" -DATE = "14:14:14 August 28, 2009" - -# Revisions - -PROJECT_REVISION = "Paella" Index: trunk/3DEES/Paella.qsf =================================================================== --- trunk/3DEES/Paella.qsf (revision 190) +++ (revision ) @@ -1,256 +1,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 132 02/25/2009 SJ Web Edition -# Date created = 14:14:14 August 28, 2009 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Paella_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE EP3C25Q240C8 -set_global_assignment -name TOP_LEVEL_ENTITY Paella -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -set_global_assignment -name MISC_FILE Paella.dpf -set_global_assignment -name MISC_FILE "C:/altera/project_12/Paella.dpf" -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF -set_global_assignment -name ENABLE_CLOCK_LATENCY ON -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" -set_global_assignment -name FMAX_REQUIREMENT "240 MHz" -section_id "LVDS Data Clock" -set_instance_assignment -name CLOCK_SETTINGS "LVDS Data Clock" -to ADC_DCO -set_global_assignment -name FMAX_REQUIREMENT "20 MHz" -section_id "LVDS Frame Clock" -set_instance_assignment -name CLOCK_SETTINGS "LVDS Frame Clock" -to ADC_FCO -set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id "USB Clock" -set_instance_assignment -name CLOCK_SETTINGS "USB Clock" -to USB_IFCLK -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3 -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4 -set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5 -set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 6 -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7 -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8 -set_location_assignment PIN_21 -to LED -set_location_assignment PIN_33 -to USB_IFCLK -set_location_assignment PIN_37 -to USB_PA6 -set_location_assignment PIN_38 -to USB_PA4 -set_location_assignment PIN_39 -to USB_PA2 -set_location_assignment PIN_41 -to USB_FLAGB -set_location_assignment PIN_43 -to USB_FLAGA -set_location_assignment PIN_44 -to USB_PB[4] -set_location_assignment PIN_45 -to USB_PB[5] -set_location_assignment PIN_46 -to USB_PB[6] -set_location_assignment PIN_49 -to USB_PB[7] -set_location_assignment PIN_50 -to USB_SLRD -set_location_assignment PIN_51 -to USB_SLWR -set_location_assignment PIN_52 -to USB_PB[0] -set_location_assignment PIN_55 -to USB_PB[1] -set_location_assignment PIN_56 -to USB_PB[2] -set_location_assignment PIN_57 -to USB_PB[3] -set_location_assignment PIN_137 -to "ADC_D[0](n)" -set_location_assignment PIN_139 -to ADC_D[0] -set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0] -set_location_assignment PIN_142 -to "ADC_D[1](n)" -set_location_assignment PIN_143 -to ADC_D[1] -set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1] -set_location_assignment PIN_144 -to "ADC_D[2](n)" -set_location_assignment PIN_145 -to ADC_D[2] -set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2] -set_location_assignment PIN_147 -to "ADC_D[3](n)" -set_location_assignment PIN_148 -to ADC_D[3] -set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[3] -set_location_assignment PIN_149 -to "ADC_DCO(n)" -set_location_assignment PIN_150 -to ADC_DCO -set_instance_assignment -name IO_STANDARD LVDS -to ADC_DCO -set_location_assignment PIN_151 -to "ADC_FCO(n)" -set_location_assignment PIN_152 -to ADC_FCO -set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO -set_location_assignment PIN_159 -to "ADC_D[4](n)" -set_location_assignment PIN_160 -to ADC_D[4] -set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[4] -set_location_assignment PIN_162 -to "ADC_D[5](n)" -set_location_assignment PIN_164 -to ADC_D[5] -set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[5] -set_location_assignment PIN_181 -to RAM_ADDR[12] -set_location_assignment PIN_182 -to RAM_DQAP -set_location_assignment PIN_183 -to RAM_DQA[0] -set_location_assignment PIN_184 -to RAM_DQA[1] -set_location_assignment PIN_185 -to RAM_DQA[2] -set_location_assignment PIN_186 -to RAM_DQA[3] -set_location_assignment PIN_187 -to RAM_DQA[4] -set_location_assignment PIN_188 -to RAM_DQA[5] -set_location_assignment PIN_189 -to RAM_DQA[6] -set_location_assignment PIN_194 -to RAM_DQA[7] -set_location_assignment PIN_195 -to RAM_ADDR[13] -set_location_assignment PIN_196 -to RAM_ADDR[14] -set_location_assignment PIN_197 -to RAM_ADDR[15] -set_location_assignment PIN_200 -to RAM_ADDR[16] -set_location_assignment PIN_201 -to RAM_ADDR[17] -set_location_assignment PIN_202 -to RAM_ADDR[18] -set_location_assignment PIN_203 -to RAM_ADDR[19] -set_location_assignment PIN_207 -to RAM_ADDR[20] -set_location_assignment PIN_210 -to CLK_100MHz -set_location_assignment PIN_214 -to RAM_ADDR[21] -set_location_assignment PIN_216 -to RAM_ADDR[0] -set_location_assignment PIN_217 -to RAM_ADDR[1] -set_location_assignment PIN_218 -to RAM_ADDR[2] -set_location_assignment PIN_219 -to RAM_ADDR[3] -set_location_assignment PIN_221 -to RAM_ADDR[4] -set_location_assignment PIN_223 -to RAM_ADDR[5] -set_location_assignment PIN_224 -to RAM_DQBP -set_location_assignment PIN_226 -to RAM_DQB[0] -set_location_assignment PIN_230 -to RAM_DQB[1] -set_location_assignment PIN_231 -to RAM_DQB[2] -set_location_assignment PIN_232 -to RAM_DQB[3] -set_location_assignment PIN_233 -to RAM_DQB[4] -set_location_assignment PIN_234 -to RAM_DQB[5] -set_location_assignment PIN_235 -to RAM_DQB[6] -set_location_assignment PIN_236 -to RAM_DQB[7] -set_location_assignment PIN_237 -to RAM_ADDR[6] -set_location_assignment PIN_238 -to RAM_ADDR[7] -set_location_assignment PIN_239 -to RAM_CLK -set_location_assignment PIN_240 -to RAM_WE -set_location_assignment PIN_4 -to RAM_ADDR[8] -set_location_assignment PIN_5 -to RAM_ADDR[9] -set_location_assignment PIN_6 -to RAM_ADDR[10] -set_location_assignment PIN_9 -to RAM_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_100MHz -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA6 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA4 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA2 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7] - -set_global_assignment -name MISC_FILE "D:/altera/MultiChannelUSB/Paella.dpf" - -set_global_assignment -name VERILOG_FILE Paella.v -set_global_assignment -name VERILOG_FILE adc_lvds.v -set_global_assignment -name VERILOG_FILE sys_pll.v -set_global_assignment -name VERILOG_FILE control.v -set_global_assignment -name VERILOG_FILE analyser.v -set_global_assignment -name VERILOG_FILE classifier.v -set_global_assignment -name VERILOG_FILE amplitude.v -set_global_assignment -name VERILOG_FILE deconv.v -set_global_assignment -name VERILOG_FILE shift.v -set_global_assignment -name VERILOG_FILE delay.v -set_global_assignment -name VERILOG_FILE coincidence.v -set_global_assignment -name VERILOG_FILE counter.v -set_global_assignment -name VERILOG_FILE histogram32.v -set_global_assignment -name VERILOG_FILE trigger.v -set_global_assignment -name VERILOG_FILE oscilloscope.v -set_global_assignment -name VERILOG_FILE configuration.v -set_global_assignment -name VERILOG_FILE usb_fifo.v -set_global_assignment -name VERILOG_FILE test.v -set_global_assignment -name MIF_FILE test.mif -set_global_assignment -name VERILOG_FILE average.v -set_global_assignment -name VERILOG_FILE filter.v -set_global_assignment -name VERILOG_FILE new_filter.v -set_global_assignment -name VERILOG_FILE clip.v -set_global_assignment -name MISC_FILE "D:/altera/3DEES-6ch/Paella.dpf" -set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id "100 MHz Clock" -set_instance_assignment -name CLOCK_SETTINGS "100 MHz Clock" -to CLK_100MHz -set_global_assignment -name MISC_FILE "D:/altera/3DEES/Paella.dpf" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Index: trunk/3DEES/Paella.v =================================================================== --- trunk/3DEES/Paella.v (revision 190) +++ (revision ) @@ -1,431 +1,0 @@ -module Paella - ( - input wire CLK_100MHz, - output wire LED, - - input wire ADC_DCO, - input wire ADC_FCO, - input wire [5:0] ADC_D, - - output wire USB_SLRD, - output wire USB_SLWR, - input wire USB_IFCLK, - input wire USB_FLAGA, // EMPTY flag for EP6 - input wire USB_FLAGB, // FULL flag for EP8 - output wire USB_PA2, - output wire USB_PA4, - output wire USB_PA6, - inout wire [7:0] USB_PB, - - output wire RAM_CLK, - output wire RAM_WE, - output wire [21:0] RAM_ADDR, - inout wire RAM_DQAP, - inout wire [7:0] RAM_DQA, - inout wire RAM_DQBP, - inout wire [7:0] RAM_DQB - ); - - localparam N = 6; - - // Turn output ports off -/* - assign RAM_CLK = 1'b0; - assign RAM_CE1 = 1'b0; - assign RAM_WE = 1'b0; - assign RAM_ADDR = 20'h00000; -*/ - - assign RAM_CLK = sys_clock; - - assign USB_PA2 = ~usb_rden; - assign USB_PA4 = usb_addr; - assign USB_PA6 = ~usb_pktend; - - wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend; - wire usb_tx_wrreq, usb_rx_rdreq; - wire usb_tx_full, usb_rx_empty; - wire [7:0] usb_tx_data, usb_rx_data; - wire usb_addr; - - assign USB_SLRD = ~usb_rdreq; - assign USB_SLWR = ~usb_wrreq; - - usb_fifo usb_unit - ( - .usb_clock(USB_IFCLK), - .usb_data(USB_PB), - .usb_full(~USB_FLAGB), - .usb_empty(~USB_FLAGA), - .usb_wrreq(usb_wrreq), - .usb_rdreq(usb_rdreq), - .usb_rden(usb_rden), - .usb_pktend(usb_pktend), - .usb_addr(usb_addr), - - .clock(sys_clock), - - .tx_full(usb_tx_full), - .tx_wrreq(usb_tx_wrreq), - .tx_data(usb_tx_data), - - .rx_empty(usb_rx_empty), - .rx_rdreq(usb_rx_rdreq), - .rx_q(usb_rx_data) - ); - -/* - reg [31:0] led_counter; - always @(posedge CLK_50MHz) - begin - led_counter = led_counter + 32'd1; - end - assign LED = led_counter[28]; -*/ - wire [11:0] osc_mux_data [4:0]; - - wire [11:0] trg_mux_data; - wire trg_flag; - - wire [6*12-1:0] int_mux_data [N-1:0]; - - wire [1:0] amp_flag [3*N-1:0]; - wire [12:0] amp_data [3*N-1:0]; - - wire cls_flag; - wire [6:0] cls_data; - - wire [1:0] amp_mux_flag [2:0]; - wire [11:0] amp_mux_data [2:0]; - - wire cnt_good [3:0]; - wire [15:0] cnt_bits_wire; - - wire sys_clock, sys_frame; - - wire [11:0] adc_data [N-1:0]; - wire [11:0] sys_data [N-1:0]; - wire [11:0] tst_data; - - wire [3:0] cmp_data; - wire [1:0] del_data; - - wire [19:0] cic_data [N-1:0]; - - wire [11:0] dec_data [N-1:0]; - wire [12:0] clp_data [N-1:0]; - wire [11:0] tmp_data; - - - wire i2c_reset; - - assign tmp_data = 12'd0; -/* - assign sys_clock = CLK_100MHz; -*/ - sys_pll sys_pll_unit( - .inclk0(CLK_100MHz), - .c0(sys_clock)); - -/* - sys_pll sys_pll_unit( - .inclk0(CLK_100MHz), - .c0(sys_clock), - .c1(ADC_DCO), - .c2(ADC_FCO)); - - wire ADC_DCO, ADC_FCO; - - - test test_unit( - .clock(ADC_FCO), - .data(tst_data)); -*/ - - adc_lvds #( - .size(6), - .width(12)) adc_lvds_unit ( - .clock(sys_clock), - .lvds_dco(ADC_DCO), - .lvds_fco(ADC_FCO), - .lvds_d(ADC_D), -// .test(tst_data), - .adc_frame(sys_frame), - .adc_data({ - adc_data[5], adc_data[3], adc_data[4], // D3, D1, D2 - adc_data[2], adc_data[1], adc_data[0]})); // S2, S1_S, S1_F - - wire [15:0] cfg_bits [63:0]; - wire [1023:0] int_cfg_bits; - - wire [39:0] cfg_mux_selector; - - wire cfg_reset; - - wire [2:0] bus_ssel; - wire bus_wren; - wire [31:0] bus_addr; - wire [15:0] bus_mosi; - wire [15:0] bus_miso [2:0]; - wire [2:0] bus_busy; - - wire [15:0] mrg_bus_miso; - wire mrg_bus_busy; - - wire [3*16-1:0] int_bus_miso; - - genvar j; - - generate - for (j = 0; j < 64; j = j + 1) - begin : CONFIGURATION_OUTPUT - assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16]; - end - endgenerate - - configuration configuration_unit ( - .clock(sys_clock), - .reset(cfg_reset), - .bus_ssel(bus_ssel[0]), - .bus_wren(bus_wren), - .bus_addr(bus_addr[5:0]), - .bus_mosi(bus_mosi), - .bus_miso(bus_miso[0]), - .bus_busy(bus_busy[0]), - .cfg_bits(int_cfg_bits)); - - generate - for (j = 0; j < 6; j = j + 1) - begin : MUX_DATA - assign int_mux_data[j] = { - {4'd0, cls_flag, 7'd0}, - {5'd0, cls_data}, - {4'd0, amp_flag[j][0], 7'd0}, - amp_data[j][11:0], - clp_data[j][11:0], - sys_data[j] - }; - end - endgenerate - - assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]}; - - lpm_mux #( - .lpm_size(6*6), - .lpm_type("LPM_MUX"), - .lpm_width(12), - .lpm_widths(6)) trg_mux_unit ( - .sel(cfg_bits[4][13:8]), - .data({ - int_mux_data[5], int_mux_data[4], int_mux_data[3], - int_mux_data[2], int_mux_data[1], int_mux_data[0]}), - .result(trg_mux_data)); - - generate - for (j = 0; j < 5; j = j + 1) - begin : OSC_CHAIN - - lpm_mux #( - .lpm_size(6*6), - .lpm_type("LPM_MUX"), - .lpm_width(12), - .lpm_widths(6)) osc_mux_unit ( - .sel(cfg_mux_selector[j*8+5:j*8]), - .data({ - int_mux_data[5], int_mux_data[4], int_mux_data[3], - int_mux_data[2], int_mux_data[1], int_mux_data[0]}), - .result(osc_mux_data[j])); - end - endgenerate - - trigger trigger_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(cfg_bits[0][0]), - .cfg_data(cfg_bits[5][11:0]), - .trg_data(trg_mux_data), - .trg_flag(trg_flag)); - - oscilloscope oscilloscope_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(cfg_bits[0][1]), - .cfg_data(cfg_bits[5][12]), - .trg_flag(trg_flag), - .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), - .ram_wren(RAM_WE), - .ram_addr(RAM_ADDR), - .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}), - .bus_ssel(bus_ssel[1]), - .bus_wren(bus_wren), - .bus_addr(bus_addr[19:0]), - .bus_mosi(bus_mosi), - .bus_miso(bus_miso[1]), - .bus_busy(bus_busy[1])); - - filter #(.size(6), .width(12)) filter_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(1'b0), - .inp_data({sys_data[5], sys_data[4], sys_data[3], - sys_data[2], sys_data[1], sys_data[0]}), - .out_data({cic_data[5], cic_data[4], cic_data[3], - cic_data[2], cic_data[1], cic_data[0]})); -/* - new_filter #(.size(6), .width(12)) filter_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(1'b0), - .inp_data({sys_data[5], sys_data[4], sys_data[3], - sys_data[2], sys_data[1], sys_data[0]}), - .out_data({cic_data[5], cic_data[4], cic_data[3], - cic_data[2], cic_data[1], cic_data[0]})); -*/ - - generate - for (j = 0; j < 2; j = j + 1) - begin : DECONV_CHAIN - - clip #(.shift(21), .width(19), .widthr(13)) clip_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(1'b0), -// .del_data({6'd0, 6'd32, 6'd32, 6'd32}), - .del_data({6'd0, cfg_bits[43+6*j][5:0], cfg_bits[41+6*j][5:0], cfg_bits[39+6*j][5:0]}), - .amp_data({6'd0, 6'd20, 6'd20, 6'd20}), -// .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}), -// exp(-32/1000)*1024*20 - .tau_data({16'd0, cfg_bits[42+6*j], cfg_bits[40+6*j], cfg_bits[38+6*j]}), - .inp_data({ - 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}), - .out_data({ - tmp_data, clp_data[j*3+2], clp_data[j*3+1], clp_data[j*3+0]})); - - end - endgenerate - - generate - for (j = 0; j < 6; j = j + 1) - begin : MCA_CHAIN -/* - shift #(.shift(11), .width(19), .widthr(13)) shift_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(1'b0), - .amp_data(6'd21), - .inp_data(cic_data[j][18:0]), - .out_data(clp_data[j])); -*/ - assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); - - amplitude #(.width(13)) amplitude_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(1'b0), -// .min_data(13'd20), - .min_data(cfg_bits[10+j][12:0]), - .max_data(13'd4095), - .inp_data(clp_data[j]), - .out_flag(amp_flag[j]), - .out_data(amp_data[j])); - end - endgenerate - -// {D3, D2, D1, S2, S1_S, S1_F} - classifier #(.width(12)) classifier_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(1'b0), -// .cfg_data({12'd20, 12'd20, -// 12'd20, 12'd20, 12'd20, 12'd20, 12'd2000, 12'd20, -// 12'd20, 12'd2000, 12'd2000, 12'd20, 12'd1000, 12'd1000}), - .cfg_data({cfg_bits[37][11:0], cfg_bits[36][11:0], - cfg_bits[35][11:0], cfg_bits[34][11:0], cfg_bits[33][11:0], cfg_bits[32][11:0], - cfg_bits[31][11:0], cfg_bits[30][11:0], cfg_bits[29][11:0], cfg_bits[28][11:0], - cfg_bits[27][11:0], cfg_bits[26][11:0], cfg_bits[25][11:0], cfg_bits[24][11:0], - cfg_bits[23][11:0], cfg_bits[22][11:0], cfg_bits[21][11:0], cfg_bits[20][11:0], - cfg_bits[19][11:0], cfg_bits[18][11:0], cfg_bits[17][11:0], cfg_bits[16][11:0]}), - .inp_data({amp_data[5][11:0], amp_data[4][11:0], amp_data[3][11:0], - amp_data[2][11:0], amp_data[1][11:0], amp_data[0][11:0]}), - .inp_flag({amp_flag[5][0], amp_flag[4][0], amp_flag[3][0], - amp_flag[2][0], amp_flag[1][0], amp_flag[0][0]}), - .out_flag(cls_flag), - .out_data(cls_data)); - - histogram32 histogram32_unit ( - .clock(sys_clock), - .frame(sys_frame), - .reset(cfg_bits[0][5]), - .hst_good(cls_flag & cfg_bits[6][0]), - .hst_data(cls_data), - .bus_ssel(bus_ssel[2]), - .bus_wren(bus_wren), - .bus_addr(bus_addr[7:0]), - .bus_mosi(bus_mosi), - .bus_miso(bus_miso[2]), - .bus_busy(bus_busy[2])); - - - generate - for (j = 0; j < 3; j = j + 1) - begin : BUS_OUTPUT - assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; - end - endgenerate - - lpm_mux #( - .lpm_size(3), - .lpm_type("LPM_MUX"), - .lpm_width(16), - .lpm_widths(2)) bus_miso_mux_unit ( - .sel(bus_addr[29:28]), - .data(int_bus_miso), - .result(mrg_bus_miso)); - - lpm_mux #( - .lpm_size(3), - .lpm_type("LPM_MUX"), - .lpm_width(1), - .lpm_widths(2)) bus_busy_mux_unit ( - .sel(bus_addr[29:28]), - .data(bus_busy), - .result(mrg_bus_busy)); - - lpm_decode #( - .lpm_decodes(3), - .lpm_type("LPM_DECODE"), - .lpm_width(2)) lpm_decode_unit ( - .data(bus_addr[29:28]), - .eq(bus_ssel)); - - - control control_unit ( - .clock(sys_clock), - .rx_empty(usb_rx_empty), - .tx_full(usb_tx_full), - .rx_data(usb_rx_data), - .rx_rdreq(usb_rx_rdreq), - .tx_wrreq(usb_tx_wrreq), - .tx_data(usb_tx_data), - .bus_wren(bus_wren), - .bus_addr(bus_addr), - .bus_mosi(bus_mosi), - .bus_miso(mrg_bus_miso), - .bus_busy(mrg_bus_busy), - .led(LED)); - -/* - altserial_flash_loader #( - .enable_shared_access("OFF"), - .enhanced_mode(1), - .intended_device_family("Cyclone III")) sfl_unit ( - .noe(1'b0), - .asmi_access_granted(), - .asmi_access_request(), - .data0out(), - .dclkin(), - .scein(), - .sdoin()); -*/ - -endmodule