Changeset 190
- Timestamp:
- Mar 27, 2014, 11:46:21 PM (10 years ago)
- Location:
- trunk/3DEES
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/3DEES/Paella.v
r188 r190 94 94 95 95 wire cls_flag; 96 wire [ 7:0] cls_data;96 wire [6:0] cls_data; 97 97 98 98 wire [1:0] amp_mux_flag [2:0]; … … 200 200 assign int_mux_data[j] = { 201 201 {4'd0, cls_flag, 7'd0}, 202 { 4'd0, cls_data},202 {5'd0, cls_data}, 203 203 {4'd0, amp_flag[j][0], 7'd0}, 204 204 amp_data[j][11:0], … … 246 246 .trg_data(trg_mux_data), 247 247 .trg_flag(trg_flag)); 248 248 249 249 oscilloscope oscilloscope_unit ( 250 250 .clock(sys_clock), … … 358 358 .reset(cfg_bits[0][5]), 359 359 .hst_good(cls_flag & cfg_bits[6][0]), 360 .hst_data(cls_data [6:0]),360 .hst_data(cls_data), 361 361 .bus_ssel(bus_ssel[2]), 362 362 .bus_wren(bus_wren), -
trunk/3DEES/classifier.v
r189 r190 8 8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F} 9 9 input wire [5:0] inp_flag, 10 output wire [ 7:0] out_data,10 output wire [6:0] out_data, 11 11 output wire out_flag 12 12 ); 13 13 14 reg out_flag_reg [ 2:0], out_flag_next [2:0];15 reg [ 10:0] out_data_reg [2:0], out_data_next [2:0];14 reg out_flag_reg [1:0], out_flag_next [1:0]; 15 reg [8:0] out_data_reg [1:0], out_data_next [1:0]; 16 16 reg [5:0] inp_flag_reg, inp_flag_next; 17 17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0]; 18 reg [15:0] int_pipe_reg [2 3:0], int_pipe_next [23:0];18 reg [15:0] int_pipe_reg [25:0], int_pipe_next [25:0]; 19 19 reg [2:0] int_data_reg [3:0], int_data_next [3:0]; 20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0]; 20 reg [3:0] int_temp_reg [1:0], int_temp_next [1:0]; 21 reg int_flag_reg [1:0], int_flag_next [1:0]; 21 22 22 23 wire [width-1:0] inp_data_wire [5:0]; 23 wire [3:0] int_pipe_wire [5:0]; 24 wire [19:0] int_comp_wire; 24 wire [3:0] int_pipe_wire [6:0]; 25 wire [20:0] int_comp_wire; 26 27 reg [3:0] add_data_reg [1:0], add_data_next [1:0]; 28 wire [2:0] add_data_wire; 25 29 26 30 integer i; … … 34 38 endgenerate 35 39 40 assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]); 41 assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]); 42 43 assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]); 44 assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]); 36 45 generate 37 assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]);38 assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]);39 40 assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]);41 assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]);42 43 46 for (j = 0; j < 4; j = j + 1) 44 47 begin : CLASSIFIER_COMPARTORS … … 49 52 end 50 53 endgenerate 51 52 generate 53 for (j = 0; j < 4; j = j + 1) 54 begin : CLASSIFIER_PIPELINE 55 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]); 56 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]); 57 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*4+0+8]); 58 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*4+1+8]); 59 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*4+2+8]); 60 assign int_pipe_wire[j+2][3] = (|int_pipe_reg[j*4+3+8]); 61 end 62 endgenerate 54 55 assign int_comp_wire[20] = add_data_reg[1] > add_data_reg[0]; 56 57 assign int_pipe_wire[0] = {|int_pipe_reg[3], |int_pipe_reg[2], |int_pipe_reg[1], |int_pipe_reg[0]}; 58 59 assign int_pipe_wire[1] = {1'b0, 1'b0, |int_pipe_reg[5], |int_pipe_reg[4]}; 60 assign int_pipe_wire[2] = {|int_pipe_reg[9], |int_pipe_reg[8], |int_pipe_reg[7], |int_pipe_reg[6]}; 61 62 assign int_pipe_wire[3] = {|int_pipe_reg[13], |int_pipe_reg[12], |int_pipe_reg[11], |int_pipe_reg[10]}; 63 assign int_pipe_wire[4] = {|int_pipe_reg[17], |int_pipe_reg[16], |int_pipe_reg[15], |int_pipe_reg[14]}; 64 assign int_pipe_wire[5] = {|int_pipe_reg[21], |int_pipe_reg[20], |int_pipe_reg[19], |int_pipe_reg[18]}; 65 assign int_pipe_wire[6] = {|int_pipe_reg[25], |int_pipe_reg[24], |int_pipe_reg[23], |int_pipe_reg[22]}; 66 67 parallel_add #( 68 .msw_subtract("NO"), 69 .representation("UNSIGNED"), 70 .result_alignment("LSB"), 71 .shift(0), 72 .size(6), 73 .width(1), 74 .widthr(3)) parallel_add_unit ( 75 .data({int_pipe_wire[2], int_pipe_wire[1][1:0]}), 76 .result(add_data_wire)); 63 77 64 78 always @(posedge clock) … … 67 81 begin 68 82 inp_flag_reg <= {(6){1'b0}}; 69 for (i = 0; i < 3; i = i + 1) 70 begin 71 out_data_reg[i] <= {(11){1'b0}}; 72 out_flag_reg[i] <= 1'b0; 83 for (i = 0; i < 2; i = i + 1) 84 begin 85 out_data_reg[i] <= {(9){1'b0}}; 86 out_flag_reg[i] <= {(1){1'b0}}; 87 int_flag_reg[i] <= {(1){1'b0}}; 88 int_temp_reg[i] <= {(4){1'b0}}; 89 add_data_reg[i] <= {(3){1'b0}}; 73 90 end 74 91 for (i = 0; i < 6; i = i + 1) … … 76 93 inp_data_reg[i] <= {(width){1'b0}}; 77 94 end 78 for (i = 0; i < 2 4; i = i + 1)95 for (i = 0; i < 26; i = i + 1) 79 96 begin 80 97 int_pipe_reg[i] <= {(16){1'b0}}; … … 84 101 int_data_reg[i] <= {(3){1'b0}}; 85 102 end 103 end 104 else 105 begin 106 inp_flag_reg <= inp_flag_next; 86 107 for (i = 0; i < 2; i = i + 1) 87 begin88 int_temp_reg[i] <= {(5){1'b0}};89 end90 end91 else92 begin93 inp_flag_reg <= inp_flag_next;94 for (i = 0; i < 3; i = i + 1)95 108 begin 96 109 out_data_reg[i] <= out_data_next[i]; 97 110 out_flag_reg[i] <= out_flag_next[i]; 111 int_flag_reg[i] <= int_flag_next[i]; 112 int_temp_reg[i] <= int_temp_next[i]; 113 add_data_reg[i] <= add_data_next[i]; 98 114 end 99 115 for (i = 0; i < 6; i = i + 1) … … 101 117 inp_data_reg[i] <= inp_data_next[i]; 102 118 end 103 for (i = 0; i < 2 4; i = i + 1)119 for (i = 0; i < 26; i = i + 1) 104 120 begin 105 121 int_pipe_reg[i] <= int_pipe_next[i]; … … 108 124 begin 109 125 int_data_reg[i] <= int_data_next[i]; 110 end111 for (i = 0; i < 2; i = i + 1)112 begin113 int_temp_reg[i] <= int_temp_next[i];114 126 end 115 127 end … … 119 131 begin 120 132 inp_flag_next = inp_flag_reg; 121 for (i = 0; i < 3; i = i + 1)133 for (i = 0; i < 2; i = i + 1) 122 134 begin 123 135 out_data_next[i] = out_data_reg[i]; 124 136 out_flag_next[i] = out_flag_reg[i]; 137 int_flag_next[i] = int_flag_reg[i]; 138 int_temp_next[i] = int_temp_reg[i]; 139 add_data_next[i] = add_data_reg[i]; 125 140 end 126 141 for (i = 0; i < 6; i = i + 1) … … 128 143 inp_data_next[i] = inp_data_reg[i]; 129 144 end 130 for (i = 0; i < 2 4; i = i + 1)145 for (i = 0; i < 26; i = i + 1) 131 146 begin 132 147 int_pipe_next[i] = int_pipe_reg[i]; … … 135 150 begin 136 151 int_data_next[i] = int_data_reg[i]; 137 end138 for (i = 0; i < 2; i = i + 1)139 begin140 int_temp_next[i] = int_temp_reg[i];141 152 end 142 153 … … 149 160 end 150 161 151 if (out_flag_reg[2]) 152 begin 153 for (i = 0; i < 3; i = i + 1) 154 begin 155 out_data_next[i] = {(11){1'b0}}; 156 out_flag_next[i] = 1'b0; 157 end 158 for (i = 0; i < 24; i = i + 1) 162 if (int_flag_reg[1]) 163 begin 164 for (i = 0; i < 2; i = i + 1) 165 begin 166 out_data_next[i] = {(9){1'b0}}; 167 out_flag_next[i] = {(1){1'b0}}; 168 int_flag_next[i] = {(1){1'b0}}; 169 int_temp_next[i] = {(4){1'b0}}; 170 add_data_next[i] = {(3){1'b0}}; 171 end 172 for (i = 0; i < 26; i = i + 1) 159 173 begin 160 174 int_pipe_next[i] = {(16){1'b0}}; 161 175 end 162 int_temp_next[0] = {(5){1'b0}};163 int_temp_next[1] = {(5){1'b0}};164 176 end 165 177 else 166 178 begin 167 out_data_next[0] = {(11){1'b0}}; 168 out_data_next[1] = out_data_reg[0]; 169 out_data_next[2] = {3'd0, out_data_reg[1][10:5], 2'd0} + {6'd0, out_data_reg[1][4:0]}; 170 171 out_flag_next[0] = 1'b1; 172 out_flag_next[1] = out_flag_reg[0]; 173 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]); 179 out_data_next[0] = {(9){1'b0}}; 180 out_data_next[1] = {out_data_reg[0][3:0], 2'd0} + out_data_reg[0][8:4]; 181 182 out_flag_next[0] = int_flag_reg[0]; 183 out_flag_next[1] = out_flag_reg[0] & int_comp_wire[20]; 184 185 int_flag_next[0] = ^int_pipe_wire[1][1:0]; 186 int_flag_next[1] = int_comp_wire[20]; 187 188 add_data_next[0] = add_data_wire; 189 add_data_next[1] = add_data_reg[0]; 174 190 175 191 for (i = 0; i < 4; i = i + 1) … … 177 193 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]}; 178 194 end 179 for (i = 4; i < 8; i = i + 1)180 begin 181 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i- 2]};182 end 183 for (i = 8; i < 24; i = i + 1)184 begin 185 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i- 4]};195 for (i = 4; i < 10; i = i + 1) 196 begin 197 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-4]}; 198 end 199 for (i = 10; i < 26; i = i + 1) 200 begin 201 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]}; 186 202 end 187 203 188 204 for (i = 0; i < 4; i = i + 1) 189 205 begin 190 case (int_pipe_wire[i+ 2][3:0])206 case (int_pipe_wire[i+3][3:0]) 191 207 4'b0000: int_data_next[i] = 3'b000; 192 208 4'b0001: int_data_next[i] = 3'b001; … … 198 214 end 199 215 200 int_temp_next[0] = {int_pipe_wire[1], ^int_pipe_wire[0]};201 int_temp_next[1] = {1'b0, int_pipe_wire[0]};202 203 case (int_temp_reg[ 0][4:0])204 5'b00011: out_data_next[0][4:0] = int_data_next[0];205 5'b00111: out_data_next[0][4:0] = int_data_next[1] + 4'd5;206 5'b01111: out_data_next[0][4:0] = int_data_next[2] + 4'd10;207 5'b11111: out_data_next[0][4:0] = int_data_next[3] + 4'd15;216 int_temp_next[0] = int_pipe_wire[0]; 217 int_temp_next[1] = int_pipe_wire[2]; 218 219 case (int_temp_reg[1]) 220 4'b0001: out_data_next[0][8:4] = int_data_reg[0] + 5'b00000; 221 4'b0011: out_data_next[0][8:4] = int_data_reg[1] + 5'b00101; 222 4'b0111: out_data_next[0][8:4] = int_data_reg[2] + 5'b01010; 223 4'b1111: out_data_next[0][8:4] = int_data_reg[3] + 5'b01111; 208 224 default: out_flag_next[0] = 1'b0; 209 225 endcase 210 226 211 case (int_temp_reg[ 1][3:0])227 case (int_temp_reg[0]) 212 228 // S1_F, electron 213 4'b0001: out_data_next[0][ 10:5] = 6'b100000;229 4'b0001: out_data_next[0][3:0] = 4'b0000; 214 230 215 231 // S1_F, proton 216 4'b0010: out_data_next[0][ 10:5] = 6'b100101;232 4'b0010: out_data_next[0][3:0] = 4'b0101; 217 233 218 234 // S1_S, electron 219 4'b0100: out_data_next[0][ 10:5] = 6'b101010;235 4'b0100: out_data_next[0][3:0] = 4'b1010; 220 236 221 237 // S1_S, proton 222 4'b1000: out_data_next[0][ 10:5] = 6'b101111;238 4'b1000: out_data_next[0][3:0] = 4'b1111; 223 239 224 240 default: out_flag_next[0] = 1'b0; … … 231 247 // assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]}; 232 248 // assign out_data = {1'd0, int_temp_reg[0][4:0]}; 233 assign out_data = out_data_reg[ 2][7:0];234 assign out_flag = out_flag_reg[ 2];249 assign out_data = out_data_reg[1][6:0]; 250 assign out_flag = out_flag_reg[1]; 235 251 236 252 endmodule
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