Index: trunk/3DEES/classifier.v
===================================================================
--- trunk/3DEES/classifier.v	(revision 181)
+++ trunk/3DEES/classifier.v	(revision 183)
@@ -12,9 +12,9 @@
 	);
 
-	reg					out_flag_reg, out_flag_next;
-	reg		[5:0]		out_data_reg, out_data_next;
+	reg					out_flag_reg [2:0], out_flag_next [2:0];
+	reg		[5:0]		out_data_reg [2:0], out_data_next [2:0];
 	reg		[5:0]		inp_flag_reg, inp_flag_next;
 	reg		[width-1:0]	inp_data_reg [5:0], inp_data_next [5:0];
-	reg		[15:0]		int_pipe_reg [19:0], int_pipe_next [19:0];	
+	reg		[15:0]		int_pipe_reg [19:0], int_pipe_next [19:0];
 	reg		[1:0]		int_data_reg [3:0], int_data_next [3:0];
 	reg		[4:0]		int_temp_reg [1:0], int_temp_next [1:0];
@@ -42,7 +42,7 @@
 			assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);
 			assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);
-		end                                                                                        
+		end
 	endgenerate
-				
+
 	generate
 		for (j = 0; j < 4; j = j + 1)
@@ -56,5 +56,5 @@
 		end
 	endgenerate
-		
+
 	always @(posedge clock)
 	begin
@@ -62,6 +62,9 @@
 		begin
 			inp_flag_reg <= {(6){1'b0}};
-			out_data_reg <= {(6){1'b0}};
-			out_flag_reg <= 1'b0;
+			for (i = 0; i < 3; i = i + 1)
+			begin
+				out_data_reg[i] <= {(6){1'b0}};
+				out_flag_reg[i] <= 1'b0;
+			end
 			for (i = 0; i < 6; i = i + 1)
 			begin
@@ -84,6 +87,9 @@
 		begin
 			inp_flag_reg <= inp_flag_next;
-			out_data_reg <= out_data_next;
-			out_flag_reg <= out_flag_next;
+			for (i = 0; i < 3; i = i + 1)
+			begin
+				out_data_reg[i] <= out_data_next[i];
+				out_flag_reg[i] <= out_flag_next[i];
+			end
 			for (i = 0; i < 6; i = i + 1)
 			begin
@@ -104,10 +110,13 @@
 		end
 	end
-	
+
 	always @*
 	begin
 		inp_flag_next = inp_flag_reg;
-		out_data_next = out_data_reg;
-		out_flag_next = out_flag_reg;
+		for (i = 0; i < 3; i = i + 1)
+		begin
+			out_data_next[i] = out_data_reg[i];
+			out_flag_next[i] = out_flag_reg[i];
+		end
 		for (i = 0; i < 6; i = i + 1)
 		begin
@@ -134,8 +143,12 @@
 				inp_data_next[i] = inp_data_wire[i];
 			end
-		
-			if (out_flag_reg)
-			begin
-				out_flag_next = 1'b0;
+
+			if (out_flag_reg[2])
+			begin
+				for (i = 0; i < 3; i = i + 1)
+				begin
+					out_data_next[i] = {(6){1'b0}};
+					out_flag_next[i] = 1'b0;
+				end
 				for (i = 0; i < 20; i = i + 1)
 				begin
@@ -144,9 +157,15 @@
 				int_temp_next[0] = {(5){1'b0}};
 				int_temp_next[1] = {(5){1'b0}};
-				out_data_next = {(6){1'b0}};
 			end
 			else
 			begin
-				out_flag_next = 1'b1;
+				out_data_next[0] = {(6){1'b0}};		
+				out_data_next[1] = out_data_reg[0];
+				out_data_next[2] = out_data_reg[1];
+
+				out_flag_next[0] = 1'b1;				
+				out_flag_next[1] = out_flag_reg[0];
+				out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]);
+
 				int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]};
 				int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]};
@@ -170,30 +189,30 @@
 					endcase
 				end
-				
+
 				int_temp_next[0] = {int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]};
 				int_temp_next[1] = {1'b0, int_pipe_wire[0]};
 
 				case (int_temp_reg[0][4:0])
-					5'b00011: out_data_next[3:0] = {2'd0, int_data_next[0]};
-					5'b00111: out_data_next[3:0] = {2'd1, int_data_next[1]};
-					5'b01111: out_data_next[3:0] = {2'd2, int_data_next[2]};
-					5'b11111: out_data_next[3:0] = {2'd3, int_data_next[3]};
-					default: out_flag_next = 1'b0;
+					5'b00011: out_data_next[0][3:0] = {2'd0, int_data_next[0]};
+					5'b00111: out_data_next[0][3:0] = {2'd1, int_data_next[1]};
+					5'b01111: out_data_next[0][3:0] = {2'd2, int_data_next[2]};
+					5'b11111: out_data_next[0][3:0] = {2'd3, int_data_next[3]};
+					default: out_flag_next[0] = 1'b0;
 				endcase
-	
+
 				case (int_temp_reg[1][3:0])
 					// S1_F, electron
-					4'b0100: out_data_next[5:4] = 2'd0;
-										
+					4'b0100: out_data_next[0][5:4] = 2'd0;
+
 					// S1_F, proton
-					4'b0101: out_data_next[5:4] = 2'd1;
-										 
+					4'b0101: out_data_next[0][5:4] = 2'd1;
+
 					// S1_S, electron
-					4'b1000: out_data_next[5:4] = 2'd2;
-										 
+					4'b1000: out_data_next[0][5:4] = 2'd2;
+
 					// S1_S, proton
-					4'b1010: out_data_next[5:4] = 2'd3;
-										 
-					default: out_flag_next = 1'b0;
+					4'b1010: out_data_next[0][5:4] = 2'd3;
+
+					default: out_flag_next[0] = 1'b0;
 				endcase
 			end
@@ -204,6 +223,6 @@
 //	assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
 //	assign out_data = {1'd0, int_temp_reg[0][4:0]};
-	assign out_data = out_data_reg;
-	assign out_flag = out_flag_reg;
+	assign out_data = out_data_reg[2];
+	assign out_flag = out_flag_reg[2];
 
 endmodule
