Index: /trunk/3DEES/Paella.qsf
===================================================================
--- /trunk/3DEES/Paella.qsf	(revision 178)
+++ /trunk/3DEES/Paella.qsf	(revision 179)
@@ -251,7 +251,4 @@
 set_global_assignment -name VERILOG_FILE Paella.v
 set_global_assignment -name VERILOG_FILE adc_lvds.v
-set_global_assignment -name VERILOG_FILE cic_pipeline.v
-set_global_assignment -name VERILOG_FILE cic_filter.v
-set_global_assignment -name VERILOG_FILE uwt_bior31.v
 set_global_assignment -name VERILOG_FILE sys_pll.v
 set_global_assignment -name VERILOG_FILE control.v
Index: unk/3DEES/cic_filter.v
===================================================================
--- /trunk/3DEES/cic_filter.v	(revision 178)
+++ 	(revision )
@@ -1,273 +1,0 @@
-module cic_filter
-	#(
-		parameter	size	=	3, // number of channels
-		parameter	width	=	12 // bit width of the input data (unsigned)
-	)
-	(
-		input	wire						clock, frame, reset,
-		input	wire	[size*width-1:0]	inp_data,
-		output	wire	[size*widthr-1:0]	out_data,
-		output	wire	[size*widthr-1:0]	out_data2,
-		output	wire	[size*widthr-1:0]	out_data3
-	);
-	
-	localparam	widthr	=	width + 16;
-	/*
-	4-bit LFSR with additional bits to keep track of previous values
-	*/
-	reg		[15:0]				int_lfsr_reg, int_lfsr_next;
-
-	reg							int_wren_reg, int_wren_next;
-	reg							int_flag_reg, int_flag_next;
-	reg		[1:0]				int_chan_reg, int_chan_next;
-	reg		[2:0]				int_case_reg, int_case_next;
-	reg		[7:0]				int_addr_reg, int_addr_next;
-
-	wire	[9:0]				int_addr_wire;
-
-	reg		[size*widthr-1:0]	acc_data_reg [3:0], acc_data_next [3:0];
-	reg		[size*widthr-1:0]	int_data_reg [12:0], int_data_next [12:0];
-
-	wire	[size*widthr-1:0]	acc_data_wire [3:0], del_data_wire [1:0];
-
-	integer i;
-	genvar j;
-
-	generate
-		for (j = 0; j < size; j = j + 1)
-		begin : INT_DATA
-			assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
-
-			// -2*del_data_1 + del_data_2 + inp_data + result
-
-			assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
-				  acc_data_reg[0][j*widthr+widthr-1:j*widthr]
-				+ del_data_wire[1][j*widthr+widthr-1:j*widthr]
-				- {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0};
-
-			assign acc_data_wire[2][j*widthr+widthr-1:j*widthr] =
-				  acc_data_reg[1][j*widthr+widthr-1:j*widthr]
-				+ acc_data_reg[2][j*widthr+widthr-1:j*widthr];
-
-			assign acc_data_wire[3][j*widthr+widthr-1:j*widthr] =
-				  acc_data_reg[2][j*widthr+widthr-1:j*widthr]
-				+ acc_data_reg[3][j*widthr+widthr-1:j*widthr];
-
-		end
-	endgenerate
-
-	cic_pipeline #(
-		.width(size*widthr)) cic_pipeline_unit (
-		.clock(clock),
-		.data(acc_data_reg[0]),
-		.rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}),
-		.rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}),
-		.wraddress(int_addr_reg),
-		.wren(int_wren_reg),
-		.qa(del_data_wire[0]),
-		.qb(del_data_wire[1]));
-
-	lpm_mux #(
-		.lpm_size(4),
-		.lpm_type("LPM_MUX"),
-		.lpm_width(10),
-		.lpm_widths(2)) mux_unit_1 (
-		.sel(int_chan_next),
-		.data({
-			2'd3, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
-			2'd2, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
-			2'd1, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3],
-			2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}),
-		.result(int_addr_wire));                            
-
-	always @(posedge clock)
-	begin
-		if (reset)
-        begin
-			int_wren_reg <= 1'b1;
-			int_flag_reg <= 1'b0;
-			int_chan_reg <= 2'd0;
-			int_case_reg <= 3'd0;
-			int_addr_reg <= 8'd0;
-			for(i = 0; i <= 3; i = i + 1)
-			begin
-				acc_data_reg[i] <= {(size*widthr){1'b0}};
-			end
-			for(i = 0; i <= 12; i = i + 1)
-			begin
-				int_data_reg[i] <= {(size*widthr){1'b0}};
-			end
-			int_lfsr_reg <= 16'd0;
-		end
-		else
-		begin
-			int_wren_reg <= int_wren_next;
-			int_flag_reg <= int_flag_next;
-			int_chan_reg <= int_chan_next;
-			int_case_reg <= int_case_next;
-			int_addr_reg <= int_addr_next;
-			for(i = 0; i <= 3; i = i + 1)
-			begin
-				acc_data_reg[i] <= acc_data_next[i];
-			end
-			for(i = 0; i <= 12; i = i + 1)
-			begin
-				int_data_reg[i] <= int_data_next[i];
-			end
-			int_lfsr_reg <= int_lfsr_next;
-		end             
-	end
-	
-	always @*
-	begin
-		int_wren_next = int_wren_reg;
-		int_flag_next = int_flag_reg;
-		int_chan_next = int_chan_reg;
-		int_case_next = int_case_reg;
-		int_addr_next = int_addr_reg;
-		for(i = 0; i <= 3; i = i + 1)
-		begin
-			acc_data_next[i] = acc_data_reg[i];
-		end
-		for(i = 0; i <= 12; i = i + 1)
-		begin
-			int_data_next[i] = int_data_reg[i];
-		end
-		int_lfsr_next = int_lfsr_reg;
-
-		case (int_case_reg)		
-			0:
-			begin
-				// write zeros
-				int_wren_next = 1'b1;
-				int_addr_next = 8'd0;
-				for(i = 0; i <= 3; i = i + 1)
-				begin
-					acc_data_next[i] = {(size*widthr){1'b0}};
-				end
-				for(i = 0; i <= 12; i = i + 1)
-				begin
-					int_data_next[i] = {(size*widthr){1'b0}};
-				end
-				int_case_next = 3'd1;
-			end	
-			1:
-			begin
-				// write zeros
-				int_addr_next = int_addr_reg + 8'd1;
-				if (&int_addr_reg)
-				begin
-					int_wren_next = 1'b0;
-					int_flag_next = 1'b0;
-					int_chan_next = 2'd0;
-					int_lfsr_next = 16'h7650;
-					int_case_next = 3'd2;
-				end
-			end	
-			2: // frame
-			begin
-				int_flag_next = 1'b0;
-				if (frame)
-				begin
-					int_wren_next = 1'b1;
-
-					int_addr_next = {4'd0, int_lfsr_reg[3:0]};
-					
-					// set read addr for 2nd pipeline
-					int_chan_next = 2'd1;
-                    
-					// prepare registers for 1st sum					
-					acc_data_next[0] = acc_data_wire[0];
-					acc_data_next[1] = int_data_reg[0];
-					acc_data_next[2] = int_data_reg[1];
-					acc_data_next[3] = int_data_reg[2];
-					
-					int_case_next = 3'd3;
-				end
-				if (int_flag_reg) // register 4th sum
-				begin
-					// register 4th sum
-					int_data_next[9] = acc_data_wire[1];
-					int_data_next[10] = acc_data_wire[2];
-					int_data_next[11] = acc_data_wire[3];
-				end
-			end
-			3:  // 1st sum
-			begin				
-				int_addr_next = {4'd1, int_lfsr_reg[3:0]};
-
-				// set read addr for 3rd pipeline
-				int_chan_next = 2'd2;
-
-				// prepare registers for 2nd sum	
-				acc_data_next[0] = int_data_reg[2];
-				acc_data_next[1] = int_data_reg[3];
-				acc_data_next[2] = int_data_reg[4];
-				acc_data_next[3] = int_data_reg[5];
-
-				// register 1st sum
-				int_data_next[0] = acc_data_wire[1];
-				int_data_next[1] = acc_data_wire[2];
-				int_data_next[2] = acc_data_wire[3];
-
-				int_case_next = 3'd4;
-			end
-			4: // 2nd sum
-			begin
-				int_addr_next = {4'd2, int_lfsr_reg[3:0]};
-
-				// set read addr for 4th pipeline
-				int_chan_next = 2'd3;
-
-				// prepare registers for 3rd sum	
-				acc_data_next[0] = int_data_reg[5];
-				acc_data_next[1] = int_data_reg[6];
-				acc_data_next[2] = int_data_reg[7];
-				acc_data_next[3] = int_data_reg[8];
-
-				// register 2nd sum
-				int_data_next[3] = acc_data_wire[1];
-				int_data_next[4] = acc_data_wire[2];
-				int_data_next[5] = acc_data_wire[3];
-				
-				int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
-
-				int_case_next = 3'd5;
-			end
-			5:  // 3rd sum
-			begin				
-				int_flag_next = 1'b1;
-
-				int_addr_next = {4'd3, int_lfsr_reg[4:1]};
-
-				// set read addr for 1st pipeline
-				int_chan_next = 2'd0;
-
-				// prepare registers for 4th sum	
-				acc_data_next[0] = int_data_reg[8];
-				acc_data_next[1] = int_data_reg[9];
-				acc_data_next[2] = int_data_reg[10];
-				acc_data_next[3] = int_data_reg[11];
-
-				// register 3rd sum
-				int_data_next[6] = acc_data_wire[1];
-				int_data_next[7] = acc_data_wire[2];
-				int_data_next[8] = acc_data_wire[3];
-				
-				// register 4th output
-				int_data_next[12] = int_data_reg[11];
-
-				int_case_next = 3'd2;
-			end
-			default:
-			begin
-				int_case_next = 3'd0;
-			end
-		endcase
-	end
-
-	assign out_data = int_data_reg[5];
-	assign out_data2 = int_data_reg[8];
-	assign out_data3 = int_data_reg[12];
-
-endmodule
Index: unk/3DEES/cic_pipeline.v
===================================================================
--- /trunk/3DEES/cic_pipeline.v	(revision 178)
+++ 	(revision )
@@ -1,104 +1,0 @@
-module cic_pipeline
-	#(
-		parameter	width	=	192
-	)
-	(
-		input	wire				clock,
-		input	wire	[width-1:0]	data,
-		input	wire	[7:0]		rdaddress_a,
-		input	wire	[7:0]		rdaddress_b,
-		input	wire	[7:0]		wraddress,
-		input	wire				wren,
-		output	wire	[width-1:0]	qa,
-		output	wire	[width-1:0]	qb
-	);
-	
-	altsyncram #(
-		.address_aclr_b("NONE"),
-		.address_reg_b("CLOCK0"),
-		.clock_enable_input_a("BYPASS"),
-		.clock_enable_input_b("BYPASS"),
-		.clock_enable_output_b("BYPASS"),
-		.intended_device_family("Cyclone III"),
-		.lpm_type("altsyncram"),
-		.numwords_a(256),
-		.numwords_b(256),
-		.operation_mode("DUAL_PORT"),
-		.outdata_aclr_b("NONE"),
-		.outdata_reg_b("CLOCK0"),
-		.power_up_uninitialized("FALSE"),
-		.read_during_write_mode_mixed_ports("DONT_CARE"),
-		.widthad_a(8),
-		.widthad_b(8),
-		.width_a(width),
-		.width_b(width),
-		.width_byteena_a(1)) ram_unit_a(
-		.wren_a(wren),
-		.clock0(clock),
-		.address_a(wraddress),
-		.address_b(rdaddress_a),
-		.data_a(data),
-		.q_b(qa),
-		.aclr0(1'b0),
-		.aclr1(1'b0),
-		.addressstall_a(1'b0),
-		.addressstall_b(1'b0),
-		.byteena_a(1'b1),
-		.byteena_b(1'b1),
-		.clock1(1'b1),
-		.clocken0(1'b1),
-		.clocken1(1'b1),
-		.clocken2(1'b1),
-		.clocken3(1'b1),
-		.data_b({width{1'b1}}),
-		.eccstatus(),
-		.q_a(),
-		.rden_a(1'b1),
-		.rden_b(1'b1),
-		.wren_b(1'b0));
-
-	altsyncram #(
-		.address_aclr_b("NONE"),
-		.address_reg_b("CLOCK0"),
-		.clock_enable_input_a("BYPASS"),
-		.clock_enable_input_b("BYPASS"),
-		.clock_enable_output_b("BYPASS"),
-		.intended_device_family("Cyclone III"),
-		.lpm_type("altsyncram"),
-		.numwords_a(256),
-		.numwords_b(256),
-		.operation_mode("DUAL_PORT"),
-		.outdata_aclr_b("NONE"),
-		.outdata_reg_b("CLOCK0"),
-		.power_up_uninitialized("FALSE"),
-		.read_during_write_mode_mixed_ports("DONT_CARE"),
-		.widthad_a(8),
-		.widthad_b(8),
-		.width_a(width),
-		.width_b(width),
-		.width_byteena_a(1)) ram_unit_b(
-		.wren_a(wren),
-		.clock0(clock),
-		.address_a(wraddress),
-		.address_b(rdaddress_b),
-		.data_a(data),
-		.q_b(qb),
-		.aclr0(1'b0),
-		.aclr1(1'b0),
-		.addressstall_a(1'b0),
-		.addressstall_b(1'b0),
-		.byteena_a(1'b1),
-		.byteena_b(1'b1),
-		.clock1(1'b1),
-		.clocken0(1'b1),
-		.clocken1(1'b1),
-		.clocken2(1'b1),
-		.clocken3(1'b1),
-		.data_b({width{1'b1}}),
-		.eccstatus(),
-		.q_a(),
-		.rden_a(1'b1),
-		.rden_b(1'b1),
-		.wren_b(1'b0));
-
-endmodule
Index: unk/3DEES/uwt_bior31.v
===================================================================
--- /trunk/3DEES/uwt_bior31.v	(revision 178)
+++ 	(revision )
@@ -1,111 +1,0 @@
-module uwt_bior31
-	#(
-		parameter	level	=	1, // transform level
-		parameter	width	=	12 // bit width of the input data (unsigned)
-
-	)
-	(
-		input	wire					clock, frame, reset,
-		input	wire	[width-1:0]		inp_data,
-		output	wire	[widthr-1:0]	out_data,
-		output	wire	[1:0]			out_flag
-	);
-
-	localparam	widthr = width + 3;
-
-	localparam	index1 = 1 << (level - 1);
-	localparam	index2 = 2 << (level - 1);
-	localparam	index3 = 3 << (level - 1);
-	
-	// Tapped delay line
-	reg		[width-1:0]		tap_data_reg [index3:0], tap_data_next [index3:0];
-	
-	wire	[1:0]			int_comp_wire;
-	reg		[1:0]			int_comp_reg, int_comp_next;
-
-	reg		[1:0]			out_flag_reg, out_flag_next;
-	
-	wire	[widthr-1:0]	add_data_wire [1:0];
-	reg		[widthr-1:0]	add_data_reg [1:0], add_data_next [1:0];
-
-	reg		[widthr-1:0]	out_data_reg, out_data_next;
-
-	integer i;
-	
-	assign add_data_wire[0] = tap_data_reg[index3] + {tap_data_reg[index2][width-2:0], 1'b0} + tap_data_reg[index2];
-	assign add_data_wire[1] = {tap_data_reg[index1][width-2:0], 1'b0} + tap_data_reg[index1] + tap_data_reg[0];
-	assign int_comp_wire[0] = (add_data_reg[0] > add_data_reg[1]);
-	assign int_comp_wire[1] = (add_data_reg[0] < add_data_reg[1]);
-
-	always @(posedge clock)
-	begin
-		if (reset)
-		begin
-			add_data_reg[0] <= {(widthr){1'b0}};
-			add_data_reg[1] <= {(widthr){1'b0}};
-			out_data_reg <= {(widthr){1'b0}};
-			int_comp_reg <= 2'd0;
-			out_flag_reg <= 2'd0;
-
-			for(i = 0; i <= index3; i = i + 1)
-			begin
-				tap_data_reg[i] <= {(width){1'b0}};
-			end
-		end
-		else
-		begin
-			add_data_reg[0] <= add_data_next[0];
-			add_data_reg[1] <= add_data_next[1];
-			out_data_reg <= out_data_next;
-			int_comp_reg <= int_comp_next;
-			out_flag_reg <= out_flag_next;
-
-			for(i = 0; i <= index3; i = i + 1)
-			begin
-				tap_data_reg[i] <= tap_data_next[i];
-			end			
-		end
-	end
-	
-	always @*
-	begin
-		add_data_next[0] = add_data_reg[0];
-		add_data_next[1] = add_data_reg[1];
-		out_data_next = out_data_reg;
-		int_comp_next = int_comp_reg;
-		out_flag_next = out_flag_reg;
-
-		for(i = 0; i <= index3; i = i + 1)
-		begin
-			tap_data_next[i] = tap_data_reg[i];
-		end
-
-		if (frame)
-		begin		
-			// Tapped delay line: shift one
-			for(i = 0; i < index3; i = i + 1)
-			begin
-				tap_data_next[i+1] = tap_data_reg[i];
-			end
-			
-			// Input in register 0
-			tap_data_next[0] = inp_data;
-
-			add_data_next[0] = add_data_wire[0];
-			add_data_next[1] = add_data_wire[1];
-			
-			out_data_next = add_data_next[0] + add_data_next[1];
-	
-			int_comp_next = int_comp_wire;
-			out_flag_next[0] = (~int_comp_reg[0]) & (int_comp_wire[0]);
-			out_flag_next[1] = (~int_comp_reg[1]) & (int_comp_wire[1]);
-
-		end
-
-	end
-
-	// output logic
-	assign	out_data = out_data_reg;
-	assign	out_flag = out_flag_reg;
-
-endmodule