Index: trunk/3DEES/Paella.dpf
===================================================================
--- trunk/3DEES/Paella.dpf (revision 177)
+++ trunk/3DEES/Paella.dpf (revision 178)
@@ -27,11 +27,11 @@
+
+
+
+
-
-
-
-
Index: trunk/3DEES/Paella.qsf
===================================================================
--- trunk/3DEES/Paella.qsf (revision 177)
+++ trunk/3DEES/Paella.qsf (revision 178)
@@ -248,4 +248,5 @@
set_global_assignment -name MISC_FILE "D:/altera/MultiChannelUSB/Paella.dpf"
+
set_global_assignment -name VERILOG_FILE Paella.v
set_global_assignment -name VERILOG_FILE adc_lvds.v
@@ -258,4 +259,5 @@
set_global_assignment -name VERILOG_FILE amplitude.v
set_global_assignment -name VERILOG_FILE deconv.v
+set_global_assignment -name VERILOG_FILE shift.v
set_global_assignment -name VERILOG_FILE delay.v
set_global_assignment -name VERILOG_FILE coincidence.v
@@ -272,9 +274,10 @@
set_global_assignment -name MIF_FILE test.mif
set_global_assignment -name VERILOG_FILE average.v
-set_global_assignment -name VERILOG_FILE extrema.v
set_global_assignment -name VERILOG_FILE filter.v
set_global_assignment -name VERILOG_FILE new_filter.v
set_global_assignment -name VERILOG_FILE clip.v
set_global_assignment -name VERILOG_FILE pwm.v
-
+set_global_assignment -name MISC_FILE "D:/altera/3DEES-6ch/Paella.dpf"
+set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id "100 MHz Clock"
+set_instance_assignment -name CLOCK_SETTINGS "100 MHz Clock" -to CLK_100MHz
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: trunk/3DEES/Paella.v
===================================================================
--- trunk/3DEES/Paella.v (revision 177)
+++ trunk/3DEES/Paella.v (revision 178)
@@ -34,5 +34,5 @@
);
- localparam N = 12;
+ localparam N = 6;
// Turn output ports off
@@ -83,4 +83,12 @@
);
+/*
+ reg [31:0] led_counter;
+ always @(posedge CLK_50MHz)
+ begin
+ led_counter = led_counter + 32'd1;
+ end
+ assign LED = led_counter[28];
+*/
wire [11:0] osc_mux_data [4:0];
@@ -88,13 +96,13 @@
wire trg_flag;
- wire [2:0] coi_data;
- wire coi_flag;
-
wire [4*12-1:0] int_mux_data [N-1:0];
- wire amp_flag [N-1:0];
- wire [11:0] amp_data [N-1:0];
-
- wire cnt_good [N-1:0];
+ wire [1:0] amp_flag [3*N-1:0];
+ wire [12:0] amp_data [3*N-1:0];
+
+ wire [1:0] amp_mux_flag [2:0];
+ wire [11:0] amp_mux_data [2:0];
+
+ wire cnt_good [3:0];
wire [15:0] cnt_bits_wire;
@@ -105,14 +113,23 @@
wire [11:0] tst_data;
- wire [11:0] cmp_data;
- wire [11:0] del_data;
-
- wire [20:0] cic_data [N-1:0];
+ wire [3:0] cmp_data;
+ wire [1:0] del_data;
+
+ wire [19:0] cic_data [N-1:0];
wire [11:0] dec_data [N-1:0];
- wire [11:0] clp_data [N-1:0];
- wire [11:0] tmp_data [1:0];
+ wire [12:0] clp_data [N-1:0];
+ wire [11:0] tmp_data;
+
wire i2c_reset;
+
+ assign tmp_data = 12'h000;
+ assign sys_clock = CLK_100MHz;
+/*
+ sys_pll sys_pll_unit(
+ .inclk0(CLK_100MHz),
+ .c0(sys_clock));
+*/
/*
sys_pll sys_pll_unit(
@@ -124,36 +141,22 @@
wire ADC_DCO, ADC_FCO;
+
test test_unit(
.clock(ADC_FCO),
.data(tst_data));
+*/
adc_lvds #(
- .size(3),
+ .size(6),
.width(12)) adc_lvds_unit (
.clock(sys_clock),
.lvds_dco(ADC_DCO),
.lvds_fco(ADC_FCO),
- .lvds_d(36'd0),
- .test(tst_data),
- .trig(12'd0),
- .adc_frame(sys_frame),
- .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
-*/
- sys_pll sys_pll_unit(
- .inclk0(CLK_100MHz),
- .c0(sys_clock));
-
- adc_lvds #(
- .size(6),
- .width(24)) adc_lvds_unit (
- .clock(sys_clock),
- .lvds_dco(ADC_DCO),
- .lvds_fco(ADC_FCO),
- .lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}),
+ .lvds_d(ADC_D),
+// .test(tst_data),
.adc_frame(sys_frame),
.adc_data({
- adc_data[11], adc_data[10], adc_data[9], adc_data[8],
- adc_data[7], adc_data[6], adc_data[5], adc_data[4],
- adc_data[3], adc_data[2], adc_data[1], adc_data[0]}));
+ adc_data[5], adc_data[4], adc_data[3],
+ adc_data[2], adc_data[1], adc_data[0]}));
wire [15:0] cfg_bits [63:0];
@@ -174,5 +177,5 @@
wire mrg_bus_busy;
- wire [12*16-1:0] int_bus_miso;
+ wire [11*16-1:0] int_bus_miso;
genvar j;
@@ -197,10 +200,10 @@
generate
- for (j = 0; j < 12; j = j + 1)
+ for (j = 0; j < 6; j = j + 1)
begin : MUX_DATA
assign int_mux_data[j] = {
- amp_data[j],
- clp_data[j],
- cic_data[j][19:8],
+ {4'd0, amp_flag[j][0], 7'd0},
+ amp_data[j][11:0],
+ clp_data[j][11:0],
sys_data[j]};
end
@@ -210,13 +213,12 @@
lpm_mux #(
- .lpm_size(4*12),
+ .lpm_size(4*6),
.lpm_type("LPM_MUX"),
.lpm_width(12),
- .lpm_widths(6)) trg_mux_unit (
- .sel(cfg_bits[4][13:8]),
+ .lpm_widths(5)) trg_mux_unit (
+ .sel(cfg_bits[4][12:8]),
.data({
- int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
- int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
- int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ int_mux_data[5], int_mux_data[4], int_mux_data[3],
+ int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
.result(trg_mux_data));
@@ -226,13 +228,12 @@
lpm_mux #(
- .lpm_size(4*12),
+ .lpm_size(4*6),
.lpm_type("LPM_MUX"),
.lpm_width(12),
- .lpm_widths(6)) osc_mux_unit (
- .sel(cfg_mux_selector[j*8+5:j*8]),
+ .lpm_widths(5)) osc_mux_unit (
+ .sel(cfg_mux_selector[j*8+4:j*8]),
.data({
- int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
- int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
- int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ int_mux_data[5], int_mux_data[4], int_mux_data[3],
+ int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
.result(osc_mux_data[j]));
end
@@ -264,53 +265,66 @@
.bus_busy(bus_busy[1]));
- new_filter #(.size(12), .width(12)) filter_unit (
+ filter #(.size(6), .width(12)) filter_unit (
.clock(sys_clock),
.frame(sys_frame),
.reset(1'b0),
- .inp_data({
- sys_data[11], sys_data[10], sys_data[9], sys_data[08],
- sys_data[7], sys_data[6], sys_data[5], sys_data[4],
- sys_data[3], sys_data[2], sys_data[1], sys_data[0]}),
- .out_data({
- cic_data[11], cic_data[10], cic_data[9], cic_data[8],
- cic_data[7], cic_data[6], cic_data[5], cic_data[4],
- cic_data[3], cic_data[2], cic_data[1], cic_data[0]}));
-
- generate
- for (j = 0; j < 3; j = j + 1)
+ .inp_data({sys_data[5], sys_data[4], sys_data[3],
+ sys_data[2], sys_data[1], sys_data[0]}),
+ .out_data({cic_data[5], cic_data[4], cic_data[3],
+ cic_data[2], cic_data[1], cic_data[0]}));
+/*
+ new_filter #(.size(6), .width(12)) filter_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .inp_data({sys_data[5], sys_data[4], sys_data[3],
+ sys_data[2], sys_data[1], sys_data[0]}),
+ .out_data({cic_data[5], cic_data[4], cic_data[3],
+ cic_data[2], cic_data[1], cic_data[0]}));
+*/
+
+ generate
+ for (j = 0; j < 2; j = j + 1)
begin : DECONV_CHAIN
- clip #(.shift(22), .width(20), .widthr(12)) clip_unit (
+ clip #(.shift(22), .width(19), .widthr(12)) clip_unit (
.clock(sys_clock),
.frame(sys_frame),
.reset(1'b0),
-// .del_data({6'd14, 6'd14, 6'd14, 6'd14}),
- .del_data({cfg_bits[39+8*j][5:0], cfg_bits[37+8*j][5:0], cfg_bits[35+8*j][5:0], cfg_bits[33+8*j][5:0]}),
- .amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
-// .tau_data({16'd17193, 16'd17193, 16'd17193, 16'd17193}), /* exp(-14/1125)*1024*17 */
- .tau_data({cfg_bits[38+8*j], cfg_bits[36+8*j], cfg_bits[34+8*j], cfg_bits[32+8*j]}),
+ .del_data({6'd0, 6'd32, 6'd32, 6'd32}),
+// .del_data({6'd0, cfg_bits[37+6*j][5:0], cfg_bits[35+6*j][5:0], cfg_bits[33+6*j][5:0]}),
+ .amp_data({6'd0, 6'd20, 6'd20, 6'd20}),
+ .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}),
+// exp(-32/1000)*1024*20
+// .tau_data({16'd0, cfg_bits[36+6*j], cfg_bits[34+6*j], cfg_bits[32+6*j]}),
.inp_data({
- cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
- cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
+ 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}),
.out_data({
- clp_data[j*4+3], clp_data[j*4+2],
- clp_data[j*4+1], clp_data[j*4+0]}));
-
- end
- endgenerate
-
- generate
- for (j = 0; j < 12; j = j + 1)
+ tmp_data, clp_data[j*3+2], clp_data[j*3+1], clp_data[j*3+0]}));
+
+ end
+ endgenerate
+
+ generate
+ for (j = 0; j < 6; j = j + 1)
begin : MCA_CHAIN
-
- assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
-
- amplitude #(.width(12)) amplitude_unit_2 (
+/*
+ shift #(.shift(11), .width(19), .widthr(13)) shift_unit (
.clock(sys_clock),
.frame(sys_frame),
.reset(1'b0),
- .cfg_data({1'b0, 12'd0, 12'd5}),
-// .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
-// .inp_data(dec_data[j]),
+ .amp_data(6'd21),
+ .inp_data(cic_data[j][18:0]),
+ .out_data(clp_data[j]));
+*/
+ assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+
+ amplitude #(.width(13)) amplitude_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .min_data({1'b0, cfg_bits[7][11:0]}),
+ .max_data(13'd4095),
+// .cfg_data(cfg_bits[6+2*j][11:0]),
.inp_data(clp_data[j]),
.out_flag(amp_flag[j]),
@@ -323,10 +337,6 @@
.frame(sys_frame),
.reset(cfg_bits[0][5]),
- .hst_good((amp_flag[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
+ .hst_good((amp_flag[0][1]) & (cnt_good[0]) & (cfg_bits[13][1])),
.hst_data(amp_data[0]),
-/*
- .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
- .hst_data(amp_data[j]),
-*/
.bus_ssel(bus_ssel[2]),
.bus_wren(bus_wren),
@@ -338,6 +348,6 @@
counter hst_counter_unit (
.clock(sys_clock),
-// .frame((sys_frame) & (~ana_dead[0])),
- .frame(sys_frame),
+ .frame((sys_frame) & (~amp_flag[0][1])),
+// .frame(sys_frame),
.reset(cfg_bits[0][8]),
.setup(cfg_bits[13][0]),
@@ -395,5 +405,5 @@
lpm_mux #(
- .lpm_size(12),
+ .lpm_size(11),
.lpm_type("LPM_MUX"),
.lpm_width(16),
Index: trunk/3DEES/adc_lvds.v
===================================================================
--- trunk/3DEES/adc_lvds.v (revision 177)
+++ trunk/3DEES/adc_lvds.v (revision 178)
@@ -4,6 +4,6 @@
module adc_lvds
#(
- parameter size = 8, // number of channels
- parameter width = 24 // channel resolution
+ parameter size = 3, // number of channels
+ parameter width = 12 // channel resolution
)
(
@@ -13,4 +13,5 @@
input wire lvds_fco,
input wire [size-1:0] lvds_d,
+ input wire [11:0] test,
output wire adc_frame,
@@ -20,4 +21,5 @@
localparam width2 = width + 2;
+
reg state, int_rdreq, adc_frame_reg;
wire int_wrfull, int_rdempty;
@@ -47,8 +49,16 @@
// LSB first
// assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
- assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
- assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
+
+// assign int_fifo_wire[j*width+width-1:j*width] = test;
+
+ assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_reg[j*width2+width2-3:j*width2], int_data_p[j], int_data_n[j]};
+ assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+2];
+// assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+8];
+
+// assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
+// assign [j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
end
endgenerate
+
dcfifo #(
Index: trunk/3DEES/amplitude.v
===================================================================
--- trunk/3DEES/amplitude.v (revision 177)
+++ trunk/3DEES/amplitude.v (revision 178)
@@ -5,8 +5,9 @@
(
input wire clock, frame, reset,
- input wire [width-1:0] cfg_data,
+ input wire [width-1:0] min_data,
+ input wire [width-1:0] max_data,
input wire [width-1:0] inp_data,
output wire [width-1:0] out_data,
- output wire out_flag
+ output wire [1:0] out_flag
);
@@ -20,4 +21,6 @@
wire int_comp_wire;
reg int_comp_reg, int_comp_next;
+
+ reg [5:0] int_cntr_reg, int_cntr_next;
assign int_comp_wire = (inp_data_reg[1] < inp_data);
@@ -35,4 +38,5 @@
int_flag_reg <= 1'b0;
int_comp_reg <= 1'b0;
+ int_cntr_reg <= 6'd0;
end
else
@@ -46,4 +50,5 @@
int_flag_reg <= int_flag_next;
int_comp_reg <= int_comp_next;
+ int_cntr_reg <= int_cntr_next;
end
end
@@ -59,4 +64,5 @@
int_flag_next = int_flag_reg;
int_comp_next = int_comp_reg;
+ int_cntr_next = int_cntr_reg;
case (int_case_reg)
@@ -71,10 +77,10 @@
out_flag_next = 1'b0;
// minimum
- if ((~int_comp_reg) & (int_comp_wire))
+ if ((~int_comp_reg) & (int_comp_wire) & int_cntr_reg[5])
begin
int_mini_next = inp_data_reg[0];
int_flag_next = 1'b1;
end
- // maximum
+ // maximum after minimum
else if ((int_comp_reg) & (~int_comp_wire) & (int_flag_reg))
begin
@@ -83,4 +89,8 @@
int_case_next = 1'b1;
end
+ else if (~int_cntr_reg[5])
+ begin
+ int_cntr_next = int_cntr_reg + 6'd1;
+ end
end
end
@@ -88,5 +98,10 @@
1:
begin
- out_flag_next = (out_data_reg >= cfg_data);
+ if (out_data_reg > min_data)
+ begin
+ int_cntr_next = 6'b0;
+// out_flag_next = 1'b1;
+ out_flag_next = (inp_data_reg[1] < max_data);
+ end
int_case_next = 1'b0;
end
@@ -96,5 +111,5 @@
assign out_data = out_data_reg;
- assign out_flag = out_flag_reg;
+ assign out_flag = {~int_cntr_reg[5], out_flag_reg};
endmodule
Index: trunk/3DEES/clip.v
===================================================================
--- trunk/3DEES/clip.v (revision 177)
+++ trunk/3DEES/clip.v (revision 178)
@@ -31,4 +31,5 @@
wire [widthr-1:0] out_data_wire;
+ reg [width3-1:0] add_data_reg [4:0], add_data_next [4:0];
wire [width3-1:0] add_data_wire;
@@ -104,7 +105,7 @@
- {2'b0, mul_data_wire1};
- assign out_data_wire = add_data_wire[width3-1] ? {(widthr){1'b0}} :
- add_data_wire[shift+widthr-1:shift]
- + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]};
+ assign out_data_wire = add_data_reg[0][width3-1] ? {(widthr){1'b0}} :
+ add_data_reg[0][shift+widthr-1:shift]
+ + {{(widthr-1){add_data_reg[0][width3-1]}}, add_data_reg[0][shift-1]};
@@ -172,4 +173,5 @@
begin
out_data_reg[i] <= {(widthr){1'b0}};
+ add_data_reg[i] <= {(width3){1'b0}};
end
end
@@ -191,4 +193,5 @@
begin
out_data_reg[i] <= out_data_next[i];
+ add_data_reg[i] <= add_data_next[i];
end
end
@@ -212,4 +215,5 @@
begin
out_data_next[i] = out_data_reg[i];
+ add_data_next[i] = add_data_reg[i];
end
@@ -230,4 +234,5 @@
begin
out_data_next[i] = {(widthr){1'b0}};
+ add_data_next[i] = {(width3){1'b0}};
end
@@ -264,4 +269,6 @@
// prepare registers for 1st sum
inp_data_next[0] = inp_data_wire[0];
+ // prepare registers for 2nd shift
+ add_data_next[0] = add_data_reg[2];
tau_data_next = tau_data_wire[0];
@@ -274,5 +281,6 @@
int_addr_next[5:0] = del_addr_reg;
// register 1st product
- out_data_next[0] = out_data_wire;
+ add_data_next[1] = add_data_wire;
+ out_data_next[1] = out_data_wire;
end
end
@@ -286,4 +294,6 @@
// prepare registers for 2nd sum
inp_data_next[0] = inp_data_reg[1];
+ // prepare registers for 3rd shift
+ add_data_next[0] = add_data_reg[3];
tau_data_next = tau_data_wire[1];
@@ -291,5 +301,6 @@
// register 2nd product
- out_data_next[1] = out_data_wire;
+ add_data_next[2] = add_data_wire;
+ out_data_next[2] = out_data_wire;
int_case_next = 3'd4;
@@ -304,4 +315,6 @@
// prepare registers for 3rd sum
inp_data_next[0] = inp_data_reg[2];
+ // prepare registers for 4th shift
+ add_data_next[0] = add_data_reg[4];
tau_data_next = tau_data_wire[2];
@@ -309,5 +322,6 @@
// register 3rd product
- out_data_next[2] = out_data_wire;
+ add_data_next[3] = add_data_wire;
+ out_data_next[3] = out_data_wire;
del_addr_next = del_addr_reg + 6'd1;
@@ -326,4 +340,6 @@
// prepare registers for 4th sum
inp_data_next[0] = inp_data_reg[3];
+ // prepare registers for 1st shift
+ add_data_next[0] = add_data_reg[1];
tau_data_next = tau_data_wire[3];
@@ -331,8 +347,9 @@
// register 4th product
- out_data_next[3] = out_data_wire;
+ add_data_next[4] = add_data_wire;
+ out_data_next[4] = out_data_wire;
// register 4th output
- out_data_next[4] = out_data_reg[0];
+ out_data_next[0] = out_data_reg[1];
int_case_next = 3'd2;
@@ -345,5 +362,5 @@
end
- assign out_data = {out_data_reg[3], out_data_reg[2], out_data_reg[1], out_data_reg[4]};
+ assign out_data = {out_data_reg[4], out_data_reg[3], out_data_reg[2], out_data_reg[0]};
endmodule
Index: trunk/3DEES/histogram16.v
===================================================================
--- trunk/3DEES/histogram16.v (revision 177)
+++ trunk/3DEES/histogram16.v (revision 178)
@@ -38,6 +38,6 @@
.intended_device_family("Cyclone III"),
.lpm_type("altsyncram"),
- .numwords_a(16384),
- .numwords_b(16384),
+ .numwords_a(10000),
+ .numwords_b(10000),
.operation_mode("BIDIR_DUAL_PORT"),
.outdata_aclr_a("NONE"),
Index: trunk/3DEES/shift.v
===================================================================
--- trunk/3DEES/shift.v (revision 178)
+++ trunk/3DEES/shift.v (revision 178)
@@ -0,0 +1,58 @@
+module shift
+ #(
+ parameter shift = 24, // right shift of the result
+ parameter width = 27, // bit width of the input data
+ parameter widthr = 12 // bit width of the output data
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [5:0] amp_data,
+ input wire [width-1:0] inp_data,
+ output wire [widthr-1:0] out_data
+ );
+
+ localparam widthp = width + 6;
+
+ reg [5:0] amp_data_reg;
+ reg [width-1:0] inp_data_reg;
+ reg [widthr-1:0] out_data_reg;
+ wire [widthr-1:0] out_data_wire;
+ wire [widthp-1:0] mul_data_wire;
+
+ assign out_data_wire = mul_data_wire[shift+widthr-1:shift]
+ + {{(widthr-1){mul_data_wire[widthp-1]}}, mul_data_wire[shift-1]};
+
+ lpm_mult #(
+ .lpm_hint("MAXIMIZE_SPEED=9"),
+ .lpm_representation("UNSIGNED"),
+ .lpm_type("LPM_MULT"),
+ .lpm_pipeline(3),
+ .lpm_widtha(width),
+ .lpm_widthb(6),
+ .lpm_widthp(widthp)) mult_unit (
+ .clock(clock),
+ .clken(1'b1),
+ .dataa(inp_data_reg),
+ .datab(amp_data_reg),
+ .result(mul_data_wire));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ amp_data_reg <= 6'b0;
+ inp_data_reg <= {(width){1'b0}};
+ out_data_reg <= {(widthr){1'b0}};
+ end
+ else if (frame)
+ begin
+ amp_data_reg <= amp_data;
+ inp_data_reg <= inp_data;
+ out_data_reg <= out_data_wire;
+ end
+ end
+
+
+ assign out_data = out_data_reg;
+
+endmodule
Index: trunk/3DEES/sys_pll.v
===================================================================
--- trunk/3DEES/sys_pll.v (revision 177)
+++ trunk/3DEES/sys_pll.v (revision 178)
@@ -39,18 +39,26 @@
module sys_pll (
inclk0,
- c0);
+ c0,
+ c1,
+ c2);
input inclk0;
output c0;
+ output c1;
+ output c2;
wire [4:0] sub_wire0;
- wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
- wire sub_wire2 = inclk0;
- wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
- .inclk (sub_wire3),
+ .inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
@@ -68,4 +76,6 @@
.fbmimicbidir (),
.fbout (),
+ .fref (),
+ .icdrclk (),
.locked (),
.pfdena (1'b1),
@@ -91,10 +101,18 @@
altpll_component.clk0_divide_by = 10,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 17,
+ altpll_component.clk0_multiply_by = 9,
altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 10,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 6,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 10,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Cyclone III",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
@@ -126,6 +144,6 @@
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_UNUSED",
- altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",