Index: /trunk/3DEES/Paella.cof
===================================================================
--- /trunk/3DEES/Paella.cof (revision 177)
+++ /trunk/3DEES/Paella.cof (revision 177)
@@ -0,0 +1,18 @@
+
+
+ EPCS16
+ EP3C25
+ Paella.jic
+ 1
+ 1
+ 7
+
+ 1
+
+ Paella.sof
+
+
+ 4
+
+
+
Index: /trunk/3DEES/Paella.dpf
===================================================================
--- /trunk/3DEES/Paella.dpf (revision 177)
+++ /trunk/3DEES/Paella.dpf (revision 177)
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: /trunk/3DEES/Paella.qpf
===================================================================
--- /trunk/3DEES/Paella.qpf (revision 177)
+++ /trunk/3DEES/Paella.qpf (revision 177)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "14:14:14 August 28, 2009"
+
+# Revisions
+
+PROJECT_REVISION = "Paella"
Index: /trunk/3DEES/Paella.qsf
===================================================================
--- /trunk/3DEES/Paella.qsf (revision 177)
+++ /trunk/3DEES/Paella.qsf (revision 177)
@@ -0,0 +1,280 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# Paella_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY Paella
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name MISC_FILE Paella.dpf
+set_global_assignment -name MISC_FILE "C:/altera/project_12/Paella.dpf"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name FMAX_REQUIREMENT "240 MHz" -section_id "LVDS Data Clock"
+set_instance_assignment -name CLOCK_SETTINGS "LVDS Data Clock" -to ADC_DCO
+set_global_assignment -name FMAX_REQUIREMENT "20 MHz" -section_id "LVDS Frame Clock"
+set_instance_assignment -name CLOCK_SETTINGS "LVDS Frame Clock" -to ADC_FCO
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id "USB Clock"
+set_instance_assignment -name CLOCK_SETTINGS "USB Clock" -to USB_IFCLK
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 6
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
+set_location_assignment PIN_21 -to LED
+set_location_assignment PIN_33 -to USB_IFCLK
+set_location_assignment PIN_37 -to USB_PA6
+set_location_assignment PIN_38 -to USB_PA4
+set_location_assignment PIN_39 -to USB_PA2
+set_location_assignment PIN_41 -to USB_FLAGB
+set_location_assignment PIN_43 -to USB_FLAGA
+set_location_assignment PIN_44 -to USB_PB[4]
+set_location_assignment PIN_45 -to USB_PB[5]
+set_location_assignment PIN_46 -to USB_PB[6]
+set_location_assignment PIN_49 -to USB_PB[7]
+set_location_assignment PIN_50 -to USB_SLRD
+set_location_assignment PIN_51 -to USB_SLWR
+set_location_assignment PIN_52 -to USB_PB[0]
+set_location_assignment PIN_55 -to USB_PB[1]
+set_location_assignment PIN_56 -to USB_PB[2]
+set_location_assignment PIN_57 -to USB_PB[3]
+set_location_assignment PIN_78 -to PWM[0]
+set_location_assignment PIN_80 -to PWM[1]
+set_location_assignment PIN_81 -to PWM[2]
+set_location_assignment PIN_82 -to PWM[3]
+set_location_assignment PIN_114 -to SPI_SEL[0]
+set_location_assignment PIN_117 -to ADC_RST
+set_location_assignment PIN_118 -to SPI_CLK
+set_location_assignment PIN_119 -to SPI_SDO
+set_location_assignment PIN_120 -to SPI_SEL[1]
+set_location_assignment PIN_137 -to "ADC_D[0](n)"
+set_location_assignment PIN_139 -to ADC_D[0]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0]
+set_location_assignment PIN_142 -to "ADC_D[1](n)"
+set_location_assignment PIN_143 -to ADC_D[1]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1]
+set_location_assignment PIN_144 -to "ADC_D[2](n)"
+set_location_assignment PIN_145 -to ADC_D[2]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2]
+set_location_assignment PIN_147 -to "ADC_D[3](n)"
+set_location_assignment PIN_148 -to ADC_D[3]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[3]
+set_location_assignment PIN_149 -to "ADC_DCO(n)"
+set_location_assignment PIN_150 -to ADC_DCO
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_DCO
+set_location_assignment PIN_151 -to "ADC_FCO(n)"
+set_location_assignment PIN_152 -to ADC_FCO
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
+set_location_assignment PIN_159 -to "ADC_D[4](n)"
+set_location_assignment PIN_160 -to ADC_D[4]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[4]
+set_location_assignment PIN_162 -to "ADC_D[5](n)"
+set_location_assignment PIN_164 -to ADC_D[5]
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[5]
+set_location_assignment PIN_181 -to RAM_ADDR[12]
+set_location_assignment PIN_182 -to RAM_DQAP
+set_location_assignment PIN_183 -to RAM_DQA[0]
+set_location_assignment PIN_184 -to RAM_DQA[1]
+set_location_assignment PIN_185 -to RAM_DQA[2]
+set_location_assignment PIN_186 -to RAM_DQA[3]
+set_location_assignment PIN_187 -to RAM_DQA[4]
+set_location_assignment PIN_188 -to RAM_DQA[5]
+set_location_assignment PIN_189 -to RAM_DQA[6]
+set_location_assignment PIN_194 -to RAM_DQA[7]
+set_location_assignment PIN_195 -to RAM_ADDR[13]
+set_location_assignment PIN_196 -to RAM_ADDR[14]
+set_location_assignment PIN_197 -to RAM_ADDR[15]
+set_location_assignment PIN_200 -to RAM_ADDR[16]
+set_location_assignment PIN_201 -to RAM_ADDR[17]
+set_location_assignment PIN_202 -to RAM_ADDR[18]
+set_location_assignment PIN_203 -to RAM_ADDR[19]
+set_location_assignment PIN_207 -to RAM_ADDR[20]
+set_location_assignment PIN_210 -to CLK_100MHz
+set_location_assignment PIN_214 -to RAM_ADDR[21]
+set_location_assignment PIN_216 -to RAM_ADDR[0]
+set_location_assignment PIN_217 -to RAM_ADDR[1]
+set_location_assignment PIN_218 -to RAM_ADDR[2]
+set_location_assignment PIN_219 -to RAM_ADDR[3]
+set_location_assignment PIN_221 -to RAM_ADDR[4]
+set_location_assignment PIN_223 -to RAM_ADDR[5]
+set_location_assignment PIN_224 -to RAM_DQBP
+set_location_assignment PIN_226 -to RAM_DQB[0]
+set_location_assignment PIN_230 -to RAM_DQB[1]
+set_location_assignment PIN_231 -to RAM_DQB[2]
+set_location_assignment PIN_232 -to RAM_DQB[3]
+set_location_assignment PIN_233 -to RAM_DQB[4]
+set_location_assignment PIN_234 -to RAM_DQB[5]
+set_location_assignment PIN_235 -to RAM_DQB[6]
+set_location_assignment PIN_236 -to RAM_DQB[7]
+set_location_assignment PIN_237 -to RAM_ADDR[6]
+set_location_assignment PIN_238 -to RAM_ADDR[7]
+set_location_assignment PIN_239 -to RAM_CLK
+set_location_assignment PIN_240 -to RAM_WE
+set_location_assignment PIN_4 -to RAM_ADDR[8]
+set_location_assignment PIN_5 -to RAM_ADDR[9]
+set_location_assignment PIN_6 -to RAM_ADDR[10]
+set_location_assignment PIN_9 -to RAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_100MHz
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SEL[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SEL[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7]
+set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PWM[0]
+set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PWM[1]
+set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PWM[2]
+set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PWM[3]
+
+set_global_assignment -name MISC_FILE "D:/altera/MultiChannelUSB/Paella.dpf"
+set_global_assignment -name VERILOG_FILE Paella.v
+set_global_assignment -name VERILOG_FILE adc_lvds.v
+set_global_assignment -name VERILOG_FILE cic_pipeline.v
+set_global_assignment -name VERILOG_FILE cic_filter.v
+set_global_assignment -name VERILOG_FILE uwt_bior31.v
+set_global_assignment -name VERILOG_FILE sys_pll.v
+set_global_assignment -name VERILOG_FILE control.v
+set_global_assignment -name VERILOG_FILE analyser.v
+set_global_assignment -name VERILOG_FILE amplitude.v
+set_global_assignment -name VERILOG_FILE deconv.v
+set_global_assignment -name VERILOG_FILE delay.v
+set_global_assignment -name VERILOG_FILE coincidence.v
+set_global_assignment -name VERILOG_FILE counter.v
+set_global_assignment -name VERILOG_FILE histogram32.v
+set_global_assignment -name VERILOG_FILE histogram16.v
+set_global_assignment -name VERILOG_FILE trigger.v
+set_global_assignment -name VERILOG_FILE oscilloscope.v
+set_global_assignment -name VERILOG_FILE configuration.v
+set_global_assignment -name VERILOG_FILE usb_fifo.v
+set_global_assignment -name VERILOG_FILE i2c_fifo.v
+set_global_assignment -name VERILOG_FILE spi_fifo.v
+set_global_assignment -name VERILOG_FILE test.v
+set_global_assignment -name MIF_FILE test.mif
+set_global_assignment -name VERILOG_FILE average.v
+set_global_assignment -name VERILOG_FILE extrema.v
+set_global_assignment -name VERILOG_FILE filter.v
+set_global_assignment -name VERILOG_FILE new_filter.v
+set_global_assignment -name VERILOG_FILE clip.v
+set_global_assignment -name VERILOG_FILE pwm.v
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: /trunk/3DEES/Paella.v
===================================================================
--- /trunk/3DEES/Paella.v (revision 177)
+++ /trunk/3DEES/Paella.v (revision 177)
@@ -0,0 +1,451 @@
+module Paella
+ (
+ input wire CLK_100MHz,
+ output wire LED,
+
+ input wire ADC_DCO,
+ input wire ADC_FCO,
+ input wire [5:0] ADC_D,
+
+ output wire [3:0] PWM,
+
+ output wire [1:0] SPI_SEL,
+ output wire SPI_SDO,
+ output wire SPI_CLK,
+ output wire ADC_RST,
+
+ output wire USB_SLRD,
+ output wire USB_SLWR,
+ input wire USB_IFCLK,
+ input wire USB_FLAGA, // EMPTY flag for EP6
+ input wire USB_FLAGB, // FULL flag for EP8
+ output wire USB_PA2,
+ output wire USB_PA4,
+ output wire USB_PA6,
+ inout wire [7:0] USB_PB,
+
+ output wire RAM_CLK,
+ output wire RAM_WE,
+ output wire [21:0] RAM_ADDR,
+ inout wire RAM_DQAP,
+ inout wire [7:0] RAM_DQA,
+ inout wire RAM_DQBP,
+ inout wire [7:0] RAM_DQB
+ );
+
+ localparam N = 12;
+
+ // Turn output ports off
+/*
+ assign RAM_CLK = 1'b0;
+ assign RAM_CE1 = 1'b0;
+ assign RAM_WE = 1'b0;
+ assign RAM_ADDR = 20'h00000;
+*/
+ assign ADC_RST = 1'b0;
+
+ assign RAM_CLK = sys_clock;
+
+ assign USB_PA2 = ~usb_rden;
+ assign USB_PA4 = usb_addr;
+ assign USB_PA6 = ~usb_pktend;
+
+ wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
+ wire usb_tx_wrreq, usb_rx_rdreq;
+ wire usb_tx_full, usb_rx_empty;
+ wire [7:0] usb_tx_data, usb_rx_data;
+ wire usb_addr;
+
+ assign USB_SLRD = ~usb_rdreq;
+ assign USB_SLWR = ~usb_wrreq;
+
+ usb_fifo usb_unit
+ (
+ .usb_clock(USB_IFCLK),
+ .usb_data(USB_PB),
+ .usb_full(~USB_FLAGB),
+ .usb_empty(~USB_FLAGA),
+ .usb_wrreq(usb_wrreq),
+ .usb_rdreq(usb_rdreq),
+ .usb_rden(usb_rden),
+ .usb_pktend(usb_pktend),
+ .usb_addr(usb_addr),
+
+ .clock(sys_clock),
+
+ .tx_full(usb_tx_full),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+
+ .rx_empty(usb_rx_empty),
+ .rx_rdreq(usb_rx_rdreq),
+ .rx_q(usb_rx_data)
+ );
+
+ wire [11:0] osc_mux_data [4:0];
+
+ wire [11:0] trg_mux_data;
+ wire trg_flag;
+
+ wire [2:0] coi_data;
+ wire coi_flag;
+
+ wire [4*12-1:0] int_mux_data [N-1:0];
+
+ wire amp_flag [N-1:0];
+ wire [11:0] amp_data [N-1:0];
+
+ wire cnt_good [N-1:0];
+ wire [15:0] cnt_bits_wire;
+
+ wire sys_clock, sys_frame;
+
+ wire [11:0] adc_data [N-1:0];
+ wire [11:0] sys_data [N-1:0];
+ wire [11:0] tst_data;
+
+ wire [11:0] cmp_data;
+ wire [11:0] del_data;
+
+ wire [20:0] cic_data [N-1:0];
+
+ wire [11:0] dec_data [N-1:0];
+ wire [11:0] clp_data [N-1:0];
+ wire [11:0] tmp_data [1:0];
+
+ wire i2c_reset;
+/*
+ sys_pll sys_pll_unit(
+ .inclk0(CLK_100MHz),
+ .c0(sys_clock),
+ .c1(ADC_DCO),
+ .c2(ADC_FCO));
+
+ wire ADC_DCO, ADC_FCO;
+
+ test test_unit(
+ .clock(ADC_FCO),
+ .data(tst_data));
+
+ adc_lvds #(
+ .size(3),
+ .width(12)) adc_lvds_unit (
+ .clock(sys_clock),
+ .lvds_dco(ADC_DCO),
+ .lvds_fco(ADC_FCO),
+ .lvds_d(36'd0),
+ .test(tst_data),
+ .trig(12'd0),
+ .adc_frame(sys_frame),
+ .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
+*/
+ sys_pll sys_pll_unit(
+ .inclk0(CLK_100MHz),
+ .c0(sys_clock));
+
+ adc_lvds #(
+ .size(6),
+ .width(24)) adc_lvds_unit (
+ .clock(sys_clock),
+ .lvds_dco(ADC_DCO),
+ .lvds_fco(ADC_FCO),
+ .lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}),
+ .adc_frame(sys_frame),
+ .adc_data({
+ adc_data[11], adc_data[10], adc_data[9], adc_data[8],
+ adc_data[7], adc_data[6], adc_data[5], adc_data[4],
+ adc_data[3], adc_data[2], adc_data[1], adc_data[0]}));
+
+ wire [15:0] cfg_bits [63:0];
+ wire [1023:0] int_cfg_bits;
+
+ wire [39:0] cfg_mux_selector;
+
+ wire cfg_reset;
+
+ wire [12:0] bus_ssel;
+ wire bus_wren;
+ wire [31:0] bus_addr;
+ wire [15:0] bus_mosi;
+ wire [15:0] bus_miso [10:0];
+ wire [12:0] bus_busy;
+
+ wire [15:0] mrg_bus_miso;
+ wire mrg_bus_busy;
+
+ wire [12*16-1:0] int_bus_miso;
+
+ genvar j;
+
+ generate
+ for (j = 0; j < 64; j = j + 1)
+ begin : CONFIGURATION_OUTPUT
+ assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
+ end
+ endgenerate
+
+ configuration configuration_unit (
+ .clock(sys_clock),
+ .reset(cfg_reset),
+ .bus_ssel(bus_ssel[0]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[5:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[0]),
+ .bus_busy(bus_busy[0]),
+ .cfg_bits(int_cfg_bits));
+
+ generate
+ for (j = 0; j < 12; j = j + 1)
+ begin : MUX_DATA
+ assign int_mux_data[j] = {
+ amp_data[j],
+ clp_data[j],
+ cic_data[j][19:8],
+ sys_data[j]};
+ end
+ endgenerate
+
+ assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
+
+ lpm_mux #(
+ .lpm_size(4*12),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(6)) trg_mux_unit (
+ .sel(cfg_bits[4][13:8]),
+ .data({
+ int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
+ int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
+ int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ .result(trg_mux_data));
+
+ generate
+ for (j = 0; j < 5; j = j + 1)
+ begin : OSC_CHAIN
+
+ lpm_mux #(
+ .lpm_size(4*12),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(6)) osc_mux_unit (
+ .sel(cfg_mux_selector[j*8+5:j*8]),
+ .data({
+ int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
+ int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
+ int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ .result(osc_mux_data[j]));
+ end
+ endgenerate
+
+ trigger trigger_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][0]),
+ .cfg_data(cfg_bits[5][11:0]),
+ .trg_data(trg_mux_data),
+ .trg_flag(trg_flag));
+
+ oscilloscope oscilloscope_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][1]),
+ .cfg_data(cfg_bits[5][12]),
+ .trg_flag(trg_flag),
+ .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+ .ram_wren(RAM_WE),
+ .ram_addr(RAM_ADDR),
+ .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
+ .bus_ssel(bus_ssel[1]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[19:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[1]),
+ .bus_busy(bus_busy[1]));
+
+ new_filter #(.size(12), .width(12)) filter_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .inp_data({
+ sys_data[11], sys_data[10], sys_data[9], sys_data[08],
+ sys_data[7], sys_data[6], sys_data[5], sys_data[4],
+ sys_data[3], sys_data[2], sys_data[1], sys_data[0]}),
+ .out_data({
+ cic_data[11], cic_data[10], cic_data[9], cic_data[8],
+ cic_data[7], cic_data[6], cic_data[5], cic_data[4],
+ cic_data[3], cic_data[2], cic_data[1], cic_data[0]}));
+
+ generate
+ for (j = 0; j < 3; j = j + 1)
+ begin : DECONV_CHAIN
+
+ clip #(.shift(22), .width(20), .widthr(12)) clip_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+// .del_data({6'd14, 6'd14, 6'd14, 6'd14}),
+ .del_data({cfg_bits[39+8*j][5:0], cfg_bits[37+8*j][5:0], cfg_bits[35+8*j][5:0], cfg_bits[33+8*j][5:0]}),
+ .amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
+// .tau_data({16'd17193, 16'd17193, 16'd17193, 16'd17193}), /* exp(-14/1125)*1024*17 */
+ .tau_data({cfg_bits[38+8*j], cfg_bits[36+8*j], cfg_bits[34+8*j], cfg_bits[32+8*j]}),
+ .inp_data({
+ cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
+ cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
+ .out_data({
+ clp_data[j*4+3], clp_data[j*4+2],
+ clp_data[j*4+1], clp_data[j*4+0]}));
+
+ end
+ endgenerate
+
+ generate
+ for (j = 0; j < 12; j = j + 1)
+ begin : MCA_CHAIN
+
+ assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+
+ amplitude #(.width(12)) amplitude_unit_2 (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .cfg_data({1'b0, 12'd0, 12'd5}),
+// .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
+// .inp_data(dec_data[j]),
+ .inp_data(clp_data[j]),
+ .out_flag(amp_flag[j]),
+ .out_data(amp_data[j]));
+ end
+ endgenerate
+
+ histogram32 histogram32_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][5]),
+ .hst_good((amp_flag[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
+ .hst_data(amp_data[0]),
+/*
+ .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
+ .hst_data(amp_data[j]),
+*/
+ .bus_ssel(bus_ssel[2]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[12:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[2]),
+ .bus_busy(bus_busy[2]));
+
+ counter hst_counter_unit (
+ .clock(sys_clock),
+// .frame((sys_frame) & (~ana_dead[0])),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][8]),
+ .setup(cfg_bits[13][0]),
+ .count(cfg_bits[13][1]),
+ .bus_ssel(bus_ssel[5]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[1:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[5]),
+ .bus_busy(bus_busy[5]),
+ .cnt_good(cnt_good[0]));
+
+
+ i2c_fifo i2c_unit(
+ .clock(sys_clock),
+ .reset(i2c_reset),
+/*
+ normal connection
+ .i2c_sda(I2C_SDA),
+ .i2c_scl(I2C_SCL),
+
+ following is a cross wire connection for EPT
+*/
+ .i2c_sda(I2C_SCL),
+ .i2c_scl(I2C_SDA),
+
+ .bus_ssel(bus_ssel[11]),
+ .bus_wren(bus_wren),
+ .bus_mosi(bus_mosi),
+ .bus_busy(bus_busy[11]));
+
+ spi_fifo spi_unit(
+ .clock(sys_clock),
+ .reset(1'b0),
+ .spi_sel(SPI_SEL),
+ .spi_sdo(SPI_SDO),
+ .spi_clk(SPI_CLK),
+
+ .bus_ssel(bus_ssel[12]),
+ .bus_wren(bus_wren),
+ .bus_mosi(bus_mosi),
+ .bus_busy(bus_busy[12]));
+
+ pwm pwm_unit(
+ .clock(sys_clock),
+ .cfg_data({cfg_bits[31], cfg_bits[30], cfg_bits[29]}),
+ .out_data(PWM));
+
+ generate
+ for (j = 0; j < 11; j = j + 1)
+ begin : BUS_OUTPUT
+ assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(12),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(4)) bus_miso_mux_unit (
+ .sel(bus_addr[31:28]),
+ .data(int_bus_miso),
+ .result(mrg_bus_miso));
+
+ lpm_mux #(
+ .lpm_size(13),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(1),
+ .lpm_widths(4)) bus_busy_mux_unit (
+ .sel(bus_addr[31:28]),
+ .data(bus_busy),
+ .result(mrg_bus_busy));
+
+ lpm_decode #(
+ .lpm_decodes(13),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(4)) lpm_decode_unit (
+ .data(bus_addr[31:28]),
+ .eq(bus_ssel));
+
+
+ control control_unit (
+ .clock(sys_clock),
+ .rx_empty(usb_rx_empty),
+ .tx_full(usb_tx_full),
+ .rx_data(usb_rx_data),
+ .rx_rdreq(usb_rx_rdreq),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr),
+ .bus_mosi(bus_mosi),
+ .bus_miso(mrg_bus_miso),
+ .bus_busy(mrg_bus_busy),
+ .led(LED));
+
+/*
+ altserial_flash_loader #(
+ .enable_shared_access("OFF"),
+ .enhanced_mode(1),
+ .intended_device_family("Cyclone III")) sfl_unit (
+ .noe(1'b0),
+ .asmi_access_granted(),
+ .asmi_access_request(),
+ .data0out(),
+ .dclkin(),
+ .scein(),
+ .sdoin());
+*/
+
+endmodule
Index: /trunk/3DEES/UserInterface.tcl
===================================================================
--- /trunk/3DEES/UserInterface.tcl (revision 177)
+++ /trunk/3DEES/UserInterface.tcl (revision 177)
@@ -0,0 +1,2200 @@
+package require XOTcl
+
+package require BLT
+package require swt
+package require usb
+
+package require zlib
+
+wm minsize . 1000 700
+
+namespace eval ::mca {
+ namespace import ::xotcl::*
+
+ namespace import ::blt::vector
+ namespace import ::blt::graph
+ namespace import ::blt::tabnotebook
+
+# -------------------------------------------------------------------------
+
+ variable oscCodes
+ array set oscCodes {
+ 1 {Channel 1}
+ 2 {Channel 2}
+ 3 {Channel 3}
+ 4 {Channel 4}
+ 5 {Channel 5}
+ 6 {Trigger}
+ }
+
+# -------------------------------------------------------------------------
+
+ variable adcCodes
+ array set adcCodes {
+ 1 {ADC 1}
+ 2 {ADC 2}
+ 3 {ADC 3}
+ 4 {ADC 4}
+ 5 {ADC 5}
+ 6 {ADC 6}
+ 7 {ADC 7}
+ 8 {ADC 8}
+ 9 {ADC 9}
+ 10 {ADC 10}
+ 11 {ADC 11}
+ 12 {ADC 12}
+ }
+
+# -------------------------------------------------------------------------
+
+ variable inpCodes
+ array set inpCodes {
+ 0 {r}
+ 1 {f}
+ 2 {d}
+ 3 {c}
+ }
+
+# -------------------------------------------------------------------------
+
+ proc validate {max size value} {
+ if {![regexp {^[0-9]*$} $value]} {
+ return 0
+ } elseif {[regexp {^0[0-9]+$} $value]} {
+ return 0
+ } elseif {$value > $max} {
+ return 0
+ } elseif {[string length $value] > $size} {
+ return 0
+ } else {
+ return 1
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ proc doublevalidate {max value} {
+ if {![regexp {^[0-9]{0,2}\.?[0-9]{0,3}$} $value]} {
+ return 0
+ } elseif {[regexp {^0[0-9]+$} $value]} {
+ return 0
+ } elseif {$value > $max} {
+ return 0
+ } else {
+ return 1
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ proc legendLabel {master row key title} {
+ label ${master}.${key}_label -anchor w -text ${title}
+ label ${master}.${key}_value -width 10 -anchor e -text {}
+
+ grid ${master}.${key}_label -row ${row} -column 1 -sticky w
+ grid ${master}.${key}_value -row ${row} -column 2 -sticky ew
+ }
+
+# -------------------------------------------------------------------------
+
+ proc legendButton {master row key title var bg {fg black}} {
+ checkbutton ${master}.${key}_check -variable $var
+ label ${master}.${key}_label -anchor w -text ${title} -bg ${bg} -fg $fg
+ label ${master}.${key}_value -width 10 -anchor e -text {} -bg ${bg} -fg $fg
+
+ grid ${master}.${key}_check -row ${row} -column 0 -sticky w
+ grid ${master}.${key}_label -row ${row} -column 1 -sticky w
+ grid ${master}.${key}_value -row ${row} -column 2 -sticky ew
+ }
+
+# -------------------------------------------------------------------------
+
+ Class UsbController
+
+# -------------------------------------------------------------------------
+
+ UsbController instproc usbConnect {} {
+ my instvar handle
+
+ puts usbConnect
+
+ if {[my exists handle]} {
+ $handle disconnect
+ unset handle
+ }
+if {1} {
+ while {[catch {usb::connect 0x09FB 0x6001 1 1 0} result]} {
+ set answer [tk_messageBox -icon error -type retrycancel \
+ -message {Cannot access USB device} -detail $result]
+# puts $result
+ if {[string equal $answer cancel]} exit
+ }
+
+ set handle $result
+
+}
+ }
+
+# -------------------------------------------------------------------------
+
+ UsbController instproc usbHandle {} {
+ my instvar handle
+
+ if {[my exists handle]} {
+ return $handle
+ } else {
+ my usbConnect
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ UsbController instproc usbCmd {command} {
+ set code [catch {[my usbHandle] writeRaw [usb::convert $command]} result]
+ switch -- $code {
+ 1 {
+# puts $result
+ my usbConnect
+ }
+ }
+
+ }
+
+# -------------------------------------------------------------------------
+
+ UsbController instproc usbCmdReadRaw {command size data} {
+ my usbCmd $command
+
+ set code [catch {[my usbHandle] readRaw $size} result]
+ switch -- $code {
+ 0 {
+ set $data $result
+ }
+ 1 {
+# puts $result
+ my usbConnect
+ }
+ 5 {
+# puts Busy
+ }
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ UsbController instproc usbCmdReadRaw {command size data} {
+ my usbCmd $command
+
+ set code [catch {[my usbHandle] readRaw $size} result]
+ switch -- $code {
+ 0 {
+ set $data $result
+ }
+ 1 {
+# puts $result
+ my usbConnect
+ }
+ 5 {
+# puts Busy
+ }
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ UsbController instproc usbCmdReadHex {command width size data} {
+ my usbCmd $command
+
+ set code [catch {[my usbHandle] readHex $width $size} result]
+ switch -- $code {
+ 0 {
+ set $data $result
+ }
+ 1 {
+# puts $result
+ my usbConnect
+ }
+ 5 {
+# puts Busy
+ }
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ Class SpiDisplay -parameter {
+ {master}
+ {controller}
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc init {} {
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc start {} {
+ my instvar config
+
+ trace add variable [myvar dac1] write [myproc dac1_update]
+ trace add variable [myvar dac2] write [myproc dac2_update]
+
+ ${config(1)}.dac1 set 0
+ ${config(1)}.dac2 set 0
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc setup {} {
+ my instvar number master
+ my instvar config
+
+ set config(1) [labelframe ${master}.cfg1 -borderwidth 1 -relief sunken -text {DAC}]
+
+ frame ${config(1)}.limits
+ label ${config(1)}.limits.min -text {2.5V}
+ label ${config(1)}.limits.max -text {0.0V}
+
+ scale ${config(1)}.dac1 -orient vertical -from 4095 -to 0 -tickinterval 0 -variable [myvar dac1]
+ scale ${config(1)}.dac2 -orient vertical -from 4095 -to 0 -tickinterval 0 -variable [myvar dac2]
+
+ pack ${config(1)}.limits.min -anchor n -side top -pady 10
+ pack ${config(1)}.limits.max -anchor s -side bottom -pady 9
+
+ grid ${config(1)}.dac1 ${config(1)}.dac2 ${config(1)}.limits -sticky ns -pady 7
+
+
+ set config(2) [labelframe ${master}.cfg2 -borderwidth 1 -relief sunken -text {ADC}]
+
+ frame ${config(2)}.spc1 -width 130 -height 10
+ frame ${config(2)}.spc2 -width 130 -height 10
+ frame ${config(2)}.spc3 -width 130 -height 10
+
+ button ${config(2)}.reset -text {Reset} -command [myproc adc_reset]
+ button ${config(2)}.pattern -text {Test pattern} -command [myproc adc_pattern]
+ button ${config(2)}.ramp -text {Test ramp} -command [myproc adc_ramp]
+ button ${config(2)}.100mV -text {Test 100 mV} -command [myproc adc_100mV]
+ button ${config(2)}.150mV -text {Test 150 mV} -command [myproc adc_150mV]
+ button ${config(2)}.fltr0 -text {Filter 14MHz} -command [myproc adc_fltr0]
+ button ${config(2)}.fltr1 -text {Filter 10MHz} -command [myproc adc_fltr1]
+ button ${config(2)}.fltr2 -text {Filter 7.5MHz} -command [myproc adc_fltr2]
+
+ grid ${config(2)}.spc1
+ grid ${config(2)}.reset -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.spc2
+ grid ${config(2)}.pattern -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.ramp -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.100mV -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.150mV -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.spc3
+ grid ${config(2)}.fltr0 -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.fltr1 -sticky ew -pady 3 -padx 5
+ grid ${config(2)}.fltr2 -sticky ew -pady 3 -padx 5
+
+ grid ${config(1)} -row 1 -column 1 -sticky ns
+ grid ${config(2)} -row 1 -column 2 -sticky ns
+
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 1
+ grid columnconfigure ${master} 2 -weight 1
+ grid columnconfigure ${master} 3 -weight 1
+
+ grid rowconfigure ${master} 0 -weight 0
+ grid rowconfigure ${master} 1 -weight 1
+ grid rowconfigure ${master} 2 -weight 0
+
+ grid rowconfigure ${config(1)} 0 -weight 1
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc dac1_update args {
+ my instvar controller dac1
+
+ set value [format {3%03x} $dac1]
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000402[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 3]00
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc dac2_update args {
+ my instvar controller dac2
+
+ set value [format {b%03x} $dac1]
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000402[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 3]00
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_reset args {
+ my instvar controller
+
+ set prefix [format {%x} 12]
+
+ set command {}
+
+ set value {000001}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ set value {040008}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_pattern args {
+ my instvar controller
+
+ set value {022000}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_ramp args {
+ my instvar controller
+
+ set value {02E000}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_100mV args {
+ my instvar controller
+
+ set value {070080}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_150mV args {
+ my instvar controller
+
+ set value {070180}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_fltr0 args {
+ my instvar controller
+
+ set value {070000}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_fltr1 args {
+ my instvar controller
+
+ set value {070004}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ SpiDisplay instproc adc_fltr2 args {
+ my instvar controller
+
+ set value {070008}
+
+ set prefix [format {%x} 12]
+
+ set command {}
+ append command 0001${prefix}00000020000000401[string range $value 0 1]
+ append command 0001${prefix}000000200000004[string range $value 2 5]
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ Class MuxDisplay -parameter {
+ {master}
+ {controller}
+ }
+
+# -------------------------------------------------------------------------
+
+ MuxDisplay instproc init {} {
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ MuxDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ MuxDisplay instproc start {} {
+ variable adcCodes
+ my instvar config chan_val
+
+ set chan_val(1) 0
+ set chan_val(2) 0
+ set chan_val(3) 0
+ set chan_val(4) 0
+ set chan_val(5) 0
+ set chan_val(6) 0
+
+ trace add variable [myvar chan_val] write [myproc chan_val_update]
+ trace add variable [myvar polar] write [myproc polar_update]
+
+ $config(1).chan_0_1 select
+ $config(2).chan_0_2 select
+ $config(3).chan_0_3 select
+ $config(4).chan_0_4 select
+ $config(5).chan_0_5 select
+ $config(6).chan_0_1 select
+
+ foreach {ch dummy} [array get adcCodes] {
+ $config(inv).polar_${ch} deselect
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ MuxDisplay instproc setup {} {
+ variable oscCodes
+ variable adcCodes
+ variable inpCodes
+ my instvar master
+ my instvar config
+
+ set size [array size inpCodes]
+ set oscList [array get oscCodes]
+ set adcList [array get adcCodes]
+ set inpList [array get inpCodes]
+
+ set mux [frame ${master}.mux]
+ set key [frame ${master}.key]
+ set inv [frame ${master}.inv]
+
+ foreach {osc title} $oscList {
+ set config($osc) [labelframe ${mux}.$osc -borderwidth 1 -relief sunken -text $title]
+ set column 1
+ foreach {code input} $inpList {
+ label $config($osc).input_${input} -text " ${input}"
+ grid $config($osc).input_${input} -row 0 -column ${column} -sticky w
+ incr column
+ }
+ foreach {ch dummy} $adcList {
+ label $config($osc).chan_${ch} -text "${ch} "
+ grid $config($osc).chan_${ch} -row ${ch} -column 0 -sticky ew
+ foreach {code input} $inpList {
+ set column [expr {$code + 1}]
+ set value [expr {$size * ($ch - 1) + $code}]
+ radiobutton $config($osc).chan_${code}_${ch} -variable [myvar chan_val($osc)] -value ${value}
+ grid $config($osc).chan_${code}_${ch} -row ${ch} -column ${column} -sticky w
+ }
+ }
+ set column [expr {($osc - 1) % 6}]
+ set row [expr {($osc - 1) / 6}]
+ grid $config($osc) -row ${row} -column ${column} -sticky news -padx 10
+ }
+
+ set config(key) [labelframe ${key}.frame -borderwidth 1 -relief sunken -text {legend}]
+
+ label $config(key).r -text "r - raw signal"
+ grid $config(key).r -row 0 -column 0 -sticky news
+
+ label $config(key).f -text "f - filtered signal"
+ grid $config(key).f -row 0 -column 1 -sticky news
+
+ label $config(key).d -text "d - deconvoluted signal"
+ grid $config(key).d -row 0 -column 2 -sticky news
+
+ label $config(key).c -text "c - clipped signal"
+ grid $config(key).c -row 0 -column 3 -sticky news
+
+ grid $config(key) -row 0 -column 0 -sticky news -padx 10
+
+
+ set config(inv) [labelframe ${inv}.frame -borderwidth 1 -relief sunken -text {polarity inversion}]
+ label $config(inv).chan_label -text "channel "
+ grid $config(inv).chan_label -row 0 -column 0 -sticky e
+ label $config(inv).polar_label -text "polarity"
+ grid $config(inv).polar_label -row 1 -column 0 -sticky e
+ foreach {ch dummy} $adcList {
+ label $config(inv).chan_${ch} -text "${ch} "
+ grid $config(inv).chan_${ch} -row 0 -column ${ch} -sticky ew
+ checkbutton $config(inv).polar_${ch} -variable [myvar polar($ch)]
+ grid $config(inv).polar_${ch} -row 1 -column ${ch} -sticky w
+ }
+ grid $config(inv) -row 0 -column 0 -sticky news -padx 10
+
+ grid ${key} -row 0 -column 0 -sticky news
+ grid ${mux} -row 1 -column 0 -sticky news
+ grid ${inv} -row 2 -column 0 -sticky news
+
+ grid columnconfigure ${master} 0 -weight 1
+ grid rowconfigure ${master} 0 -weight 1
+ grid rowconfigure ${master} 1 -weight 1
+ grid rowconfigure ${master} 2 -weight 1
+
+ grid columnconfigure ${inv} 0 -weight 1
+
+ grid columnconfigure ${key} 0 -weight 1
+ grid columnconfigure $config(key) 0 -weight 1
+ grid columnconfigure $config(key) 1 -weight 1
+ grid columnconfigure $config(key) 2 -weight 1
+ grid columnconfigure $config(key) 3 -weight 1
+
+
+ grid columnconfigure ${mux} 0 -weight 1
+ grid columnconfigure ${mux} 1 -weight 1
+ grid columnconfigure ${mux} 2 -weight 1
+ grid columnconfigure ${mux} 3 -weight 1
+ grid columnconfigure ${mux} 4 -weight 1
+ grid columnconfigure ${mux} 5 -weight 1
+
+
+ }
+
+
+# ------------------------------------------------------------------------
+
+ MuxDisplay instproc chan_val_update args {
+ my instvar controller chan_val
+
+ set byte1 [format {%02x%02x} $chan_val(2) $chan_val(1)]
+ set byte2 [format {%02x%02x} $chan_val(4) $chan_val(3)]
+ set byte3 [format {%02x%02x} $chan_val(6) $chan_val(5)]
+
+ $controller usbCmd 000200020004${byte1}000200030004${byte2}000200040004${byte3}
+ }
+
+# -------------------------------------------------------------------------
+
+ MuxDisplay instproc polar_update args {
+ my instvar controller polar
+
+ set value {0b}
+ for {set i 12} {$i >= 1} {incr i -1} {
+ append value $polar($i)
+ }
+
+ set value [format {%04x} $value]
+
+ $controller usbCmd 000200010004${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ Class HstDisplay -parameter {
+ {number}
+ {master}
+ {controller}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc init {} {
+
+ my set data {}
+
+ vector create [myvar xvec](4096)
+ vector create [myvar yvec](4096)
+
+ # fill one vector for the x axis with 4096 points
+ [myvar xvec] seq -0.5 4095.5
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc start {} {
+ my instvar config
+
+ trace add variable [myvar data] write [myproc data_update]
+ trace add variable [myvar cntr_val] write [myproc cntr_val_update]
+ trace add variable [myvar rate_val] write [myproc rate_val_update]
+
+ trace add variable [myvar axis] write [myproc axis_update]
+ trace add variable [myvar thrs] write [myproc thrs_update]
+ trace add variable [myvar thrs_val] write [myproc thrs_update]
+ trace add variable [myvar base] write [myproc base_update]
+ trace add variable [myvar base_typ] write [myproc base_typ_update]
+ trace add variable [myvar base_val] write [myproc base_val_update]
+
+ ${config}.axis_check select
+
+ ${config}.thrs_check select
+ ${config}.thrs_field set 25
+
+ ${config}.base_auto select
+ ${config}.base_field set 20
+ ${config}.base_check select
+
+ set cntr_tmp 1200000000
+ my set cntr_val $cntr_tmp
+ my set cntr_bak $cntr_tmp
+ my set cntr_old $cntr_tmp
+ my set yvec_bak 0.0
+ my set yvec_old 0.0
+
+ my set rate_val(inst) 0.0
+ my set rate_val(mean) 0.0
+
+# my cntr_reset
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc setup {} {
+ my instvar number master
+ my instvar xvec yvec graph
+ my instvar config thrs thrs_val base base_typ base_val
+ my instvar cntr_h cntr_m cntr_s
+
+ # create a graph widget and show a grid
+ set graph [graph ${master}.graph -height 250 -leftmargin 80]
+ $graph crosshairs configure -hide no -linewidth 1 -color darkblue -dashes {2 2}
+ $graph grid configure -hide no
+ $graph legend configure -hide yes
+ $graph axis configure x -min 0 -max 4096
+
+ set config [frame ${master}.config -width 170]
+
+ checkbutton ${config}.axis_check -text {log scale} -variable [myvar axis]
+
+ frame ${config}.spc1 -width 170 -height 30
+
+ frame ${config}.rate_frame -borderwidth 0 -width 170
+ legendLabel ${config}.rate_frame 0 inst {Inst. rate, 1/s}
+ legendLabel ${config}.rate_frame 1 mean {Avg. rate, 1/s}
+
+ frame ${config}.spc2 -width 170 -height 30
+
+ frame ${config}.chan_frame -borderwidth 0 -width 170
+ legendLabel ${config}.chan_frame 0 axisy {Bin entries}
+ legendLabel ${config}.chan_frame 1 axisx {Bin number}
+
+ frame ${config}.spc3 -width 170 -height 30
+
+ frame ${config}.cntr_frame -borderwidth 0 -width 170
+
+ label ${config}.cntr_frame.h -width 3 -anchor w -text {h}
+ entry ${config}.cntr_frame.h_field -width 3 -textvariable [myvar cntr_h] \
+ -validate all -vcmd {::mca::validate 999 3 %P}
+ label ${config}.cntr_frame.m -width 3 -anchor w -text {m}
+ entry ${config}.cntr_frame.m_field -width 3 -textvariable [myvar cntr_m] \
+ -validate all -vcmd {::mca::validate 59 2 %P}
+ label ${config}.cntr_frame.s -width 3 -anchor w -text {s}
+ entry ${config}.cntr_frame.s_field -width 6 -textvariable [myvar cntr_s] \
+ -validate all -vcmd {::mca::doublevalidate 59.999 %P}
+
+ grid ${config}.cntr_frame.h_field ${config}.cntr_frame.h \
+ ${config}.cntr_frame.m_field ${config}.cntr_frame.m ${config}.cntr_frame.s_field ${config}.cntr_frame.s
+
+ frame ${config}.spc4 -width 170 -height 10
+
+ button ${config}.start -text Start \
+ -bg yellow -activebackground yellow -command [myproc cntr_start]
+ button ${config}.reset -text Reset \
+ -bg red -activebackground red -command [myproc cntr_reset]
+
+ frame ${config}.spc5 -width 170 -height 30
+
+ checkbutton ${config}.thrs_check -text threshold -variable [myvar thrs]
+ spinbox ${config}.thrs_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar thrs_val] \
+ -validate all -vcmd {::mca::validate 4095 4 %P}
+
+ frame ${config}.spc6 -width 170 -height 30
+
+ checkbutton ${config}.base_check -text baseline -variable [myvar base]
+ radiobutton ${config}.base_auto -text automatic -variable [myvar base_typ] -value 1
+ radiobutton ${config}.base_const -text constant -variable [myvar base_typ] -value 0
+ spinbox ${config}.base_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar base_val] \
+ -validate all -vcmd {::mca::validate 4095 4 %P}
+
+ frame ${config}.spc7 -width 170 -height 30
+
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+ grid ${config}.axis_check -sticky w
+ grid ${config}.spc1
+ grid ${config}.rate_frame -sticky ew -padx 5
+ grid ${config}.spc2
+ grid ${config}.chan_frame -sticky ew -padx 5
+ grid ${config}.spc3
+ grid ${config}.cntr_frame -sticky ew -padx 5
+ grid ${config}.spc4
+ grid ${config}.start -sticky ew -pady 3 -padx 5
+ grid ${config}.reset -sticky ew -pady 3 -padx 5
+ grid ${config}.spc5
+ grid ${config}.thrs_check -sticky w
+ grid ${config}.thrs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc6
+ grid ${config}.base_check -sticky w
+ grid ${config}.base_auto -sticky w
+ grid ${config}.base_const -sticky w
+ grid ${config}.base_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc7
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+
+ grid ${graph} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 80
+
+ grid columnconfigure ${config}.rate_frame 1 -weight 1
+ grid columnconfigure ${config}.chan_frame 1 -weight 1
+
+ # enable zooming
+ Blt_ZoomStack $graph
+
+ my crosshairs $graph
+
+ #bind .graph {%W crosshairs configure -position @%x,%y}
+
+ # create one element with data for the x and y axis, no dots
+ $graph element create Spectrum1 -color blue -linewidth 2 -symbol none -smooth step -xdata [myvar xvec] -ydata [myvar yvec]
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc coor_update {W x y} {
+ my instvar config graph
+
+ $W crosshairs configure -position @${x},${y}
+
+ set index [$W axis invtransform x $x]
+ set index [::tcl::mathfunc::round $index]
+ catch {
+ ${config}.chan_frame.axisy_value configure -text [[myvar yvec] index $index]
+ ${config}.chan_frame.axisx_value configure -text ${index}.0
+ }
+ }
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc crosshairs {graph} {
+ set method [myproc coor_update]
+ bind $graph [list [self] coor_update %W %x %y]
+ bind $graph {
+ %W crosshairs off
+ }
+ bind $graph {
+ %W crosshairs on
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc axis_update args {
+ my instvar axis graph
+ if {$axis} {
+ $graph axis configure y -min 1 -max 1E10 -logscale yes
+ } else {
+ $graph axis configure y -min {} -max {} -logscale no
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc thrs_update args {
+ my instvar controller config number thrs thrs_val
+
+ if {[string equal $thrs_val {}]} {
+ set thrs_val 0
+ }
+
+ set val_addr [format %02x [expr {6 + 2 * ${number}}]]
+
+ if {$thrs} {
+ ${config}.thrs_field configure -state normal
+ set value [format %03x $thrs_val]
+ } else {
+ ${config}.thrs_field configure -state disabled
+ set value 000
+ }
+
+ $controller usbCmd 000200${val_addr}00040${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc base_update args {
+ my instvar controller config number base base_typ
+
+ set val_addr [format %02x [expr {7 + 2 * ${number}}]]
+
+ if {$base} {
+ ${config}.base_auto configure -state normal
+ ${config}.base_const configure -state normal
+ my base_typ_update
+ } else {
+ ${config}.base_auto configure -state disabled
+ ${config}.base_const configure -state disabled
+ ${config}.base_field configure -state disabled
+ $controller usbCmd 000200${val_addr}0004${base_typ}000
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc base_typ_update args {
+ my instvar config base_typ
+
+ switch -- $base_typ {
+ 1 {
+ ${config}.base_field configure -state disabled
+ }
+ 0 {
+ ${config}.base_field configure -state normal
+ }
+ }
+
+ my base_val_update
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc base_val_update args {
+ my instvar controller number base_typ base_val
+
+ if {[string equal $base_val {}]} {
+ set base_val 0
+ }
+
+ set val_addr [format %02x [expr {7 + 2 * ${number}}]]
+ set value [format %03x $base_val]
+
+ $controller usbCmd 000200${val_addr}0004${base_typ}${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc rate_val_update {name key op} {
+ my instvar config rate_val
+
+ ${config}.rate_frame.${key}_value configure -text [format {%.2e} $rate_val(${key})]
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_val_update args {
+ my instvar cntr_val cntr_h cntr_m cntr_s
+
+ set cntr_tmp [expr {${cntr_val}/20000}]
+ set cntr_h [expr {${cntr_tmp}/3600000}]
+ set cntr_m [expr {${cntr_tmp}%3600000/60000}]
+ set cntr_s [expr {${cntr_tmp}%3600000%60000/1000.0}]
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_setup {} {
+ my instvar controller number cntr_val
+
+ set word0 [format %08x [expr {${cntr_val} & 0xFFFFFFFF}]]
+ set word1 [format %08x [expr {${cntr_val} >> 32}]]
+
+ set prefix [format %x [expr {5 + ${number}}]]
+
+ set command {}
+ append command 0001${prefix}000000200000004[string range $word0 4 7]
+ append command 0001${prefix}000000200010004[string range $word0 0 3]
+ append command 0001${prefix}000000200020004[string range $word1 4 7]
+ append command 0001${prefix}000000200030004[string range $word1 0 3]
+
+ # send counter value
+ $controller usbCmd $command
+
+ # load counter value
+# set val_addr [format %02x [expr {12 + ${number}}]]
+# $controller usbCmd 000200${val_addr}00040001000200${val_addr}00040000
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_reset {} {
+ my instvar controller number after_handle
+ my instvar cntr_val cntr_bak cntr_old yvec_bak yvec_old
+
+ my cntr_stop
+
+ set value [format %04x [expr {1 << (5 + ${number})}]]
+ $controller usbCmd 000200000004${value}0002000000040000
+
+ set cntr_val $cntr_bak
+ my cntr_setup
+
+ set cntr_old $cntr_bak
+ set yvec_bak 0.0
+ set yvec_old 0.0
+
+ my acquire
+
+ my cntr_ready
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_ready {} {
+ my instvar config cntr_val cntr_bak
+
+ set cntr_val $cntr_bak
+
+ ${config}.start configure -text Start -command [myproc cntr_start]
+ ${config}.reset configure -state active
+
+ ${config}.cntr_frame.h_field configure -state normal
+ ${config}.cntr_frame.m_field configure -state normal
+ ${config}.cntr_frame.s_field configure -state normal
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_start {} {
+ my instvar config
+ my instvar cntr_h cntr_m cntr_s
+ my instvar cntr_val cntr_bak cntr_old yvec_bak yvec_old
+
+ set h $cntr_h
+ set m $cntr_m
+ set s $cntr_s
+
+ if {[string equal $h {}]} {
+ set h 0
+ }
+ if {[string equal $m {}]} {
+ set m 0
+ }
+ if {[string equal $s {}]} {
+ set s 0
+ }
+
+ set cntr_tmp [expr {${h}*3600000 + ${m}*60000 + ${s}*1000}]
+ set cntr_tmp [expr {entier(20000 * ${cntr_tmp})}]
+
+ if {$cntr_tmp > 0} {
+ ${config}.cntr_frame.h_field configure -state disabled
+ ${config}.cntr_frame.m_field configure -state disabled
+ ${config}.cntr_frame.s_field configure -state disabled
+
+ set cntr_val $cntr_tmp
+ set cntr_bak $cntr_tmp
+ set cntr_old $cntr_tmp
+ set yvec_bak [usb::integrateBlt [myvar yvec] 0]
+ set yvec_old $yvec_bak
+
+ my cntr_setup
+
+ my cntr_resume
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_pause {} {
+ my instvar config
+
+ my cntr_stop
+
+ ${config}.start configure -text Resume -command [myproc cntr_resume]
+# ${config}.reset configure -state active
+
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_resume {} {
+ my instvar controller config number auto
+
+ set val_addr [format %02x [expr {13 + ${number}}]]
+
+ ${config}.start configure -text Pause -command [myproc cntr_pause]
+# ${config}.reset configure -state disabled
+
+ $controller usbCmd 000200${val_addr}00040002
+
+ set auto 1
+
+ after 100 [myproc acquire_loop]
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc cntr_stop {} {
+ my instvar controller config number auto
+
+ set val_addr [format %02x [expr {13 + ${number}}]]
+
+ $controller usbCmd 000200${val_addr}00040000
+
+ set auto 0
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc data_update args {
+ my instvar data
+ usb::convertBlt $data 4 [myvar yvec]
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc acquire_loop {} {
+ my instvar cntr_val auto
+
+ my acquire
+
+ if {$cntr_val == 0} {
+ my cntr_stop
+ my cntr_ready
+ } elseif {$auto} {
+ after 1000 [myproc acquire_loop]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc acquire {} {
+ my instvar controller config number
+ my instvar cntr_val cntr_bak cntr_old yvec_bak yvec_old rate_val
+
+ set size 4096
+
+ set prefix [format {%x} [expr {$number + 2}]]
+
+ set value [format {%08x} [expr {$size * 2}]]
+
+ set command 0001${prefix}000000200000001[string range $value 0 3]0003[string range $value 4 7]00050000
+
+ $controller usbCmdReadRaw $command [expr {$size * 4}] [myvar data]
+ set yvec_new [usb::integrateBlt [myvar yvec]]
+
+ set prefix [format {%x} [expr {$number + 5}]]
+ set command 0001${prefix}000000200000003000400050000
+
+ $controller usbCmdReadHex $command 8 1 [myvar cntr_val]
+ set cntr_new $cntr_val
+
+ if {$cntr_new < $cntr_old} {
+ set rate_val(inst) [expr {($yvec_new - $yvec_old)*20000000/($cntr_old - $cntr_new)}]
+ set rate_val(mean) [expr {($yvec_new - $yvec_bak)*20000000/($cntr_bak - $cntr_new)}]
+ set yvec_old $yvec_new
+ set cntr_old $cntr_new
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc save_data {data} {
+ my instvar number
+
+ set types {
+ {{Data Files} {.dat} }
+ {{All Files} * }
+ }
+
+ set stamp [clock format [clock seconds] -format %Y%m%d_%H%M%S]
+ set fname spectrum_[expr {$number + 1}]_${stamp}.dat
+
+ set fname [tk_getSaveFile -filetypes $types -initialfile $fname]
+ if {[string equal $fname {}]} {
+ return
+ }
+
+ set x [catch {
+ set fid [open $fname w+]
+ puts $fid $data
+ close $fid
+ }]
+
+ if { $x || ![file exists $fname] || ![file isfile $fname] || ![file readable $fname] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$fname\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$fname\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc register {} {
+ my save_data [join [[myvar yvec] range 0 4095] \n]
+ }
+
+# -------------------------------------------------------------------------
+
+ Class CntDisplay -parameter {
+ {master}
+ {controller}
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc init {} {
+
+ my set data {}
+ my set cntr 0
+ my set recs 0
+
+ vector create [myvar xvec](16384)
+ vector create [myvar yvec](16384)
+
+ # fill one vector for the x axis with 16384 points
+ [myvar xvec] seq -0.5 16384.5
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc start {} {
+ my instvar config
+
+ trace add variable [myvar data] write [myproc data_update]
+
+ trace add variable [myvar thrs_val] write [myproc thrs_val_update]
+
+ trace add variable [myvar cntr] write [myproc cntr_update]
+ trace add variable [myvar recs] write [myproc recs_update]
+
+ trace add variable [myvar axis] write [myproc axis_update]
+
+ ${config}.axis_check select
+
+ my set thrs_val 100
+
+ my set cntr_val 100
+ my set cntr_bak 100
+ my set recs_val 100
+ my set recs_bak 100
+
+# my cntr_reset
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc setup {} {
+ my instvar master
+ my instvar xvec yvec graph
+ my instvar config
+ my instvar cntr_ms
+
+ # create a graph widget and show a grid
+ set graph [graph ${master}.graph -height 250 -leftmargin 80]
+ $graph crosshairs configure -hide no -linewidth 1 -color darkblue -dashes {2 2}
+ $graph grid configure -hide no
+ $graph legend configure -hide yes
+ $graph axis configure x -min 0 -max 16384
+
+ set config [frame ${master}.config -width 170]
+
+ checkbutton ${config}.axis_check -text {log scale} -variable [myvar axis]
+
+ frame ${config}.spc1 -width 170 -height 30
+
+ frame ${config}.chan_frame -borderwidth 0 -width 170
+ legendLabel ${config}.chan_frame 0 mean {Mean value}
+ legendLabel ${config}.chan_frame 1 entr {Total entries}
+ legendLabel ${config}.chan_frame 2 empty {}
+ legendLabel ${config}.chan_frame 3 axisy {Bin entries}
+ legendLabel ${config}.chan_frame 4 axisx {Bin number}
+
+ frame ${config}.spc3 -width 170 -height 30
+
+ label ${config}.thrs -text {amplitude threshold}
+ spinbox ${config}.thrs_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar thrs_val] \
+ -validate all -vcmd {::mca::validate 4095 4 %P}
+
+ frame ${config}.spc4 -width 170 -height 30
+
+ label ${config}.cntr -text {time of exposure (s)}
+ spinbox ${config}.cntr_field -from 0 -to 9999 \
+ -increment 10 -width 10 -textvariable [myvar cntr_val] \
+ -validate all -vcmd {::mca::validate 9999 4 %P}
+
+ frame ${config}.spc5 -width 170 -height 10
+
+ label ${config}.recs -text {number of exposures}
+ spinbox ${config}.recs_field -from 0 -to 99999 \
+ -increment 10 -width 10 -textvariable [myvar recs_val] \
+ -validate all -vcmd {::mca::validate 99999 5 %P}
+
+ frame ${config}.spc6 -width 170 -height 10
+
+ button ${config}.start -text {Start} \
+ -bg yellow -activebackground yellow -command [myproc recs_start]
+
+ button ${config}.reset -text Reset \
+ -bg red -activebackground red -command [myproc cntr_reset]
+
+ frame ${config}.spc7 -width 170 -height 30
+
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+ grid ${config}.axis_check -sticky w
+ grid ${config}.spc1
+ grid ${config}.chan_frame -sticky ew -padx 5
+ grid ${config}.spc3
+ grid ${config}.thrs -sticky w -pady 1 -padx 3
+ grid ${config}.thrs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc4
+ grid ${config}.cntr -sticky w -pady 1 -padx 3
+ grid ${config}.cntr_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc5
+ grid ${config}.recs -sticky w -pady 1 -padx 3
+ grid ${config}.recs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc6
+ grid ${config}.start -sticky ew -pady 3 -padx 5
+ grid ${config}.reset -sticky ew -pady 3 -padx 5
+ grid ${config}.spc7
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+
+ grid ${graph} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 80
+
+ grid columnconfigure ${config}.chan_frame 1 -weight 1
+
+ # enable zooming
+ Blt_ZoomStack $graph
+
+ my crosshairs $graph
+
+ #bind .graph {%W crosshairs configure -position @%x,%y}
+
+ # create one element with data for the x and y axis, no dots
+ $graph element create Spectrum1 -color blue -linewidth 2 -symbol none -smooth step -xdata [myvar xvec] -ydata [myvar yvec]
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc coor_update {W x y} {
+ my instvar config graph
+
+ $W crosshairs configure -position @${x},${y}
+
+ set index [$W axis invtransform x $x]
+ set index [::tcl::mathfunc::round $index]
+ catch {
+ ${config}.chan_frame.axisy_value configure -text [[myvar yvec] index $index]
+ ${config}.chan_frame.axisx_value configure -text ${index}.0
+ }
+ }
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc crosshairs {graph} {
+ set method [myproc coor_update]
+ bind $graph [list [self] coor_update %W %x %y]
+ bind $graph {
+ %W crosshairs off
+ }
+ bind $graph {
+ %W crosshairs on
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc thrs_val_update args {
+ my instvar controller config thrs_val
+
+ if {[string equal $thrs_val {}]} {
+ set thrs_val 0
+ }
+
+ set val_addr [format %02x 12]
+
+ ${config}.thrs_field configure -state normal
+ set value [format %03x $thrs_val]
+
+ $controller usbCmd 000200${val_addr}00040${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc cntr_update args {
+ my instvar cntr cntr_val
+ set cntr_val [expr {${cntr}/20000000}]
+
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc recs_update args {
+ my instvar recs recs_val
+ set recs_val [expr {${recs}*1}]
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc cntr_setup {} {
+ my instvar controller cntr_val
+
+ set cntr_tmp [expr {${cntr_val} * 20000000}]
+ set word0 [format {%08x} [expr {${cntr_tmp} & 0xFFFFFFFF}]]
+ set word1 [format {%08x} [expr {${cntr_tmp} >> 32}]]
+
+ set prefix [format {%x} 9]
+
+ set command {}
+ append command 0001${prefix}000000200000004[string range $word0 4 7]
+ append command 0001${prefix}000000200010004[string range $word0 0 3]
+ append command 0001${prefix}000000200020004[string range $word1 4 7]
+ append command 0001${prefix}000000200030004[string range $word1 0 3]
+
+ # send counter value
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc recs_setup {} {
+ my instvar controller recs_val
+
+ set word0 [format {%08x} [expr {${recs_val} & 0xFFFFFFFF}]]
+ set word1 [format {%08x} [expr {${recs_val} >> 32}]]
+
+ set prefix [format {%x} 10]
+
+ set command {}
+ append command 0001${prefix}000000200000004[string range $word0 4 7]
+ append command 0001${prefix}000000200010004[string range $word0 0 3]
+ append command 0001${prefix}000000200020004[string range $word1 4 7]
+ append command 0001${prefix}000000200030004[string range $word1 0 3]
+
+ # send counter value
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc cntr_reset {} {
+ my instvar controller after_handle
+ my instvar cntr_val cntr_bak recs_val recs_bak
+
+ my cntr_stop
+
+ set value [format {%04x} [expr {1 << 11}]]
+ $controller usbCmd 000200000004${value}0002000000040000
+
+ my recs_stop
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc cntr_ready {} {
+ my instvar config cntr_val cntr_bak recs_val recs_bak
+
+ set cntr_val $cntr_bak
+ set recs_val $recs_bak
+
+ ${config}.start configure -text Start -command [myproc recs_start]
+ ${config}.reset configure -state active
+
+ ${config}.start configure -state active
+ ${config}.cntr_field configure -state normal
+ ${config}.recs_field configure -state normal
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc recs_start {} {
+ my instvar controller config auto
+ my instvar cntr_val cntr_bak recs_val recs_bak
+
+ if {$cntr_val > 0 && $recs_val > 0} {
+ ${config}.start configure -text {Stop} -command [myproc recs_stop]
+ ${config}.cntr_field configure -state disabled
+ ${config}.recs_field configure -state disabled
+
+ set cntr_bak $cntr_val
+ set recs_bak $recs_val
+
+ my cntr_setup
+ my recs_setup
+
+ set val_addr [format {%02x} 16]
+
+ $controller usbCmd 000200${val_addr}00040002
+
+ set auto 1
+
+ after 100 [myproc acquire_loop]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc recs_stop {} {
+ my instvar cntr_val cntr_bak recs_val recs_bak
+
+ my cntr_stop
+
+ set cntr_val $cntr_bak
+ my cntr_setup
+
+ set recs_val $recs_bak
+ my recs_setup
+
+ my acquire
+
+ my cntr_ready
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc cntr_stop {} {
+ my instvar controller config auto
+
+ set val_addr [format {%02x} 16]
+
+ $controller usbCmd 000200${val_addr}00040000
+
+ set auto 0
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc acquire_loop {} {
+ my instvar recs_val auto
+
+ my acquire
+
+ if {$recs_val == 0} {
+ my cntr_stop
+ my cntr_ready
+ } elseif {$auto} {
+ after 1000 [myproc acquire_loop]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc data_update args {
+ my instvar config data
+ usb::convertBlt $data 2 [myvar yvec]
+
+ ${config}.chan_frame.mean_value configure \
+ -text [format {%.2e} [usb::integrateBlt [myvar yvec] 1]]
+ ${config}.chan_frame.entr_value configure \
+ -text [usb::integrateBlt [myvar yvec] 0]
+
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc axis_update args {
+ my instvar axis graph
+ if {$axis} {
+ $graph axis configure y -min 1 -max 1E5 -logscale yes
+ } else {
+ $graph axis configure y -min {} -max {} -logscale no
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc acquire {} {
+ my instvar controller config
+ my instvar cntr cntr_val recs recs_val
+
+ set size 16384
+
+ set prefix [format {%x} 8]
+
+ set value [format {%08x} $size]
+
+ set command 0001${prefix}000000200000001[string range $value 0 3]0003[string range $value 4 7]00050000
+
+ $controller usbCmdReadRaw $command [expr {$size * 2}] [myvar data]
+
+ set prefix [format {%x} 9]
+ set command 0001${prefix}000000200000003000400050000
+
+ $controller usbCmdReadHex $command 8 1 [myvar cntr]
+
+ set prefix [format {%x} 10]
+ set command 0001${prefix}000000200000003000400050000
+
+ $controller usbCmdReadHex $command 8 1 [myvar recs]
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc save_data {data} {
+
+ set types {
+ {{Data Files} {.dat} }
+ {{All Files} * }
+ }
+
+ set stamp [clock format [clock seconds] -format %Y%m%d_%H%M%S]
+ set fname counts_${stamp}.dat
+
+ set fname [tk_getSaveFile -filetypes $types -initialfile $fname]
+ if {[string equal $fname {}]} {
+ return
+ }
+
+ set x [catch {
+ set fid [open $fname w+]
+ puts $fid $data
+ close $fid
+ }]
+
+ if { $x || ![file exists $fname] || ![file isfile $fname] || ![file readable $fname] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$fname\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$fname\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ CntDisplay instproc register {} {
+ my save_data [join [[myvar yvec] range 0 16383] \n]
+ }
+
+# -------------------------------------------------------------------------
+
+ Class OscDisplay -parameter {
+ {master}
+ {controller}
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc init {} {
+ my instvar sequence data xvec yvec
+
+ set data {}
+
+ set sequence 0
+
+# set xvec [vector create #auto(262144)]
+ set xvec [vector create #auto(10000)]
+
+ for {set i 1} {$i <= 9} {incr i} {
+# dict set yvec $i [vector create #auto(262144)]
+ dict set yvec $i [vector create #auto(10000)]
+ }
+
+ # fill one vector for the x axis
+# $xvec seq 0 262143
+ $xvec seq 0 10000
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc start {} {
+ my instvar config
+ my instvar recs_val directory
+
+ set directory $::env(HOMEPATH)
+ set recs_val 100
+
+ trace add variable [myvar chan] write [myproc chan_update]
+
+ trace add variable [myvar data] write [myproc data_update]
+
+ trace add variable [myvar auto] write [myproc auto_update]
+
+ trace add variable [myvar thrs] write [myproc thrs_update 0]
+ trace add variable [myvar thrs_val] write [myproc thrs_update 0]
+
+ trace add variable [myvar recs_val] write [myproc recs_val_update]
+
+ trace add variable [myvar last] write [myproc last_update]
+
+ ${config}.chan_frame.chan1_check select
+ ${config}.chan_frame.chan2_check select
+ ${config}.chan_frame.chan3_check select
+ ${config}.chan_frame.chan4_check select
+ ${config}.chan_frame.chan5_check select
+ ${config}.chan_frame.chan6_check select
+
+ ${config}.thrs_check select
+ ${config}.thrs_field set 100
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc setup {} {
+ my instvar master
+ my instvar xvec yvec graph
+ my instvar config
+
+ # create a graph widget and show a grid
+ set graph [graph ${master}.graph -height 250 -leftmargin 80]
+ $graph crosshairs configure -hide no -linewidth 1 -color darkblue -dashes {2 2}
+ $graph grid configure -hide no
+ $graph legend configure -hide yes
+ $graph axis configure x -min 0 -max 10000
+ $graph axis configure y -min 0 -max 4100
+
+# scale ${master}.last -orient horizontal -from 1 -to 27 -tickinterval 0 -showvalue no -variable [myvar last]
+
+ set config [frame ${master}.config -width 170]
+
+ frame ${config}.chan_frame -width 170
+ legendButton ${config}.chan_frame 0 chan1 {Channel 1} [myvar chan(1)] turquoise2
+ legendButton ${config}.chan_frame 1 chan2 {Channel 2} [myvar chan(2)] SpringGreen2
+ legendButton ${config}.chan_frame 2 chan3 {Channel 3} [myvar chan(3)] orchid2
+ legendButton ${config}.chan_frame 3 chan4 {Channel 4} [myvar chan(4)] orange2
+ legendButton ${config}.chan_frame 4 chan5 {Channel 5} [myvar chan(5)] blue1 white
+ legendButton ${config}.chan_frame 5 chan6 {Channel 6} [myvar chan(6)] gray65 white
+ legendLabel ${config}.chan_frame 6 axisx {Time axis}
+
+ frame ${config}.spc1 -width 170 -height 30
+
+ checkbutton ${config}.auto_check -text {auto update} -variable [myvar auto]
+
+ frame ${config}.spc2 -width 170 -height 30
+
+ checkbutton ${config}.thrs_check -text threshold -variable [myvar thrs]
+ spinbox ${config}.thrs_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar thrs_val] \
+ -validate all -vcmd {::mca::validate 4095 4 %P}
+
+ frame ${config}.spc3 -width 170 -height 30
+
+ button ${config}.acquire -text Acquire \
+ -bg green -activebackground green -command [myproc acquire_start]
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+ frame ${config}.spc4 -width 170 -height 30
+
+ label ${config}.recs -text {number of records}
+ spinbox ${config}.recs_field -from 0 -to 10000 \
+ -increment 10 -width 10 -textvariable [myvar recs_val] \
+ -validate all -vcmd {::mca::validate 10000 5 %P}
+
+ frame ${config}.spc5 -width 170 -height 10
+
+ button ${config}.sequence -text {Start Recording} -command [myproc sequence_start] \
+ -bg yellow -activebackground yellow
+
+ frame ${config}.spc6 -width 170 -height 10
+
+ button ${config}.recover -text {Read file} \
+ -bg lightblue -activebackground lightblue -command [myproc recover]
+
+ grid ${config}.chan_frame -sticky ew
+ grid ${config}.spc1
+ grid ${config}.auto_check -sticky w
+ grid ${config}.spc2
+ grid ${config}.thrs_check -sticky w
+ grid ${config}.thrs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc3
+ grid ${config}.acquire -sticky ew -pady 3 -padx 5
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+ grid ${config}.spc4
+ grid ${config}.recs -sticky w -pady 1 -padx 3
+ grid ${config}.recs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc5
+ grid ${config}.sequence -sticky ew -pady 3 -padx 5
+ grid ${config}.spc6
+ grid ${config}.recover -sticky ew -pady 3 -padx 5
+
+ grid ${graph} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+# grid ${master}.last -row 1 -column 0 -columnspan 2 -sticky ew
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 120
+
+ grid columnconfigure ${config}.chan_frame 2 -weight 1
+
+ # enable zooming
+ Blt_ZoomStack $graph
+
+ my crosshairs $graph
+
+ # create one element with data for the x and y axis, no dots
+ $graph pen create pen1 -color turquoise3 -linewidth 2 -symbol none
+ $graph pen create pen2 -color SpringGreen3 -linewidth 2 -symbol none
+ $graph pen create pen3 -color orchid3 -linewidth 2 -symbol none
+ $graph pen create pen4 -color orange3 -linewidth 2 -symbol none
+ $graph pen create pen5 -color blue2 -linewidth 2 -symbol none
+ $graph pen create pen6 -color gray55 -linewidth 2 -symbol none
+
+ $graph element create Spectrum1 -pen pen1 -xdata $xvec -ydata [dict get $yvec 1]
+ $graph element create Spectrum2 -pen pen2 -xdata $xvec -ydata [dict get $yvec 2]
+ $graph element create Spectrum3 -pen pen3 -xdata $xvec -ydata [dict get $yvec 3]
+ $graph element create Spectrum4 -pen pen4 -xdata $xvec -ydata [dict get $yvec 4]
+ $graph element create Spectrum5 -pen pen5 -xdata $xvec -ydata [dict get $yvec 5]
+ $graph element create Spectrum6 -pen pen6 -xdata $xvec -ydata [dict get $yvec 6]
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc coor_update {W x y} {
+ my instvar xvec yvec graph
+ my instvar config
+
+ $W crosshairs configure -position @${x},${y}
+
+ set index [$W axis invtransform x $x]
+ set index [::tcl::mathfunc::round $index]
+ catch {
+ ${config}.chan_frame.chan1_value configure -text [[dict get $yvec 1] index $index]
+ ${config}.chan_frame.chan2_value configure -text [[dict get $yvec 2] index $index]
+ ${config}.chan_frame.chan3_value configure -text [[dict get $yvec 3] index $index]
+ ${config}.chan_frame.chan4_value configure -text [[dict get $yvec 4] index $index]
+ ${config}.chan_frame.chan5_value configure -text [[dict get $yvec 5] index $index]
+ ${config}.chan_frame.chan6_value configure -text [[dict get $yvec 6] index $index]
+ ${config}.chan_frame.axisx_value configure -text ${index}.0
+ }
+ }
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc crosshairs {graph} {
+ set method [myproc coor_update]
+ bind $graph [list [self] coor_update %W %x %y]
+ bind $graph {
+ %W crosshairs off
+ }
+ bind $graph {
+ %W crosshairs on
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc chan_update {name key op} {
+ my instvar config graph chan
+
+ if {$chan(${key})} {
+ $graph pen configure pen${key} -linewidth 2
+ } else {
+ $graph pen configure pen${key} -linewidth 0
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc recs_val_update args {
+ my instvar recs_val
+ if {[string equal $recs_val {}]} {
+ set recs_val 0
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc last_update args {
+ my instvar graph last
+
+ set first [expr {$last - 1}]
+
+ $graph axis configure x -min ${first}0000 -max ${last}0000
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc thrs_update {reset args} {
+ my instvar controller config thrs thrs_val
+
+ if {[string equal $thrs_val {}]} {
+ set thrs_val 0
+ }
+
+ if {$thrs} {
+ ${config}.thrs_field configure -state normal
+ set value [format %03x $thrs_val]
+ } else {
+ ${config}.thrs_field configure -state disabled
+ set value 000
+ }
+
+ set command {}
+ if {$reset} {
+ append command 0002000500041${value}
+ }
+ append command 0002000500040${value}
+
+ $controller usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc data_update args {
+ my instvar data yvec
+ my instvar graph chan waiting sequence auto
+
+ usb::convertOsc $data $yvec
+
+ foreach {key value} [array get chan] {
+ $graph pen configure pen${key} -dashes 0
+ }
+
+ set waiting 0
+
+ if {$sequence} {
+ my sequence_register
+ } elseif {$auto} {
+ after 1000 [myproc acquire_start]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc acquire_start {} {
+ my instvar graph chan controller waiting
+
+ foreach {key value} [array get chan] {
+ $graph pen configure pen${key} -dashes dot
+ }
+
+ # restart
+ my thrs_update 1
+
+ set waiting 1
+
+ after 200 [myproc acquire_loop]
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc acquire_loop {} {
+ my instvar controller waiting
+
+# set size 262144
+ set size 10000
+
+ set value [format {%08x} [expr {$size * 4}]]
+
+ set command 00011000000200000001[string range $value 0 3]0003[string range $value 4 7]00050000
+
+ $controller usbCmdReadRaw $command [expr {$size * 8}] [myvar data]
+
+ if {$waiting} {
+ after 200 [myproc acquire_loop]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc auto_update args {
+ my instvar config auto
+
+ if {$auto} {
+ ${config}.recs_field configure -state disabled
+ ${config}.sequence configure -state disabled
+ ${config}.acquire configure -state disabled
+ ${config}.register configure -state disabled
+ ${config}.recover configure -state disabled
+
+ my acquire_start
+ } else {
+ ${config}.recs_field configure -state normal
+ ${config}.sequence configure -state active
+ ${config}.acquire configure -state active
+ ${config}.register configure -state active
+ ${config}.recover configure -state active
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc save_data {fname} {
+ my instvar data
+
+ set fid [open $fname w+]
+ fconfigure $fid -translation binary -encoding binary
+
+# puts -nonewline $fid [binary format "H*iH*" "1f8b0800" [clock seconds] "0003"]
+# puts -nonewline $fid [zlib deflate $data]
+ puts -nonewline $fid $data
+# puts -nonewline $fid [binary format i [zlib crc32 $data]]
+# puts -nonewline $fid [binary format i [string length $data]]
+
+ close $fid
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc open_data {} {
+ set types {
+ {{Data Files} {.dat} }
+ {{All Files} * }
+ }
+
+ set fname [tk_getOpenFile -filetypes $types]
+ if {[string equal $fname {}]} {
+ return
+ }
+
+ set x [catch {
+ set fid [open $fname r+]
+ fconfigure $fid -translation binary -encoding binary
+# set size [file size $fname]
+# seek $fid 10
+# my set data [zlib inflate [read $fid [expr {$size - 18}]]]
+ my set data [read $fid]
+ close $fid
+ }]
+
+ if { $x || ![file exists $fname] || ![file isfile $fname] || ![file readable $fname] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while reading \"$fname\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$fname\" read successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc register {} {
+ set types {
+ {{Data Files} {.dat} }
+ {{All Files} * }
+ }
+
+ set stamp [clock format [clock seconds] -format %Y%m%d_%H%M%S]
+ set fname oscillogram_${stamp}.dat
+
+ set fname [tk_getSaveFile -filetypes $types -initialfile $fname]
+ if {[string equal $fname {}]} {
+ return
+ }
+
+ if {[catch {my save_data $fname} result]} {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$fname\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$fname\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc recover {} {
+ my open_data
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc sequence_start {} {
+ my instvar config recs_val recs_bak directory counter sequence
+
+ set counter 1
+ if {$counter > $recs_val} {
+ return
+ }
+
+ set directory [tk_chooseDirectory -initialdir $directory -title {Choose a directory}]
+
+ if {[string equal $directory {}]} {
+ return
+ }
+
+ ${config}.recs_field configure -state disabled
+ ${config}.sequence configure -text {Stop Recording} -command [myproc sequence_stop]
+ ${config}.acquire configure -state disabled
+ ${config}.register configure -state disabled
+ ${config}.recover configure -state disabled
+
+ set recs_bak $recs_val
+
+ set sequence 1
+
+ my acquire_start
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc sequence_register {} {
+ my instvar config recs_val recs_bak directory counter
+
+ set fname [file join $directory oscillogram_$counter.dat]
+
+ my incr counter
+
+ if {[catch {my save_data $fname} result]} {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$fname\""
+ } elseif {$counter <= $recs_bak} {
+ set recs_val [expr {$recs_bak - $counter}]
+ my acquire_start
+ return
+ }
+
+ my sequence_stop
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc sequence_stop {} {
+ my instvar config recs_val recs_bak sequence
+
+ set sequence 0
+
+ set recs_val $recs_bak
+
+ ${config}.recs_field configure -state normal
+ ${config}.sequence configure -text {Start Recording} -command [myproc sequence_start]
+ ${config}.acquire configure -state active
+ ${config}.register configure -state active
+ ${config}.recover configure -state active
+ }
+
+# -------------------------------------------------------------------------
+
+ namespace export MuxDisplay
+ namespace export HstDisplay
+ namespace export CntDisplay
+ namespace export OscDisplay
+}
+
+set notebook [::blt::tabnotebook .notebook -borderwidth 1 -selectforeground black -side bottom]
+
+grid ${notebook} -row 0 -column 0 -sticky news -pady 5
+
+grid rowconfigure . 0 -weight 1
+grid columnconfigure . 0 -weight 1
+
+::mca::UsbController usb
+usb usbCmd 00000000
+
+set window [frame ${notebook}.spi]
+$notebook insert end -text "DAC & ADC control" -window $window -fill both
+::mca::SpiDisplay spi -master $window -controller usb
+
+set window [frame ${notebook}.mux]
+$notebook insert end -text "Interconnect" -window $window -fill both
+::mca::MuxDisplay mux -master $window -controller usb
+
+set window [frame ${notebook}.ept]
+$notebook insert end -text "Oscilloscope" -window $window -fill both
+::mca::OscDisplay osc -master $window -controller usb
+
+update
+
+spi start
+
+mux start
+
+osc start
+
+spi adc_reset
Index: /trunk/3DEES/adc_lvds.v
===================================================================
--- /trunk/3DEES/adc_lvds.v (revision 177)
+++ /trunk/3DEES/adc_lvds.v (revision 177)
@@ -0,0 +1,123 @@
+
+(* ALTERA_ATTRIBUTE = {"{-to int_data_p} DDIO_INPUT_REGISTER=HIGH; {-to int_data_n} DDIO_INPUT_REGISTER=LOW"} *)
+
+module adc_lvds
+ #(
+ parameter size = 8, // number of channels
+ parameter width = 24 // channel resolution
+ )
+ (
+ input wire clock,
+
+ input wire lvds_dco,
+ input wire lvds_fco,
+ input wire [size-1:0] lvds_d,
+
+ output wire adc_frame,
+ output wire [size*width-1:0] adc_data
+
+ );
+ localparam width2 = width + 2;
+
+ reg state, int_rdreq, adc_frame_reg;
+ wire int_wrfull, int_rdempty;
+
+ reg [size-1:0] int_data_p, int_data_n;
+
+ reg [2:0] int_edge_reg;
+
+ reg [size*width-1:0] int_fifo_reg;
+ wire [size*width-1:0] int_fifo_wire;
+
+ reg [size*width2-1:0] int_data_reg;
+ wire [size*width2-1:0] int_data_wire;
+
+ wire [size*width-1:0] int_q_wire;
+ reg [size*width-1:0] adc_data_reg;
+
+
+
+ genvar j;
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : INT_DATA
+// MSB first
+// assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]};
+// LSB first
+// assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
+ assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
+ assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
+ end
+ endgenerate
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(size*width),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("ON")) fifo_unit (
+// .data(int_data_wire),
+ .data(int_fifo_reg),
+ .rdclk(clock),
+ .rdreq((~int_rdempty) & int_rdreq),
+ .wrclk(lvds_fco),
+ .wrreq(~int_wrfull),
+ .q(int_q_wire),
+ .rdempty(int_rdempty),
+ .wrfull(int_wrfull),
+ .aclr(),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ always @ (posedge clock)
+ begin
+ case (state)
+ 1'b0:
+ begin
+ int_rdreq <= 1'b1;
+ adc_frame_reg <= 1'b0;
+ state <= 1'b1;
+ end
+
+ 1'b1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_rdreq <= 1'b0;
+ adc_frame_reg <= 1'b1;
+ adc_data_reg <= int_q_wire;
+ state <= 1'b0;
+ end
+ end
+ endcase
+ end
+
+ always @ (negedge lvds_dco)
+ begin
+ int_data_n <= lvds_d;
+ end
+
+ always @ (posedge lvds_dco)
+ begin
+ int_data_p <= lvds_d;
+ int_data_reg <= int_data_wire;
+ int_edge_reg <= {(~int_edge_reg[1]), int_edge_reg[0], lvds_fco};
+ if (int_edge_reg[1] & int_edge_reg[2])
+ begin
+ int_fifo_reg <= int_fifo_wire;
+ end
+ end
+
+ assign adc_frame = adc_frame_reg;
+ assign adc_data = adc_data_reg;
+
+endmodule
Index: /trunk/3DEES/amplitude.v
===================================================================
--- /trunk/3DEES/amplitude.v (revision 177)
+++ /trunk/3DEES/amplitude.v (revision 177)
@@ -0,0 +1,100 @@
+module amplitude
+ #(
+ parameter width = 12 // bit width of the input data
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [width-1:0] cfg_data,
+ input wire [width-1:0] inp_data,
+ output wire [width-1:0] out_data,
+ output wire out_flag
+ );
+
+ reg int_case_reg, int_case_next;
+ reg out_flag_reg, out_flag_next;
+ reg int_flag_reg, int_flag_next;
+ reg [width-1:0] int_mini_reg, int_mini_next;
+ reg [width-1:0] out_data_reg, out_data_next;
+ reg [width-1:0] inp_data_reg [1:0], inp_data_next [1:0];
+
+ wire int_comp_wire;
+ reg int_comp_reg, int_comp_next;
+
+ assign int_comp_wire = (inp_data_reg[1] < inp_data);
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_case_reg <= 1'b0;
+ int_mini_reg <= {(width){1'b0}};
+ inp_data_reg[0] <= {(width){1'b0}};
+ inp_data_reg[1] <= {(width){1'b0}};
+ out_data_reg <= {(width){1'b0}};
+ out_flag_reg <= 1'b0;
+ int_flag_reg <= 1'b0;
+ int_comp_reg <= 1'b0;
+ end
+ else
+ begin
+ int_case_reg <= int_case_next;
+ int_mini_reg <= int_mini_next;
+ inp_data_reg[0] <= inp_data_next[0];
+ inp_data_reg[1] <= inp_data_next[1];
+ out_data_reg <= out_data_next;
+ out_flag_reg <= out_flag_next;
+ int_flag_reg <= int_flag_next;
+ int_comp_reg <= int_comp_next;
+ end
+ end
+
+ always @*
+ begin
+ int_case_next = int_case_reg;
+ int_mini_next = int_mini_reg;
+ inp_data_next[0] = inp_data_reg[0];
+ inp_data_next[1] = inp_data_reg[1];
+ out_data_next = out_data_reg;
+ out_flag_next = out_flag_reg;
+ int_flag_next = int_flag_reg;
+ int_comp_next = int_comp_reg;
+
+ case (int_case_reg)
+ 0:
+ begin
+ if (frame)
+ begin
+ inp_data_next[0] = inp_data;
+ inp_data_next[1] = inp_data_reg[0];
+ int_comp_next = int_comp_wire;
+ out_data_next = {(width){1'b0}};
+ out_flag_next = 1'b0;
+ // minimum
+ if ((~int_comp_reg) & (int_comp_wire))
+ begin
+ int_mini_next = inp_data_reg[0];
+ int_flag_next = 1'b1;
+ end
+ // maximum
+ else if ((int_comp_reg) & (~int_comp_wire) & (int_flag_reg))
+ begin
+ out_data_next = inp_data_reg[0] - int_mini_reg;
+ int_flag_next = 1'b0;
+ int_case_next = 1'b1;
+ end
+ end
+ end
+
+ 1:
+ begin
+ out_flag_next = (out_data_reg >= cfg_data);
+ int_case_next = 1'b0;
+ end
+
+ endcase
+ end
+
+ assign out_data = out_data_reg;
+ assign out_flag = out_flag_reg;
+
+endmodule
Index: /trunk/3DEES/analyser.v
===================================================================
--- /trunk/3DEES/analyser.v (revision 177)
+++ /trunk/3DEES/analyser.v (revision 177)
@@ -0,0 +1,187 @@
+module analyser
+ (
+ input wire clock, frame, reset,
+ input wire [24:0] cfg_data,
+ input wire [1:0] uwt_flag,
+ input wire [11:0] uwt_data,
+ output wire ana_dead,
+ output wire ana_good,
+ output wire [11:0] ana_data,
+ output wire [11:0] ana_base
+ );
+
+ reg [2:0] state_reg, state_next;
+ reg [4:0] counter_reg, counter_next;
+ reg dead_reg, dead_next;
+ reg good_reg, good_next;
+ reg [11:0] data_reg, data_next;
+
+ reg [19:0] sample_reg, sample_next;
+
+ reg [19:0] buffer_reg [31:0];
+ reg [19:0] buffer_next [31:0];
+
+ wire [11:0] baseline = buffer_reg[31][16:5];
+ wire counter_max = (&counter_reg);
+
+ integer i;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ state_reg <= 3'd0;
+ counter_reg <= 5'd0;
+ sample_reg <= 20'd0;
+ dead_reg <= 1'b0;
+ good_reg <= 1'b0;
+ data_reg <= 12'd0;
+
+ for (i = 0; i <= 31; i = i + 1)
+ begin
+ buffer_reg[i] <= 20'hfffff;
+ end
+ end
+ else
+ begin
+ state_reg <= state_next;
+ counter_reg <= counter_next;
+ sample_reg <= sample_next;
+ dead_reg <= dead_next;
+ good_reg <= good_next;
+ data_reg <= data_next;
+
+ for (i = 0; i <= 31; i = i + 1)
+ begin
+ buffer_reg[i] <= buffer_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ state_next = state_reg;
+ counter_next = counter_reg;
+ sample_next = sample_reg;
+ dead_next = dead_reg;
+ good_next = good_reg;
+ data_next = data_reg;
+
+ for (i = 0; i <= 31; i = i + 1)
+ begin
+ buffer_next[i] = buffer_reg[i];
+ end
+
+ case (state_reg)
+ 0: // skip first 32 samples
+ begin
+ if (frame)
+ begin
+ counter_next = counter_reg + 5'd1;
+ if (counter_max)
+ begin
+ state_next = 3'd1;
+ end
+ end
+ end
+
+ 1: // skip first 32 baseline samples
+ begin
+ if (frame)
+ begin
+ for (i = 0; i < 31; i = i + 1)
+ begin
+ buffer_next[i+1] = buffer_reg[i] + {8'd0, uwt_data};
+ end
+ buffer_next[0] = {8'd0, uwt_data};
+
+ counter_next = counter_reg + 5'd1;
+ if (counter_max)
+ begin
+ state_next = 3'd2;
+ end
+ end
+ end
+
+ 2:
+ begin
+ if (frame)
+ begin
+
+ if (cfg_data[24])
+ begin
+ if (uwt_data > baseline)
+ begin
+ data_next = uwt_data - baseline;
+ end
+ else
+ begin
+ data_next = 12'd0;
+ end
+ end
+ else
+ begin
+ if (uwt_data > cfg_data[23:12])
+ begin
+ data_next = uwt_data - cfg_data[23:12];
+ end
+ else
+ begin
+ data_next = 12'd0;
+ end
+ end
+
+ sample_next = {8'd0, uwt_data};
+
+ dead_next = 1'b1;
+ good_next = 1'b0;
+
+ state_next = 3'd3;
+ end
+ end
+
+ 3:
+ begin
+
+ // if (sample - baseline < threshold)
+ if (data_reg < cfg_data[11:0])
+ begin
+ for (i = 0; i < 31; i = i + 1)
+ begin
+ buffer_next[i+1] = buffer_reg[i] + sample_reg;
+ end
+ buffer_next[0] = sample_reg;
+ dead_next = 1'b0;
+ end
+
+ state_next = 3'd2;
+
+ // skip 32 samples after peak
+ if (counter_max)
+ begin
+ if (uwt_flag[1])
+ begin
+ counter_next = 5'd0;
+ state_next = 3'd4;
+ end
+ end
+ else
+ begin
+ counter_next = counter_reg + 5'd1;
+ end
+ end
+
+ 4:
+ begin
+ good_next = dead_reg;
+ state_next = 2'd2;
+ end
+ endcase
+ end
+
+ assign ana_dead = dead_reg;
+ assign ana_good = good_reg;
+ assign ana_data = data_reg;
+ assign ana_base = baseline;
+
+endmodule
Index: /trunk/3DEES/average.v
===================================================================
--- /trunk/3DEES/average.v (revision 177)
+++ /trunk/3DEES/average.v (revision 177)
@@ -0,0 +1,305 @@
+module average
+ #(
+ parameter size = 1, // number of channels
+ parameter width = 16 // bit width of the input data
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [3*size*6-1:0] del_data,
+ input wire [3*size*width-1:0] inp_data,
+ output wire [3*size*width2-1:0] out_data
+ );
+
+ localparam width1 = width + 1;
+ localparam width2 = width + 6 + 1;
+
+ reg int_wren_reg, int_wren_next;
+ reg [1:0] int_chan_reg, int_chan_next;
+ reg [2:0] int_case_reg, int_case_next;
+ reg [7:0] int_addr_reg, int_addr_next;
+
+ reg [5:0] del_addr_reg, del_addr_next;
+ wire [5:0] del_addr_wire;
+ wire [7:0] int_addr_wire;
+
+ reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0];
+ wire [size*width2-1:0] acc_data_wire;
+
+ reg [size*width1-1:0] sub_data_reg [3:0], sub_data_next [3:0];
+ wire [size*width1-1:0] sub_data_wire;
+
+ reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0];
+ wire [size*width-1:0] inp_data_wire [3:0];
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : INT_DATA
+ assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
+ assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
+ assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
+
+ lpm_mux #(
+ .lpm_size(3),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(8),
+ .lpm_widths(2)) mux_unit_1 (
+ .sel(int_chan_next),
+ .data({
+ 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
+ 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
+ 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
+ .result(int_addr_wire));
+
+ lpm_add_sub #(
+ .lpm_direction("SUB"),
+ .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
+ .lpm_representation("UNSIGNED"),
+ .lpm_type("LPM_ADD_SUB"),
+ .lpm_width(6)) add_unit_1 (
+ .dataa(del_addr_reg),
+ .datab(int_addr_wire[5:0]),
+ .result(del_addr_wire));
+
+ lpm_add_sub #(
+ .lpm_direction("SUB"),
+ .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
+ .lpm_representation("SIGNED"),
+ .lpm_type("LPM_ADD_SUB"),
+ .lpm_width(width1)) sub_unit_1 (
+ .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
+ .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
+ .result(sub_data_wire[j*width1+width1-1:j*width1]));
+
+ lpm_add_sub #(
+ .lpm_direction("ADD"),
+ .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
+ .lpm_representation("SIGNED"),
+ .lpm_type("LPM_ADD_SUB"),
+ .lpm_width(width2)) acc_unit_1 (
+ .dataa({{(width2-width1+1){sub_data_reg[0][j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
+ .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
+ .result(acc_data_wire[j*width2+width2-1:j*width2]));
+
+ end
+ endgenerate
+
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(256),
+ .numwords_b(256),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(8),
+ .widthad_b(8),
+ .width_a(size*width),
+ .width_b(size*width),
+ .width_byteena_a(1)) ram_unit_1 (
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .address_a(int_addr_reg),
+ .address_b({int_addr_wire[7:6], del_addr_wire}),
+ .data_a(inp_data_reg[0]),
+ .q_b(inp_data_wire[3]),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({(size*width){1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_chan_reg <= 2'd0;
+ int_case_reg <= 3'd0;
+ del_addr_reg <= 6'd0;
+ int_addr_reg <= 8'd0;
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ inp_data_reg[i] <= {(size*width){1'b0}};
+ end
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ sub_data_reg[i] <= {(size*width1){1'b0}};
+ acc_data_reg[i] <= {(size*width2){1'b0}};
+ end
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_chan_reg <= int_chan_next;
+ int_case_reg <= int_case_next;
+ del_addr_reg <= del_addr_next;
+ int_addr_reg <= int_addr_next;
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ inp_data_reg[i] <= inp_data_next[i];
+ end
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ sub_data_reg[i] <= sub_data_next[i];
+ acc_data_reg[i] <= acc_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_chan_next = int_chan_reg;
+ int_case_next = int_case_reg;
+ del_addr_next = del_addr_reg;
+ int_addr_next = int_addr_reg;
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ inp_data_next[i] = inp_data_reg[i];
+ end
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ sub_data_next[i] = sub_data_reg[i];
+ acc_data_next[i] = acc_data_reg[i];
+ end
+
+ case (int_case_reg)
+ 0:
+ begin
+ // write zeros
+ int_wren_next = 1'b1;
+ del_addr_next = 6'd0;
+ int_addr_next = 8'd0;
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ inp_data_next[i] = {(size*width){1'b0}};
+ end
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ sub_data_next[i] = {(size*width1){1'b0}};
+ acc_data_next[i] = {(size*width2){1'b0}};
+ end
+
+ int_case_next = 3'd1;
+ end
+ 1:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 8'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_chan_next = 2'd0;
+ int_case_next = 3'd2;
+ end
+ end
+ 2: // frame
+ begin
+ if (frame)
+ begin
+ int_wren_next = 1'b1;
+
+ int_addr_next[7:6] = 2'd0;
+
+ // set read addr for 2nd pipeline
+ int_chan_next = 2'd1;
+
+ // register input data for 2nd and 3rd sums
+ inp_data_next[1] = inp_data_wire[1];
+ inp_data_next[2] = inp_data_wire[2];
+
+ // prepare registers for 1st sum
+ inp_data_next[0] = inp_data_wire[0];
+
+ sub_data_next[0] = sub_data_reg[1];
+ acc_data_next[0] = acc_data_reg[1];
+
+ int_case_next = 3'd3;
+ end
+
+ end
+ 3: // 1st sum
+ begin
+ int_addr_next[7:6] = 2'd1;
+
+ // set read addr for 3rd pipeline
+ int_chan_next = 2'd2;
+
+ // prepare registers for 2nd sum
+ inp_data_next[0] = inp_data_reg[1];
+
+ sub_data_next[0] = sub_data_reg[2];
+ acc_data_next[0] = acc_data_reg[2];
+
+ // register 1st sum
+ sub_data_next[1] = sub_data_wire;
+ acc_data_next[1] = acc_data_wire;
+
+ int_case_next = 3'd4;
+ end
+ 4: // 2nd sum
+ begin
+ int_addr_next[7:6] = 2'd2;
+
+ // prepare registers for 3rd sum
+ inp_data_next[0] = inp_data_reg[2];
+
+ sub_data_next[0] = sub_data_reg[3];
+ acc_data_next[0] = acc_data_reg[3];
+
+ // register 2nd sum
+ sub_data_next[2] = sub_data_wire;
+ acc_data_next[2] = acc_data_wire;
+
+ del_addr_next = del_addr_reg + 6'd1;
+
+ int_case_next = 3'd5;
+ end
+ 5: // 3rd sum
+ begin
+ int_wren_next = 1'b0;
+
+ // set read addr for 1st pipeline
+ int_chan_next = 2'd0;
+
+ // register 3rd sum
+ sub_data_next[3] = sub_data_wire;
+ acc_data_next[3] = acc_data_wire;
+
+ int_addr_next[5:0] = del_addr_reg;
+
+ int_case_next = 3'd2;
+ end
+ default:
+ begin
+ int_case_next = 3'd0;
+ end
+ endcase
+ end
+
+ assign out_data = {acc_data_reg[3], acc_data_reg[2], acc_data_reg[1]};
+
+endmodule
Index: /trunk/3DEES/cic_filter.v
===================================================================
--- /trunk/3DEES/cic_filter.v (revision 177)
+++ /trunk/3DEES/cic_filter.v (revision 177)
@@ -0,0 +1,273 @@
+module cic_filter
+ #(
+ parameter size = 3, // number of channels
+ parameter width = 12 // bit width of the input data (unsigned)
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [size*width-1:0] inp_data,
+ output wire [size*widthr-1:0] out_data,
+ output wire [size*widthr-1:0] out_data2,
+ output wire [size*widthr-1:0] out_data3
+ );
+
+ localparam widthr = width + 16;
+ /*
+ 4-bit LFSR with additional bits to keep track of previous values
+ */
+ reg [15:0] int_lfsr_reg, int_lfsr_next;
+
+ reg int_wren_reg, int_wren_next;
+ reg int_flag_reg, int_flag_next;
+ reg [1:0] int_chan_reg, int_chan_next;
+ reg [2:0] int_case_reg, int_case_next;
+ reg [7:0] int_addr_reg, int_addr_next;
+
+ wire [9:0] int_addr_wire;
+
+ reg [size*widthr-1:0] acc_data_reg [3:0], acc_data_next [3:0];
+ reg [size*widthr-1:0] int_data_reg [12:0], int_data_next [12:0];
+
+ wire [size*widthr-1:0] acc_data_wire [3:0], del_data_wire [1:0];
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : INT_DATA
+ assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
+
+ // -2*del_data_1 + del_data_2 + inp_data + result
+
+ assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
+ acc_data_reg[0][j*widthr+widthr-1:j*widthr]
+ + del_data_wire[1][j*widthr+widthr-1:j*widthr]
+ - {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0};
+
+ assign acc_data_wire[2][j*widthr+widthr-1:j*widthr] =
+ acc_data_reg[1][j*widthr+widthr-1:j*widthr]
+ + acc_data_reg[2][j*widthr+widthr-1:j*widthr];
+
+ assign acc_data_wire[3][j*widthr+widthr-1:j*widthr] =
+ acc_data_reg[2][j*widthr+widthr-1:j*widthr]
+ + acc_data_reg[3][j*widthr+widthr-1:j*widthr];
+
+ end
+ endgenerate
+
+ cic_pipeline #(
+ .width(size*widthr)) cic_pipeline_unit (
+ .clock(clock),
+ .data(acc_data_reg[0]),
+ .rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}),
+ .rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}),
+ .wraddress(int_addr_reg),
+ .wren(int_wren_reg),
+ .qa(del_data_wire[0]),
+ .qb(del_data_wire[1]));
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(10),
+ .lpm_widths(2)) mux_unit_1 (
+ .sel(int_chan_next),
+ .data({
+ 2'd3, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
+ 2'd2, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
+ 2'd1, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3],
+ 2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}),
+ .result(int_addr_wire));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_flag_reg <= 1'b0;
+ int_chan_reg <= 2'd0;
+ int_case_reg <= 3'd0;
+ int_addr_reg <= 8'd0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ acc_data_reg[i] <= {(size*widthr){1'b0}};
+ end
+ for(i = 0; i <= 12; i = i + 1)
+ begin
+ int_data_reg[i] <= {(size*widthr){1'b0}};
+ end
+ int_lfsr_reg <= 16'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_flag_reg <= int_flag_next;
+ int_chan_reg <= int_chan_next;
+ int_case_reg <= int_case_next;
+ int_addr_reg <= int_addr_next;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ acc_data_reg[i] <= acc_data_next[i];
+ end
+ for(i = 0; i <= 12; i = i + 1)
+ begin
+ int_data_reg[i] <= int_data_next[i];
+ end
+ int_lfsr_reg <= int_lfsr_next;
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_flag_next = int_flag_reg;
+ int_chan_next = int_chan_reg;
+ int_case_next = int_case_reg;
+ int_addr_next = int_addr_reg;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ acc_data_next[i] = acc_data_reg[i];
+ end
+ for(i = 0; i <= 12; i = i + 1)
+ begin
+ int_data_next[i] = int_data_reg[i];
+ end
+ int_lfsr_next = int_lfsr_reg;
+
+ case (int_case_reg)
+ 0:
+ begin
+ // write zeros
+ int_wren_next = 1'b1;
+ int_addr_next = 8'd0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ acc_data_next[i] = {(size*widthr){1'b0}};
+ end
+ for(i = 0; i <= 12; i = i + 1)
+ begin
+ int_data_next[i] = {(size*widthr){1'b0}};
+ end
+ int_case_next = 3'd1;
+ end
+ 1:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 8'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_flag_next = 1'b0;
+ int_chan_next = 2'd0;
+ int_lfsr_next = 16'h7650;
+ int_case_next = 3'd2;
+ end
+ end
+ 2: // frame
+ begin
+ int_flag_next = 1'b0;
+ if (frame)
+ begin
+ int_wren_next = 1'b1;
+
+ int_addr_next = {4'd0, int_lfsr_reg[3:0]};
+
+ // set read addr for 2nd pipeline
+ int_chan_next = 2'd1;
+
+ // prepare registers for 1st sum
+ acc_data_next[0] = acc_data_wire[0];
+ acc_data_next[1] = int_data_reg[0];
+ acc_data_next[2] = int_data_reg[1];
+ acc_data_next[3] = int_data_reg[2];
+
+ int_case_next = 3'd3;
+ end
+ if (int_flag_reg) // register 4th sum
+ begin
+ // register 4th sum
+ int_data_next[9] = acc_data_wire[1];
+ int_data_next[10] = acc_data_wire[2];
+ int_data_next[11] = acc_data_wire[3];
+ end
+ end
+ 3: // 1st sum
+ begin
+ int_addr_next = {4'd1, int_lfsr_reg[3:0]};
+
+ // set read addr for 3rd pipeline
+ int_chan_next = 2'd2;
+
+ // prepare registers for 2nd sum
+ acc_data_next[0] = int_data_reg[2];
+ acc_data_next[1] = int_data_reg[3];
+ acc_data_next[2] = int_data_reg[4];
+ acc_data_next[3] = int_data_reg[5];
+
+ // register 1st sum
+ int_data_next[0] = acc_data_wire[1];
+ int_data_next[1] = acc_data_wire[2];
+ int_data_next[2] = acc_data_wire[3];
+
+ int_case_next = 3'd4;
+ end
+ 4: // 2nd sum
+ begin
+ int_addr_next = {4'd2, int_lfsr_reg[3:0]};
+
+ // set read addr for 4th pipeline
+ int_chan_next = 2'd3;
+
+ // prepare registers for 3rd sum
+ acc_data_next[0] = int_data_reg[5];
+ acc_data_next[1] = int_data_reg[6];
+ acc_data_next[2] = int_data_reg[7];
+ acc_data_next[3] = int_data_reg[8];
+
+ // register 2nd sum
+ int_data_next[3] = acc_data_wire[1];
+ int_data_next[4] = acc_data_wire[2];
+ int_data_next[5] = acc_data_wire[3];
+
+ int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
+
+ int_case_next = 3'd5;
+ end
+ 5: // 3rd sum
+ begin
+ int_flag_next = 1'b1;
+
+ int_addr_next = {4'd3, int_lfsr_reg[4:1]};
+
+ // set read addr for 1st pipeline
+ int_chan_next = 2'd0;
+
+ // prepare registers for 4th sum
+ acc_data_next[0] = int_data_reg[8];
+ acc_data_next[1] = int_data_reg[9];
+ acc_data_next[2] = int_data_reg[10];
+ acc_data_next[3] = int_data_reg[11];
+
+ // register 3rd sum
+ int_data_next[6] = acc_data_wire[1];
+ int_data_next[7] = acc_data_wire[2];
+ int_data_next[8] = acc_data_wire[3];
+
+ // register 4th output
+ int_data_next[12] = int_data_reg[11];
+
+ int_case_next = 3'd2;
+ end
+ default:
+ begin
+ int_case_next = 3'd0;
+ end
+ endcase
+ end
+
+ assign out_data = int_data_reg[5];
+ assign out_data2 = int_data_reg[8];
+ assign out_data3 = int_data_reg[12];
+
+endmodule
Index: /trunk/3DEES/cic_pipeline.v
===================================================================
--- /trunk/3DEES/cic_pipeline.v (revision 177)
+++ /trunk/3DEES/cic_pipeline.v (revision 177)
@@ -0,0 +1,104 @@
+module cic_pipeline
+ #(
+ parameter width = 192
+ )
+ (
+ input wire clock,
+ input wire [width-1:0] data,
+ input wire [7:0] rdaddress_a,
+ input wire [7:0] rdaddress_b,
+ input wire [7:0] wraddress,
+ input wire wren,
+ output wire [width-1:0] qa,
+ output wire [width-1:0] qb
+ );
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(256),
+ .numwords_b(256),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(8),
+ .widthad_b(8),
+ .width_a(width),
+ .width_b(width),
+ .width_byteena_a(1)) ram_unit_a(
+ .wren_a(wren),
+ .clock0(clock),
+ .address_a(wraddress),
+ .address_b(rdaddress_a),
+ .data_a(data),
+ .q_b(qa),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({width{1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(256),
+ .numwords_b(256),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(8),
+ .widthad_b(8),
+ .width_a(width),
+ .width_b(width),
+ .width_byteena_a(1)) ram_unit_b(
+ .wren_a(wren),
+ .clock0(clock),
+ .address_a(wraddress),
+ .address_b(rdaddress_b),
+ .data_a(data),
+ .q_b(qb),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({width{1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+endmodule
Index: /trunk/3DEES/clip.v
===================================================================
--- /trunk/3DEES/clip.v (revision 177)
+++ /trunk/3DEES/clip.v (revision 177)
@@ -0,0 +1,349 @@
+module clip
+ #(
+ parameter shift = 24, // right shift of the result
+ parameter width = 27, // bit width of the input data
+ parameter widthr = 12 // bit width of the output data
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [4*6-1:0] del_data,
+ input wire [4*6-1:0] amp_data,
+ input wire [4*16-1:0] tau_data,
+ input wire [4*width-1:0] inp_data,
+ output wire [4*widthr-1:0] out_data
+ );
+
+ localparam width1 = width + 16;
+ localparam width2 = width + 6;
+ localparam width3 = width1 + 2;
+
+ reg int_wren_reg, int_wren_next;
+ reg int_flag_reg, int_flag_next;
+ reg [1:0] int_chan_reg, int_chan_next;
+ reg [2:0] int_case_reg, int_case_next;
+ reg [7:0] int_addr_reg, int_addr_next;
+
+ reg [5:0] del_addr_reg, del_addr_next;
+ wire [5:0] del_addr_wire;
+ wire [7:0] int_addr_wire;
+
+ reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0];
+ wire [widthr-1:0] out_data_wire;
+
+ wire [width3-1:0] add_data_wire;
+
+ wire [width1-1:0] mul_data_wire1;
+ wire [width2-1:0] mul_data_wire2;
+
+ reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0];
+ wire [width-1:0] inp_data_wire [4:0];
+
+ reg [5:0] amp_data_reg, amp_data_next;
+ wire [5:0] amp_data_wire [3:0];
+
+ reg [15:0] tau_data_reg, tau_data_next;
+ wire [15:0] tau_data_wire [3:0];
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 4; j = j + 1)
+ begin : INT_DATA
+ assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
+ assign amp_data_wire[j] = amp_data[j*6+6-1:j*6];
+ assign tau_data_wire[j] = tau_data[j*16+16-1:j*16];
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(8),
+ .lpm_widths(2)) mux_unit_1 (
+ .sel(int_chan_next),
+ .data({
+ 2'd3, del_data[3*6+6-1:3*6],
+ 2'd2, del_data[2*6+6-1:2*6],
+ 2'd1, del_data[1*6+6-1:1*6],
+ 2'd0, del_data[0*6+6-1:0*6]}),
+ .result(int_addr_wire));
+
+ assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
+
+ lpm_mult #(
+ .lpm_hint("MAXIMIZE_SPEED=9"),
+ .lpm_representation("UNSIGNED"),
+ .lpm_type("LPM_MULT"),
+ .lpm_pipeline(3),
+ .lpm_widtha(width),
+ .lpm_widthb(16),
+ .lpm_widthp(width1)) mult_unit_1 (
+ .clock(clock),
+ .clken(int_wren_reg),
+ .dataa(inp_data_wire[4]),
+ .datab(tau_data_reg),
+ .result(mul_data_wire1));
+
+ lpm_mult #(
+ .lpm_hint("MAXIMIZE_SPEED=9"),
+ .lpm_representation("UNSIGNED"),
+ .lpm_type("LPM_MULT"),
+ .lpm_pipeline(3),
+ .lpm_widtha(width),
+ .lpm_widthb(6),
+ .lpm_widthp(width2)) mult_unit_2 (
+ .clock(clock),
+ .clken(int_wren_reg),
+ .dataa(inp_data_reg[0]),
+ .datab(amp_data_reg),
+ .result(mul_data_wire2));
+
+ assign add_data_wire =
+ {2'b0, mul_data_wire2, {(width1-width2){1'b0}}}
+ - {2'b0, mul_data_wire1};
+
+ assign out_data_wire = add_data_wire[width3-1] ? {(widthr){1'b0}} :
+ add_data_wire[shift+widthr-1:shift]
+ + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]};
+
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(256),
+ .numwords_b(256),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(8),
+ .widthad_b(8),
+ .width_a(width),
+ .width_b(width),
+ .width_byteena_a(1)) ram_unit_1 (
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .address_a(int_addr_reg),
+ .address_b({int_addr_wire[7:6], del_addr_wire}),
+ .data_a(inp_data_reg[0]),
+ .q_b(inp_data_wire[4]),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({(width){1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_flag_reg <= 1'b0;
+ int_chan_reg <= 2'd0;
+ int_case_reg <= 3'd0;
+ del_addr_reg <= 6'd0;
+ int_addr_reg <= 8'd0;
+ amp_data_reg <= 6'd0;
+ tau_data_reg <= 16'd0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_reg[i] <= {(width){1'b0}};
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ out_data_reg[i] <= {(widthr){1'b0}};
+ end
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_flag_reg <= int_flag_next;
+ int_chan_reg <= int_chan_next;
+ int_case_reg <= int_case_next;
+ del_addr_reg <= del_addr_next;
+ int_addr_reg <= int_addr_next;
+ amp_data_reg <= amp_data_next;
+ tau_data_reg <= tau_data_next;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_reg[i] <= inp_data_next[i];
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ out_data_reg[i] <= out_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_flag_next = int_flag_reg;
+ int_chan_next = int_chan_reg;
+ int_case_next = int_case_reg;
+ del_addr_next = del_addr_reg;
+ int_addr_next = int_addr_reg;
+ amp_data_next = amp_data_reg;
+ tau_data_next = tau_data_reg;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_next[i] = inp_data_reg[i];
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ out_data_next[i] = out_data_reg[i];
+ end
+
+ case (int_case_reg)
+ 0:
+ begin
+ // write zeros
+ int_wren_next = 1'b1;
+ del_addr_next = 6'd0;
+ int_addr_next = 8'd0;
+ amp_data_next = 6'd0;
+ tau_data_next = 16'd0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_next[i] = {(width){1'b0}};
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ out_data_next[i] = {(widthr){1'b0}};
+ end
+
+ int_case_next = 3'd1;
+ end
+ 1:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 8'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_flag_next = 1'b0;
+ int_chan_next = 2'd0;
+ int_case_next = 3'd2;
+ end
+ end
+ 2: // frame
+ begin
+ int_flag_next = 1'b0;
+ int_wren_next = frame;
+ if (frame)
+ begin
+ int_addr_next[7:6] = 2'd0;
+
+ // set read addr for 2nd pipeline
+ int_chan_next = 2'd1;
+
+ // register input data for 2nd, 3rd and 4th sums
+ inp_data_next[1] = inp_data_wire[1];
+ inp_data_next[2] = inp_data_wire[2];
+ inp_data_next[3] = inp_data_wire[3];
+
+ // prepare registers for 1st sum
+ inp_data_next[0] = inp_data_wire[0];
+
+ tau_data_next = tau_data_wire[0];
+ amp_data_next = amp_data_wire[0];
+
+ int_case_next = 3'd3;
+ end
+ if (int_flag_reg) // register 4th sum
+ begin
+ int_addr_next[5:0] = del_addr_reg;
+ // register 1st product
+ out_data_next[0] = out_data_wire;
+ end
+ end
+ 3: // 1st sum
+ begin
+ int_addr_next[7:6] = 2'd1;
+
+ // set read addr for 3rd pipeline
+ int_chan_next = 2'd2;
+
+ // prepare registers for 2nd sum
+ inp_data_next[0] = inp_data_reg[1];
+
+ tau_data_next = tau_data_wire[1];
+ amp_data_next = amp_data_wire[1];
+
+ // register 2nd product
+ out_data_next[1] = out_data_wire;
+
+ int_case_next = 3'd4;
+ end
+ 4: // 2nd sum
+ begin
+ int_addr_next[7:6] = 2'd2;
+
+ // set read addr for 4th pipeline
+ int_chan_next = 2'd3;
+
+ // prepare registers for 3rd sum
+ inp_data_next[0] = inp_data_reg[2];
+
+ tau_data_next = tau_data_wire[2];
+ amp_data_next = amp_data_wire[2];
+
+ // register 3rd product
+ out_data_next[2] = out_data_wire;
+
+ del_addr_next = del_addr_reg + 6'd1;
+
+ int_case_next = 3'd5;
+ end
+ 5: // 3rd sum
+ begin
+ int_flag_next = 1'b1;
+
+ int_addr_next[7:6] = 2'd3;
+
+ // set read addr for 1st pipeline
+ int_chan_next = 2'd0;
+
+ // prepare registers for 4th sum
+ inp_data_next[0] = inp_data_reg[3];
+
+ tau_data_next = tau_data_wire[3];
+ amp_data_next = amp_data_wire[3];
+
+ // register 4th product
+ out_data_next[3] = out_data_wire;
+
+ // register 4th output
+ out_data_next[4] = out_data_reg[0];
+
+ int_case_next = 3'd2;
+ end
+ default:
+ begin
+ int_case_next = 3'd0;
+ end
+ endcase
+ end
+
+ assign out_data = {out_data_reg[3], out_data_reg[2], out_data_reg[1], out_data_reg[4]};
+
+endmodule
Index: /trunk/3DEES/coincidence.v
===================================================================
--- /trunk/3DEES/coincidence.v (revision 177)
+++ /trunk/3DEES/coincidence.v (revision 177)
@@ -0,0 +1,79 @@
+module coincidence
+ #(
+ parameter input_width = 4,
+ parameter window_size = 10,
+ parameter output_width = 3
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [output_width-1:0] cfg_data,
+ input wire [input_width-1:0] trg_data,
+ output wire [output_width-1:0] coi_data,
+ output wire coi_flag
+ );
+
+ reg [window_size-1:0] coi_pipe_reg [input_width-1:0];
+ reg coi_flag_reg;
+
+ wire [output_width-1:0] coi_data_wire;
+ wire [input_width-1:0] int_data_wire;
+
+ integer i;
+ genvar j;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ coi_flag_reg <= 1'b0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ coi_pipe_reg[i] <= 0;
+ end
+ end
+ else if (frame)
+ begin
+ if (coi_data_wire >= cfg_data)
+ begin
+ coi_flag_reg <= 1'b1;
+ for(i = 0; i < input_width; i = i + 1)
+ begin
+ coi_pipe_reg[i] <= 0;
+ end
+ end
+ else
+ begin
+ coi_flag_reg <= 1'b0;
+ for(i = 0; i < input_width; i = i + 1)
+ begin
+ coi_pipe_reg[i] <= {coi_pipe_reg[i][window_size-2:0], trg_data[i]};
+ end
+ end
+ end
+ end
+
+ generate
+ for (j = 0; j < input_width; j = j + 1)
+ begin : INT_DATA
+ assign int_data_wire[j] = (|coi_pipe_reg[j]);
+ end
+ endgenerate
+
+ parallel_add #(
+ .msw_subtract("NO"),
+ .representation("UNSIGNED"),
+ .result_alignment("LSB"),
+ .pipeline(1),
+ .shift(0),
+ .size(input_width),
+ .width(1),
+ .widthr(output_width)) parallel_add_unit (
+ .clock(clock),
+ .data(int_data_wire),
+ .result(coi_data_wire));
+
+
+ assign coi_data = coi_data_wire;
+ assign coi_flag = coi_flag_reg;
+
+endmodule
Index: /trunk/3DEES/configuration.v
===================================================================
--- /trunk/3DEES/configuration.v (revision 177)
+++ /trunk/3DEES/configuration.v (revision 177)
@@ -0,0 +1,82 @@
+module configuration
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [5:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire [1023:0] cfg_bits
+ );
+
+ wire [63:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+ reg [15:0] int_miso_reg;
+
+ wire [1023:0] int_bits_wire;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 64; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(int_bits_wire[j*16+15:j*16]),
+ .aclr(),
+ .aload(),
+ .aset(),
+ .sload(),
+ .sset());
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(64),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(6)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(int_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(64),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(6)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cfg_bits = int_bits_wire;
+
+endmodule
Index: /trunk/3DEES/control.v
===================================================================
--- /trunk/3DEES/control.v (revision 177)
+++ /trunk/3DEES/control.v (revision 177)
@@ -0,0 +1,260 @@
+module control
+ (
+ input wire clock, reset,
+
+ input wire rx_empty, tx_full,
+ input wire [7:0] rx_data,
+
+ output wire rx_rdreq, tx_wrreq,
+ output wire [7:0] tx_data,
+
+ output wire bus_wren,
+ output wire [31:0] bus_addr,
+ output wire [15:0] bus_mosi,
+
+ input wire [15:0] bus_miso,
+ input wire bus_busy,
+
+ output wire led
+ );
+
+ reg [23:0] led_counter;
+
+ reg int_bus_wren;
+ reg [31:0] int_bus_addr;
+ reg [31:0] int_bus_cntr;
+ reg [15:0] int_bus_mosi;
+
+ reg int_rdreq, int_wrreq;
+ reg [7:0] int_data;
+ reg int_led;
+
+ reg [1:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ reg [4:0] state;
+
+ reg [31:0] address, counter;
+
+ reg [15:0] prefix;
+
+ wire [15:0] dest, data;
+
+ reg [7:0] buffer [3:0];
+
+ assign dest = {buffer[0], buffer[1]};
+ assign data = {buffer[2], buffer[3]};
+
+ always @(posedge clock)
+ begin
+ if (~rx_empty)
+ begin
+ int_led <= 1'b0;
+ led_counter <= 24'd0;
+ end
+ else
+ begin
+ if (&led_counter)
+ begin
+ int_led <= 1'b1;
+ end
+ else
+ begin
+ led_counter <= led_counter + 24'd1;
+ end
+ end
+
+ case(state)
+ 0:
+ begin
+ int_rdreq <= 1'b1;
+ int_wrreq <= 1'b0;
+ idle_counter <= 5'd0;
+ byte_counter <= 2'd0;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ // read 4 bytes
+ if (~rx_empty)
+ begin
+ idle_counter <= 5'd0;
+ byte_counter <= byte_counter + 2'd1;
+ buffer[byte_counter] <= rx_data;
+ if (&byte_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+ else if(|byte_counter)
+ begin
+ idle_counter <= idle_counter + 5'd1;
+ if (&idle_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+ end
+
+ 2:
+ begin
+ case (dest)
+ 16'h0000:
+ begin
+ // reset
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+
+ 16'h0001:
+ begin
+ // prefix register
+ prefix <= data;
+ state <= 5'd0;
+ end
+
+
+ 16'h0002:
+ begin
+ // address register
+ address <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0003:
+ begin
+ // counter register
+ counter <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0004:
+ begin
+ // single write
+ int_bus_addr <= address;
+ int_bus_mosi <= data;
+ int_bus_wren <= 1'b1;
+ prefix <= 16'd0;
+ state <= 5'd3;
+ end
+
+ 16'h0005:
+ begin
+ // multi read
+ int_bus_addr <= address;
+ int_bus_cntr <= counter;
+ int_bus_wren <= 1'b0;
+ prefix <= 16'd0;
+ state <= 5'd4;
+ end
+
+ default:
+ begin
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ // single write
+ 3:
+ begin
+ if (~bus_busy)
+ begin
+ int_bus_addr <= 32'd0;
+ int_bus_mosi <= 16'd0;
+ int_bus_wren <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+
+ // multi read
+ 4:
+ begin
+ if (bus_busy)
+ begin
+ buffer[0] <= 8'd1;
+ buffer[1] <= 8'd0;
+ int_bus_cntr <= 32'd0;
+ end
+ else
+ begin
+ buffer[0] <= 8'd0;
+ buffer[1] <= 8'd0;
+ end
+ state <= 5'd7;
+ end
+
+ 5:
+ begin
+ buffer[0] <= bus_miso[7:0];
+ buffer[1] <= bus_miso[15:8];
+ int_bus_addr <= int_bus_addr + 32'd1;
+ int_bus_cntr <= int_bus_cntr - 32'd1;
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_data <= buffer[0];
+ int_wrreq <= 1'b1;
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ if (~tx_full)
+ begin
+ int_data <= buffer[1];
+ state <= 5'd9;
+ end
+ end
+
+ 9:
+ begin
+ if (~tx_full)
+ begin
+ int_wrreq <= 1'b0;
+ state <= 5'd10;
+ end
+ end
+
+ 10:
+ begin
+ if (|int_bus_cntr)
+ begin
+ state <= 5'd5;
+ end
+ else
+ begin
+ state <= 5'd0;
+ end
+ end
+
+ default:
+ begin
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ assign bus_wren = int_bus_wren;
+ assign bus_addr = int_bus_addr;
+ assign bus_mosi = int_bus_mosi;
+ assign rx_rdreq = int_rdreq & (~rx_empty);
+ assign tx_wrreq = int_wrreq & (~tx_full);
+ assign tx_data = int_data;
+ assign led = int_led;
+
+endmodule
Index: /trunk/3DEES/counter.v
===================================================================
--- /trunk/3DEES/counter.v (revision 177)
+++ /trunk/3DEES/counter.v (revision 177)
@@ -0,0 +1,96 @@
+module counter
+ (
+ input wire clock, frame,
+
+ input wire reset, setup, count,
+
+ input wire bus_ssel, bus_wren,
+ input wire [1:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire cnt_good
+ );
+
+ wire [3:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+
+ reg cnt_good_reg;
+ reg [15:0] int_miso_reg;
+
+ wire [63:0] reg_bits_wire;
+ wire [63:0] cnt_bits_wire;
+
+ reg int_load_reg;
+
+ integer i;
+ genvar j;
+
+ lpm_counter #(
+ .lpm_direction("DOWN"),
+ .lpm_port_updown("PORT_UNUSED"),
+ .lpm_type("LPM_COUNTER"),
+ .lpm_width(64)) lpm_counter_component (
+ .sload(int_load_reg | setup),
+ .sclr(reset),
+ .clock(clock),
+ .data(reg_bits_wire),
+ .cnt_en((frame) & (count) & (|cnt_bits_wire)),
+ .q(cnt_bits_wire));
+
+ generate
+ for (j = 0; j < 4; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(reg_bits_wire[j*16+15:j*16]));
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(2)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(cnt_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(4),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(2)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ cnt_good_reg <= 1'b0;
+ int_load_reg <= 1'b0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ cnt_good_reg <= |cnt_bits_wire;
+ int_load_reg <= bus_ssel & bus_wren;
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cnt_good = cnt_good_reg;
+
+endmodule
Index: /trunk/3DEES/deconv.v
===================================================================
--- /trunk/3DEES/deconv.v (revision 177)
+++ /trunk/3DEES/deconv.v (revision 177)
@@ -0,0 +1,372 @@
+module deconv
+ #(
+ parameter shift = 24, // right shift of the result
+ parameter width = 27, // bit width of the input data
+ parameter widthr = 12 // bit width of the output data
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [4*6-1:0] del_data,
+ input wire [4*6-1:0] amp_data,
+ input wire [4*16-1:0] tau_data,
+ input wire [4*width-1:0] inp_data,
+ output wire [4*widthr-1:0] out_data
+ );
+
+ localparam width1 = width + 1;
+ localparam width2 = width + 6 + 1;
+ localparam width3 = width + 16 + 3;
+
+ reg int_wren_reg, int_wren_next;
+ reg int_flag_reg, int_flag_next;
+ reg [1:0] int_chan_reg, int_chan_next;
+ reg [2:0] int_case_reg, int_case_next;
+ reg [7:0] int_addr_reg, int_addr_next;
+
+ reg [5:0] del_addr_reg, del_addr_next;
+ wire [5:0] del_addr_wire;
+ wire [7:0] int_addr_wire;
+
+ reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0];
+ wire [widthr-1:0] out_data_wire;
+
+ wire [width3-1:0] add_data_wire;
+
+ wire [width3-1:0] mul_data_wire [1:0];
+
+ reg [width2-1:0] acc_data_reg [4:0], acc_data_next [4:0];
+ wire [width2-1:0] acc_data_wire;
+
+ wire [width1-1:0] sub_data_wire;
+
+ reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0];
+ wire [width-1:0] inp_data_wire [4:0];
+
+ reg [5:0] amp_data_reg, amp_data_next;
+ wire [5:0] amp_data_wire [3:0];
+
+ reg [15:0] tau_data_reg, tau_data_next;
+ wire [15:0] tau_data_wire [3:0];
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 4; j = j + 1)
+ begin : INT_DATA
+ assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
+ assign amp_data_wire[j] = amp_data[j*6+6-1:j*6];
+ assign tau_data_wire[j] = tau_data[j*16+16-1:j*16];
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(8),
+ .lpm_widths(2)) mux_unit_1 (
+ .sel(int_chan_next),
+ .data({
+ 2'd3, del_data[3*6+6-1:3*6],
+ 2'd2, del_data[2*6+6-1:2*6],
+ 2'd1, del_data[1*6+6-1:1*6],
+ 2'd0, del_data[0*6+6-1:0*6]}),
+ .result(int_addr_wire));
+
+ assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
+
+ assign sub_data_wire =
+ {{(width1-width){1'b0}}, inp_data_reg[0]}
+ - {{(width1-width){1'b0}}, inp_data_wire[4]};
+
+ assign acc_data_wire =
+ {{(width2-width1+1){sub_data_wire[width1-1]}}, sub_data_wire[width1-2:0]}
+ + acc_data_reg[0];
+
+ lpm_mult #(
+ .lpm_hint("MAXIMIZE_SPEED=9"),
+ .lpm_representation("SIGNED"),
+ .lpm_type("LPM_MULT"),
+ .lpm_pipeline(3),
+ .lpm_widtha(width1),
+ .lpm_widthb(17),
+ .lpm_widthp(width3)) mult_unit_1 (
+ .clock(clock),
+ .clken(int_wren_reg),
+ .dataa(sub_data_wire),
+ .datab({1'b0, tau_data_reg}),
+ .result(mul_data_wire[0]));
+
+ lpm_mult #(
+ .lpm_hint("MAXIMIZE_SPEED=9"),
+ .lpm_representation("UNSIGNED"),
+ .lpm_type("LPM_MULT"),
+ .lpm_pipeline(3),
+ .lpm_widtha(width2),
+ .lpm_widthb(6),
+ .lpm_widthp(width3)) mult_unit_2 (
+ .clock(clock),
+ .clken(int_wren_reg),
+ .dataa(acc_data_reg[0]),
+ .datab(amp_data_reg),
+ .result(mul_data_wire[1]));
+
+ assign add_data_wire =
+ mul_data_wire[0]
+ + mul_data_wire[1];
+
+ assign out_data_wire =
+ add_data_wire[shift+widthr-1:shift]
+ + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]};
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(256),
+ .numwords_b(256),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(8),
+ .widthad_b(8),
+ .width_a(width),
+ .width_b(width),
+ .width_byteena_a(1)) ram_unit_1 (
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .address_a(int_addr_reg),
+ .address_b({int_addr_wire[7:6], del_addr_wire}),
+ .data_a(inp_data_reg[0]),
+ .q_b(inp_data_wire[4]),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({(width){1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_flag_reg <= 1'b0;
+ int_chan_reg <= 2'd0;
+ int_case_reg <= 3'd0;
+ del_addr_reg <= 6'd0;
+ int_addr_reg <= 8'd0;
+ amp_data_reg <= 6'd0;
+ tau_data_reg <= 16'd0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_reg[i] <= {(width){1'b0}};
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ acc_data_reg[i] <= {(width2){1'b0}};
+ out_data_reg[i] <= {(widthr){1'b0}};
+ end
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_flag_reg <= int_flag_next;
+ int_chan_reg <= int_chan_next;
+ int_case_reg <= int_case_next;
+ del_addr_reg <= del_addr_next;
+ int_addr_reg <= int_addr_next;
+ amp_data_reg <= amp_data_next;
+ tau_data_reg <= tau_data_next;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_reg[i] <= inp_data_next[i];
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ acc_data_reg[i] <= acc_data_next[i];
+ out_data_reg[i] <= out_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_flag_next = int_flag_reg;
+ int_chan_next = int_chan_reg;
+ int_case_next = int_case_reg;
+ del_addr_next = del_addr_reg;
+ int_addr_next = int_addr_reg;
+ amp_data_next = amp_data_reg;
+ tau_data_next = tau_data_reg;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_next[i] = inp_data_reg[i];
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ acc_data_next[i] = acc_data_reg[i];
+ out_data_next[i] = out_data_reg[i];
+ end
+
+ case (int_case_reg)
+ 0:
+ begin
+ // write zeros
+ int_wren_next = 1'b1;
+ del_addr_next = 6'd0;
+ int_addr_next = 8'd0;
+ amp_data_next = 6'd0;
+ tau_data_next = 16'd0;
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ inp_data_next[i] = {(width){1'b0}};
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ acc_data_next[i] = {(width2){1'b0}};
+ out_data_next[i] = {(widthr){1'b0}};
+ end
+
+ int_case_next = 3'd1;
+ end
+ 1:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 8'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_flag_next = 1'b0;
+ int_chan_next = 2'd0;
+ int_case_next = 3'd2;
+ end
+ end
+ 2: // frame
+ begin
+ int_flag_next = 1'b0;
+ int_wren_next = frame;
+ if (frame)
+ begin
+ int_addr_next[7:6] = 2'd0;
+
+ // set read addr for 2nd pipeline
+ int_chan_next = 2'd1;
+
+ // register input data for 2nd, 3rd and 4th sums
+ inp_data_next[1] = inp_data_wire[1];
+ inp_data_next[2] = inp_data_wire[2];
+ inp_data_next[3] = inp_data_wire[3];
+
+ // prepare registers for 1st sum
+ inp_data_next[0] = inp_data_wire[0];
+ acc_data_next[0] = acc_data_reg[1];
+
+ tau_data_next = tau_data_wire[0];
+ amp_data_next = amp_data_wire[0];
+
+ int_case_next = 3'd3;
+ end
+ if (int_flag_reg) // register 4th sum
+ begin
+ int_addr_next[5:0] = del_addr_reg;
+ // register 4th sum and 1st product
+ acc_data_next[4] = acc_data_wire;
+ out_data_next[0] = out_data_wire;
+ end
+ end
+ 3: // 1st sum
+ begin
+ int_addr_next[7:6] = 2'd1;
+
+ // set read addr for 3rd pipeline
+ int_chan_next = 2'd2;
+
+ // prepare registers for 2nd sum
+ inp_data_next[0] = inp_data_reg[1];
+ acc_data_next[0] = acc_data_reg[2];
+
+ tau_data_next = tau_data_wire[1];
+ amp_data_next = amp_data_wire[1];
+
+ // register 1st sum and 2nd product
+ acc_data_next[1] = acc_data_wire;
+ out_data_next[1] = out_data_wire;
+
+ int_case_next = 3'd4;
+ end
+ 4: // 2nd sum
+ begin
+ int_addr_next[7:6] = 2'd2;
+
+ // set read addr for 4th pipeline
+ int_chan_next = 2'd3;
+
+ // prepare registers for 3rd sum
+ inp_data_next[0] = inp_data_reg[2];
+ acc_data_next[0] = acc_data_reg[3];
+
+ tau_data_next = tau_data_wire[2];
+ amp_data_next = amp_data_wire[2];
+
+ // register 2nd sum and 3rd product
+ acc_data_next[2] = acc_data_wire;
+ out_data_next[2] = out_data_wire;
+
+ del_addr_next = del_addr_reg + 6'd1;
+
+ int_case_next = 3'd5;
+ end
+ 5: // 3rd sum
+ begin
+ int_flag_next = 1'b1;
+
+ int_addr_next[7:6] = 2'd3;
+
+ // set read addr for 1st pipeline
+ int_chan_next = 2'd0;
+
+ // prepare registers for 4th sum
+ inp_data_next[0] = inp_data_reg[3];
+ acc_data_next[0] = acc_data_reg[4];
+
+ tau_data_next = tau_data_wire[3];
+ amp_data_next = amp_data_wire[3];
+
+ // register 3rd sum and 4th product
+ acc_data_next[3] = acc_data_wire;
+ out_data_next[3] = out_data_wire;
+
+ // register 4th output
+ out_data_next[4] = out_data_reg[0];
+
+ int_case_next = 3'd2;
+ end
+ default:
+ begin
+ int_case_next = 3'd0;
+ end
+ endcase
+ end
+
+ assign out_data = {out_data_reg[3], out_data_reg[2], out_data_reg[1], out_data_reg[4]};
+
+endmodule
Index: /trunk/3DEES/delay.v
===================================================================
--- /trunk/3DEES/delay.v (revision 177)
+++ /trunk/3DEES/delay.v (revision 177)
@@ -0,0 +1,37 @@
+module delay
+ #(
+ parameter width = 12,
+ parameter length = 32
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [width-1:0] inp_data,
+ output wire [width-1:0] out_data
+ );
+
+ reg [width-1:0] int_pipe_reg [length-1:0];
+
+ integer i;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ for(i = 0; i < length; i = i + 1)
+ begin
+ int_pipe_reg[i] <= 0;
+ end
+ end
+ else if (frame)
+ begin
+ for(i = 0; i <= 30; i = i + 1)
+ begin
+ int_pipe_reg[i+1] <= int_pipe_reg[i];
+ end
+ int_pipe_reg[0] <= inp_data;
+ end
+ end
+
+ assign out_data = int_pipe_reg[length-1];
+
+endmodule
Index: /trunk/3DEES/filter.v
===================================================================
--- /trunk/3DEES/filter.v (revision 177)
+++ /trunk/3DEES/filter.v (revision 177)
@@ -0,0 +1,242 @@
+module filter
+ #(
+ parameter size = 3, // number of channels
+ parameter width = 12 // bit width of the input data (unsigned)
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [size*width-1:0] inp_data,
+ output wire [size*widthr-1:0] out_data
+ );
+
+ localparam widthr = width + 8;
+ /*
+ 5-bit LFSR with additional bits to keep track of previous values
+ */
+ reg [31:0] int_lfsr_reg, int_lfsr_next;
+
+ reg int_wren_reg, int_wren_next;
+ reg int_flag_reg, int_flag_next;
+ reg int_chan_reg, int_chan_next;
+ reg [1:0] int_case_reg, int_case_next;
+ reg [5:0] int_addr_reg, int_addr_next;
+
+ wire [5:0] int_addr_wire;
+
+ reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0];
+ reg [size*widthr-1:0] int_data_reg [2:0], int_data_next [2:0];
+
+ wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : INT_DATA
+ assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
+
+ assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
+ acc_data_reg[0][j*widthr+widthr-1:j*widthr]
+ - del_data_wire[j*widthr+widthr-1:j*widthr]
+ + acc_data_reg[1][j*widthr+widthr-1:j*widthr];
+
+ end
+ endgenerate
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(64),
+ .numwords_b(64),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(6),
+ .widthad_b(6),
+ .width_a(size*widthr),
+ .width_b(size*widthr),
+ .width_byteena_a(1)) ram_unit_1 (
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .address_a(int_addr_reg),
+ .address_b(int_addr_wire),
+ .data_a(acc_data_reg[0]),
+ .q_b(del_data_wire),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({(size*widthr){1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+ lpm_mux #(
+ .lpm_size(2),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(6),
+ .lpm_widths(1)) mux_unit_1 (
+ .sel(int_chan_next),
+ .data({
+ 1'b1, int_lfsr_reg[20+4:20],
+ 1'b0, int_lfsr_reg[5+4:5]}),
+ .result(int_addr_wire));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_flag_reg <= 1'b0;
+ int_chan_reg <= 1'b0;
+ int_case_reg <= 2'd0;
+ int_addr_reg <= 6'd0;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_reg[i] <= {(size*widthr){1'b0}};
+ end
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ int_data_reg[i] <= {(size*widthr){1'b0}};
+ end
+ int_lfsr_reg <= 32'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_flag_reg <= int_flag_next;
+ int_chan_reg <= int_chan_next;
+ int_case_reg <= int_case_next;
+ int_addr_reg <= int_addr_next;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_reg[i] <= acc_data_next[i];
+ end
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ int_data_reg[i] <= int_data_next[i];
+ end
+ int_lfsr_reg <= int_lfsr_next;
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_flag_next = int_flag_reg;
+ int_chan_next = int_chan_reg;
+ int_case_next = int_case_reg;
+ int_addr_next = int_addr_reg;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_next[i] = acc_data_reg[i];
+ end
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ int_data_next[i] = int_data_reg[i];
+ end
+ int_lfsr_next = int_lfsr_reg;
+
+ case (int_case_reg)
+ 0:
+ begin
+ // write zeros
+ int_wren_next = 1'b1;
+ int_addr_next = 6'd0;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_next[i] = {(size*widthr){1'b0}};
+ end
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ int_data_next[i] = {(size*widthr){1'b0}};
+ end
+ int_case_next = 2'd1;
+ end
+ 1:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 6'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_flag_next = 1'b0;
+ int_chan_next = 1'b0;
+ int_lfsr_next = 32'h0722BDA6;
+ int_case_next = 'd2;
+ end
+ end
+ 2: // frame
+ begin
+ int_flag_next = 1'b0;
+ if (frame)
+ begin
+ int_wren_next = 1'b1;
+
+ int_addr_next = {1'b0, int_lfsr_reg[4:0]};
+
+ // set read addr for 2nd pipeline
+ int_chan_next = 1'b1;
+
+ // prepare registers for 1st sum
+ acc_data_next[0] = acc_data_wire[0];
+ acc_data_next[1] = int_data_reg[0];
+
+ int_lfsr_next = {int_lfsr_reg[30:0], int_lfsr_reg[2] ~^ int_lfsr_reg[4]};
+
+ int_case_next = 'd3;
+ end
+ if (int_flag_reg) // register 2nd sum
+ begin
+ // register 2nd sum
+ int_data_next[1] = acc_data_wire[1];
+ end
+ end
+ 3: // 2nd sum
+ begin
+ int_flag_next = 1'b1;
+
+ int_addr_next = {1'b1, int_lfsr_reg[5:1]};
+
+ // set read addr for 1st pipeline
+ int_chan_next = 1'b0;
+
+ // prepare registers for 2nd sum
+ acc_data_next[0] = int_data_reg[0];
+ acc_data_next[1] = int_data_reg[1];
+
+ // register 1st sum
+ int_data_next[0] = acc_data_wire[1];
+
+ // register 2nd output
+ int_data_next[2] = int_data_reg[1];
+
+ int_case_next = 2'd2;
+ end
+ default:
+ begin
+ int_case_next = 2'd0;
+ end
+ endcase
+ end
+
+ assign out_data = int_data_reg[2];
+
+endmodule
Index: /trunk/3DEES/histogram16.v
===================================================================
--- /trunk/3DEES/histogram16.v (revision 177)
+++ /trunk/3DEES/histogram16.v (revision 177)
@@ -0,0 +1,199 @@
+module histogram16
+ (
+ input wire clock, frame, reset,
+
+ input wire hst_good,
+ input wire [13:0] hst_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [13:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+ // signal declaration
+ reg [3:0] int_case_reg, int_case_next;
+ reg int_wren_reg, int_wren_next;
+ reg [13:0] int_addr_reg, int_addr_next;
+ reg [15:0] int_data_reg, int_data_next;
+
+ reg [13:0] bus_addr_reg, bus_addr_next;
+ reg [15:0] bus_miso_reg, bus_miso_next;
+
+ reg bus_wren_reg, bus_wren_next;
+ reg [15:0] bus_mosi_reg, bus_mosi_next;
+
+ wire [15:0] q_a_wire;
+ wire [15:0] q_b_wire;
+
+ altsyncram #(
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_a("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .indata_reg_b("CLOCK0"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(16384),
+ .numwords_b(16384),
+ .operation_mode("BIDIR_DUAL_PORT"),
+ .outdata_aclr_a("NONE"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_a("CLOCK0"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("OLD_DATA"),
+ .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
+ .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
+ .widthad_a(14),
+ .widthad_b(14),
+ .width_a(16),
+ .width_b(16),
+ .width_byteena_a(1),
+ .width_byteena_b(1),
+ .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .wren_b(bus_wren_reg),
+ .address_a(int_addr_reg),
+ .address_b(bus_addr_reg),
+ .data_a(int_data_reg),
+ .data_b(bus_mosi_reg),
+ .q_a(q_a_wire),
+ .q_b(q_b_wire),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .eccstatus(),
+ .rden_a(1'b1),
+ .rden_b(1'b1));
+
+ // body
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_addr_reg <= 14'd0;
+ int_data_reg <= 16'd0;
+ int_case_reg <= 4'b0;
+ bus_addr_reg <= 14'd0;
+ bus_miso_reg <= 16'd0;
+ bus_wren_reg <= 1'b0;
+ bus_mosi_reg <= 16'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_addr_reg <= int_addr_next;
+ int_data_reg <= int_data_next;
+ int_case_reg <= int_case_next;
+ bus_addr_reg <= bus_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_wren_reg <= bus_wren_next;
+ bus_mosi_reg <= bus_mosi_next;
+ end
+ end
+
+ always @*
+ begin
+ bus_addr_next = bus_addr_reg;
+ bus_miso_next = bus_miso_reg;
+
+ bus_wren_next = 1'b0;
+ bus_mosi_next = bus_mosi_reg;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = q_b_wire;
+ bus_addr_next = bus_addr;
+ bus_wren_next = bus_wren;
+ if (bus_wren)
+ begin
+ bus_mosi_next = bus_mosi;
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_addr_next = int_addr_reg;
+ int_data_next = int_data_reg;
+ int_case_next = int_case_reg;
+
+ case (int_case_reg)
+
+ 0:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 14'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_case_next = 4'd1;
+ end
+ end
+
+ 1:
+ begin
+ int_wren_next = 1'b0;
+/*
+ if (&int_data_reg)
+ begin
+ int_case_next = 4'd0;
+ end
+ else if (frame & hst_good)
+*/
+ if (frame & hst_good)
+ begin
+ int_addr_next = hst_data;
+ int_case_next = 4'd2;
+ end
+ end
+
+ 2:
+ begin
+ int_case_next = 4'd3;
+ end
+
+ 3:
+ begin
+ int_case_next = 4'd4;
+ end
+
+ 4:
+ begin
+ int_case_next = 4'd1;
+ if (~&q_a_wire)
+ begin
+ int_wren_next = 1'b1;
+ int_data_next = q_a_wire + 16'd1;
+ end
+ end
+
+ default:
+ begin
+ int_wren_next = 1'b0;
+ int_addr_next = 14'd0;
+ int_data_next = 16'd0;
+ int_case_next = 4'd0;
+ end
+ endcase
+ end
+
+ // output logic
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = 1'b0;
+endmodule
Index: /trunk/3DEES/histogram32.v
===================================================================
--- /trunk/3DEES/histogram32.v (revision 177)
+++ /trunk/3DEES/histogram32.v (revision 177)
@@ -0,0 +1,199 @@
+module histogram32
+ (
+ input wire clock, frame, reset,
+
+ input wire hst_good,
+ input wire [11:0] hst_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [12:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+ // signal declaration
+ reg [3:0] int_case_reg, int_case_next;
+ reg int_wren_reg, int_wren_next;
+ reg [11:0] int_addr_reg, int_addr_next;
+ reg [31:0] int_data_reg, int_data_next;
+
+ reg [12:0] bus_addr_reg, bus_addr_next;
+ reg [15:0] bus_miso_reg, bus_miso_next;
+
+ reg bus_wren_reg, bus_wren_next;
+ reg [15:0] bus_mosi_reg, bus_mosi_next;
+
+ wire [31:0] q_a_wire;
+ wire [15:0] q_b_wire;
+
+ altsyncram #(
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_a("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .indata_reg_b("CLOCK0"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(4096),
+ .numwords_b(8192),
+ .operation_mode("BIDIR_DUAL_PORT"),
+ .outdata_aclr_a("NONE"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_a("CLOCK0"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("OLD_DATA"),
+ .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
+ .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
+ .widthad_a(12),
+ .widthad_b(13),
+ .width_a(32),
+ .width_b(16),
+ .width_byteena_a(1),
+ .width_byteena_b(1),
+ .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .wren_b(bus_wren_reg),
+ .address_a(int_addr_reg),
+ .address_b(bus_addr_reg),
+ .data_a(int_data_reg),
+ .data_b(bus_mosi_reg),
+ .q_a(q_a_wire),
+ .q_b(q_b_wire),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .eccstatus(),
+ .rden_a(1'b1),
+ .rden_b(1'b1));
+
+ // body
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_addr_reg <= 12'd0;
+ int_data_reg <= 32'd0;
+ int_case_reg <= 4'b0;
+ bus_addr_reg <= 13'd0;
+ bus_miso_reg <= 16'd0;
+ bus_wren_reg <= 1'b0;
+ bus_mosi_reg <= 16'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_addr_reg <= int_addr_next;
+ int_data_reg <= int_data_next;
+ int_case_reg <= int_case_next;
+ bus_addr_reg <= bus_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_wren_reg <= bus_wren_next;
+ bus_mosi_reg <= bus_mosi_next;
+ end
+ end
+
+ always @*
+ begin
+ bus_addr_next = bus_addr_reg;
+ bus_miso_next = bus_miso_reg;
+
+ bus_wren_next = 1'b0;
+ bus_mosi_next = bus_mosi_reg;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = q_b_wire;
+ bus_addr_next = bus_addr;
+ bus_wren_next = bus_wren;
+ if (bus_wren)
+ begin
+ bus_mosi_next = bus_mosi;
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_addr_next = int_addr_reg;
+ int_data_next = int_data_reg;
+ int_case_next = int_case_reg;
+
+ case (int_case_reg)
+
+ 0:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 12'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_case_next = 4'd1;
+ end
+ end
+
+ 1:
+ begin
+ int_wren_next = 1'b0;
+/*
+ if (&int_data_reg)
+ begin
+ int_case_next = 4'd0;
+ end
+ else if (frame & hst_good)
+*/
+ if (frame & hst_good)
+ begin
+ int_addr_next = hst_data;
+ int_case_next = 4'd2;
+ end
+ end
+
+ 2:
+ begin
+ int_case_next = 4'd3;
+ end
+
+ 3:
+ begin
+ int_case_next = 4'd4;
+ end
+
+ 4:
+ begin
+ int_case_next = 4'd1;
+ if (~&q_a_wire)
+ begin
+ int_wren_next = 1'b1;
+ int_data_next = q_a_wire + 32'd1;
+ end
+ end
+
+ default:
+ begin
+ int_wren_next = 1'b0;
+ int_addr_next = 12'd0;
+ int_data_next = 32'd0;
+ int_case_next = 4'd0;
+ end
+ endcase
+ end
+
+ // output logic
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = 1'b0;
+endmodule
Index: /trunk/3DEES/i2c_fifo.v
===================================================================
--- /trunk/3DEES/i2c_fifo.v (revision 177)
+++ /trunk/3DEES/i2c_fifo.v (revision 177)
@@ -0,0 +1,219 @@
+module i2c_fifo
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [15:0] bus_mosi,
+
+ output wire bus_busy,
+
+ inout wire i2c_sda,
+ inout wire i2c_scl
+ );
+
+ wire int_rdempty, int_wrfull, i2c_clk, start, stop;
+ wire [15:0] int_q;
+
+ reg int_bus_busy;
+ reg int_rdreq, int_wrreq, int_clken, int_sdo, int_scl, int_ack;
+ reg [15:0] int_bus_mosi;
+ reg [15:0] int_data;
+ reg [9:0] counter;
+ reg [4:0] state;
+
+ assign i2c_sda = int_sdo ? 1'bz : 1'b0;
+ assign i2c_scl = int_scl | (int_clken ? counter[9] : 1'b0);
+
+ assign start = int_data[8];
+ assign stop = int_data[9];
+
+ scfifo #(
+ .add_ram_output_register("OFF"),
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("scfifo"),
+ .lpm_width(16),
+ .lpm_widthu(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF")) fifo_tx (
+ .rdreq((~int_rdempty) & (int_rdreq) & (&counter)),
+ .aclr(1'b0),
+ .clock(clock),
+ .wrreq(int_wrreq),
+ .data(int_bus_mosi),
+ .empty(int_rdempty),
+ .q(int_q),
+ .full(int_wrfull),
+ .almost_empty(),
+ .almost_full(),
+ .sclr(),
+ .usedw());
+
+ always @ (posedge clock)
+ begin
+ int_bus_busy <= int_wrfull;
+
+ if (bus_ssel)
+ begin
+ if (~int_wrfull & bus_wren)
+ begin
+ int_bus_mosi <= bus_mosi;
+ int_wrreq <= 1'b1;
+ end
+ end
+
+ if (~int_wrfull & int_wrreq)
+ begin
+ int_wrreq <= 1'b0;
+ end
+
+ end
+
+ always @ (posedge clock)
+ begin
+ counter <= counter + 10'd1;
+ if (&counter)
+ begin
+ case (state)
+ 0:
+ begin
+ int_ack <= 1'b0;
+ int_sdo <= 1'b1;
+ int_scl <= 1'b1;
+ int_rdreq <= 1'b1;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+
+ 2:
+ begin
+ if (start)
+ begin
+ int_sdo <= 1'b1;
+ int_scl <= 1'b1;
+ state <= 5'd3;
+ end
+ else
+ begin
+ state <= 5'd5;
+ end
+ end
+
+ 3:
+ begin // start
+ int_sdo <= 1'b0;
+ state <= 5'd4;
+ end
+
+ 4:
+ begin
+ int_scl <= 1'b0;
+ state <= 5'd5;
+ end
+
+ 5:
+ begin // data
+ int_clken <= 1'b1;
+ int_sdo <= int_data[7];
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ int_sdo <= int_data[6];
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_sdo <= int_data[5];
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ int_sdo <= int_data[4];
+ state <= 5'd9;
+ end
+
+ 9:
+ begin
+ int_sdo <= int_data[3];
+ state <= 5'd10;
+ end
+
+ 10:
+ begin
+ int_sdo <= int_data[2];
+ state <= 5'd11;
+ end
+
+ 11:
+ begin
+ int_sdo <= int_data[1];
+ state <= 5'd12;
+ end
+
+ 12:
+ begin
+ int_sdo <= int_data[0];
+ state <= 5'd13;
+ end
+
+ 13:
+ begin // ack
+ int_sdo <= 1'b1;
+ int_rdreq <= 1'b1;
+ state <= 5'd14;
+ end
+
+ 14:
+ begin
+ int_ack <= i2c_sda;
+ int_rdreq <= 1'b0;
+ if (stop | int_rdempty)
+ begin
+ int_clken <= 1'b0;
+ int_sdo <= 1'b0;
+ int_scl <= 1'b0;
+ state <= 5'd15;
+ end
+ else if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_sdo <= int_q[7];
+ state <= 5'd6;
+ end
+ end
+
+ 15:
+ begin // stop
+ int_scl <= 1'b1;
+ state <= 5'd16;
+ end
+
+ 16:
+ begin
+ int_sdo <= 1'b1;
+ state <= 5'd0;
+ end
+
+ endcase
+ end
+ end
+
+ // output logic
+ assign bus_busy = int_bus_busy;
+
+endmodule
Index: /trunk/3DEES/new_filter.v
===================================================================
--- /trunk/3DEES/new_filter.v (revision 177)
+++ /trunk/3DEES/new_filter.v (revision 177)
@@ -0,0 +1,276 @@
+module new_filter
+ #(
+ parameter size = 3, // number of channels
+ parameter width = 12 // bit width of the input data (unsigned)
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [size*width-1:0] inp_data,
+ output wire [size*widthr-1:0] out_data
+ );
+
+ localparam widthr = width + 9;
+ /*
+ 4-bit LFSR with additional bits to keep track of previous values
+ */
+ reg [15:0] int_lfsr_reg, int_lfsr_next;
+
+ reg int_wren_reg, int_wren_next;
+ reg int_flag_reg, int_flag_next;
+ reg [1:0] int_chan_reg, int_chan_next;
+ reg [2:0] int_case_reg, int_case_next;
+ reg [5:0] int_addr_reg, int_addr_next;
+
+ wire [5:0] int_addr_wire;
+
+ reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0];
+ reg [size*widthr-1:0] int_data_reg [4:0], int_data_next [4:0];
+
+ wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : INT_DATA
+ assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
+
+ assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
+ acc_data_reg[0][j*widthr+widthr-1:j*widthr]
+ - del_data_wire[j*widthr+widthr-1:j*widthr]
+ + acc_data_reg[1][j*widthr+widthr-1:j*widthr];
+
+ end
+ endgenerate
+
+ altsyncram #(
+ .address_aclr_b("NONE"),
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(64),
+ .numwords_b(64),
+ .operation_mode("DUAL_PORT"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("DONT_CARE"),
+ .widthad_a(6),
+ .widthad_b(6),
+ .width_a(size*widthr),
+ .width_b(size*widthr),
+ .width_byteena_a(1)) ram_unit_1 (
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .address_a(int_addr_reg),
+ .address_b(int_addr_wire),
+ .data_a(acc_data_reg[0]),
+ .q_b(del_data_wire),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({(size*widthr){1'b1}}),
+ .eccstatus(),
+ .q_a(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0));
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(6),
+ .lpm_widths(2)) mux_unit_1 (
+ .sel(int_chan_next),
+ .data({
+ 2'd3, int_lfsr_reg[5+3:5],
+ 2'd2, int_lfsr_reg[4+3:4],
+ 2'd1, int_lfsr_reg[4+3:4],
+ 2'd0, int_lfsr_reg[3+3:3]}),
+ .result(int_addr_wire));
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_flag_reg <= 1'b0;
+ int_chan_reg <= 2'd0;
+ int_case_reg <= 3'd0;
+ int_addr_reg <= 6'd0;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_reg[i] <= {(size*widthr){1'b0}};
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ int_data_reg[i] <= {(size*widthr){1'b0}};
+ end
+ int_lfsr_reg <= 16'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_flag_reg <= int_flag_next;
+ int_chan_reg <= int_chan_next;
+ int_case_reg <= int_case_next;
+ int_addr_reg <= int_addr_next;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_reg[i] <= acc_data_next[i];
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ int_data_reg[i] <= int_data_next[i];
+ end
+ int_lfsr_reg <= int_lfsr_next;
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_flag_next = int_flag_reg;
+ int_chan_next = int_chan_reg;
+ int_case_next = int_case_reg;
+ int_addr_next = int_addr_reg;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_next[i] = acc_data_reg[i];
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ int_data_next[i] = int_data_reg[i];
+ end
+ int_lfsr_next = int_lfsr_reg;
+
+ case (int_case_reg)
+ 0:
+ begin
+ // write zeros
+ int_wren_next = 1'b1;
+ int_addr_next = 6'd0;
+ for(i = 0; i <= 1; i = i + 1)
+ begin
+ acc_data_next[i] = {(size*widthr){1'b0}};
+ end
+ for(i = 0; i <= 4; i = i + 1)
+ begin
+ int_data_next[i] = {(size*widthr){1'b0}};
+ end
+ int_case_next = 3'd1;
+ end
+ 1:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 6'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_flag_next = 1'b0;
+ int_chan_next = 2'd0;
+ int_lfsr_next = 16'h7650;
+ int_case_next = 3'd2;
+ end
+ end
+ 2: // frame
+ begin
+ int_flag_next = 1'b0;
+ if (frame)
+ begin
+ int_wren_next = 1'b1;
+
+ int_addr_next = {2'd0, int_lfsr_reg[3:0]};
+
+ // set read addr for 2nd pipeline
+ int_chan_next = 2'd1;
+
+ // prepare registers for 1st sum
+ acc_data_next[0] = acc_data_wire[0];
+ acc_data_next[1] = int_data_reg[0];
+
+ int_case_next = 3'd3;
+ end
+ if (int_flag_reg) // register 4th sum
+ begin
+ // register 4th sum
+ int_data_next[3] = acc_data_wire[1];
+ end
+ end
+ 3: // 1st sum
+ begin
+ int_addr_next = {2'd1, int_lfsr_reg[3:0]};
+
+ // set read addr for 3rd pipeline
+ int_chan_next = 2'd2;
+
+ // prepare registers for 2nd sum
+ acc_data_next[0] = int_data_reg[0];
+ acc_data_next[1] = int_data_reg[1];
+
+ // register 1st sum
+ int_data_next[0] = acc_data_wire[1];
+
+ int_case_next = 3'd4;
+ end
+ 4: // 2nd sum
+ begin
+ int_addr_next = {2'd2, int_lfsr_reg[3:0]};
+
+ // set read addr for 4th pipeline
+ int_chan_next = 2'd3;
+
+ // prepare registers for 3rd sum
+ acc_data_next[0] = int_data_reg[1];
+ acc_data_next[1] = int_data_reg[2];
+
+ // register 2nd sum
+ int_data_next[1] = acc_data_wire[1];
+
+ int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
+
+ int_case_next = 3'd5;
+ end
+ 5: // 3rd sum
+ begin
+ int_flag_next = 1'b1;
+
+ int_addr_next = {2'd3, int_lfsr_reg[4:1]};
+
+ // set read addr for 1st pipeline
+ int_chan_next = 2'd0;
+
+ // prepare registers for 4th sum
+ acc_data_next[0] = int_data_reg[2];
+ acc_data_next[1] = int_data_reg[3];
+
+ // register 3rd sum
+ int_data_next[2] = acc_data_wire[1];
+
+ // register 4th output
+ int_data_next[4] = int_data_reg[3];
+
+ int_case_next = 3'd2;
+ end
+ default:
+ begin
+ int_case_next = 3'd0;
+ end
+ endcase
+ end
+
+ assign out_data = int_data_reg[4];
+
+endmodule
Index: /trunk/3DEES/oscilloscope.v
===================================================================
--- /trunk/3DEES/oscilloscope.v (revision 177)
+++ /trunk/3DEES/oscilloscope.v (revision 177)
@@ -0,0 +1,246 @@
+module oscilloscope
+ (
+ input wire clock, frame, reset,
+
+ input wire cfg_data,
+
+ input wire trg_flag,
+
+ input wire [63:0] osc_data,
+
+ output wire ram_wren,
+ output wire [19:0] ram_addr,
+ inout wire [17:0] ram_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [19:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+
+ reg [63:0] osc_data_reg, osc_data_next;
+
+ reg [2:0] int_case_reg, int_case_next;
+
+ reg int_trig_reg, int_trig_next;
+ reg [19:0] int_trig_addr_reg, int_trig_addr_next;
+
+ reg [19:0] int_cntr_reg [1:0];
+ reg [19:0] int_cntr_next [1:0];
+
+ reg [15:0] bus_miso_reg, bus_miso_next;
+ reg bus_busy_reg, bus_busy_next;
+
+ reg ram_wren_reg [2:0];
+ reg ram_wren_next [2:0];
+
+ reg [17:0] ram_data_reg [2:0];
+ reg [17:0] ram_data_next [2:0];
+
+ reg [19:0] ram_addr_reg, ram_addr_next;
+
+ wire [17:0] ram_wren_wire;
+
+ assign ram_wren = ~ram_wren_reg[0];
+ assign ram_addr = ram_addr_reg;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 18; j = j + 1)
+ begin : SRAM_WREN
+ assign ram_wren_wire[j] = ram_wren_reg[2];
+ assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz;
+ end
+ endgenerate
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ osc_data_reg <= 64'd0;
+ ram_addr_reg <= 20'd0;
+ bus_miso_reg <= 16'd0;
+ bus_busy_reg <= 1'b0;
+ int_case_reg <= 5'd0;
+ int_cntr_reg[0] <= 20'd0;
+ int_cntr_reg[1] <= 20'd0;
+ int_trig_reg <= 1'b0;
+ int_trig_addr_reg <= 20'd0;
+
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ ram_wren_reg[i] <= 1'b0;
+ ram_data_reg[i] <= 16'd0;
+ end
+ end
+ else
+ begin
+ osc_data_reg <= osc_data_next;
+ ram_addr_reg <= ram_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_busy_reg <= bus_busy_next;
+ int_case_reg <= int_case_next;
+ int_cntr_reg[0] <= int_cntr_next[0];
+ int_cntr_reg[1] <= int_cntr_next[1];
+ int_trig_reg <= int_trig_next;
+ int_trig_addr_reg <= int_trig_addr_next;
+
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ ram_wren_reg[i] <= ram_wren_next[i];
+ ram_data_reg[i] <= ram_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+
+ osc_data_next = osc_data_reg;
+ ram_addr_next = ram_addr_reg;
+ bus_miso_next = bus_miso_reg;
+ bus_busy_next = bus_busy_reg;
+ int_case_next = int_case_reg;
+ int_cntr_next[0] = int_cntr_reg[0];
+ int_cntr_next[1] = int_cntr_reg[1];
+ int_trig_next = int_trig_reg;
+ int_trig_addr_next = int_trig_addr_reg;
+
+ for(i = 0; i < 2; i = i + 1)
+ begin
+ ram_wren_next[i+1] = ram_wren_reg[i];
+ ram_data_next[i+1] = ram_data_reg[i];
+ end
+ ram_wren_next[0] = 1'b0;
+ ram_data_next[0] = 18'd0;
+
+ case (int_case_reg)
+ 0:
+ begin
+ bus_busy_next = 1'b0;
+ int_cntr_next[0] = 20'd0;
+ int_cntr_next[1] = 20'd0;
+ int_trig_next = 1'b0;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = ram_data[15:0];
+ ram_wren_next[0] = bus_wren;
+ if (bus_wren)
+ begin
+ ram_addr_next = bus_addr;
+ ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0};
+ end
+ else
+ begin
+ ram_addr_next = int_trig_addr_reg + bus_addr;
+// ram_addr_next = bus_addr;
+ end
+ end
+ else if (cfg_data)
+ begin
+ // start recording
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = 18'd0;
+ ram_addr_next = 20'd0;
+ bus_busy_next = 1'b1;
+ int_case_next = 3'd1;
+ int_trig_addr_next = 20'd0;
+// int_cntr_next[0] = {cfg_data[7:0], 10'd0};
+ int_cntr_next[0] = 20'd262143;
+// int_cntr_next[1] = {cfg_data[15:8], 10'd0};
+ int_cntr_next[1] = 20'd5000;
+ end
+
+ end
+
+ // write zeros
+ 1:
+ begin
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = 18'd2;
+ if(&ram_addr_reg)
+ begin
+ int_case_next = 3'd2;
+ end
+ else
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ end
+ end
+
+ // sample recording
+ 2:
+ begin
+ if (frame)
+ begin
+ osc_data_next = osc_data;
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {2'd0, osc_data[15:0]};
+
+ int_case_next = 3'd3;
+
+ if (|int_cntr_reg[1])
+ begin
+ int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+ int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
+ end
+ else if (int_trig_reg)
+ begin
+ if (|int_cntr_reg[0])
+ begin
+ int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+ end
+ end
+ else if (trg_flag)
+ begin
+ int_trig_next = 1'b1;
+ int_trig_addr_next = ram_addr_reg - 20'd19999;
+ end
+ end
+ end
+
+ 3:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {2'd0, osc_data_reg[31:16]};
+ int_case_next = 3'd4;
+ end
+
+ 4:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {2'd0, osc_data_reg[47:32]};
+ int_case_next = 3'd5;
+ end
+
+ 5:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {2'd0, osc_data_reg[63:48]};
+ if (|int_cntr_reg[0])
+ begin
+ int_case_next = 3'd2;
+ end
+ else
+ begin
+ int_case_next = 3'd0;
+ end
+ end
+
+ endcase
+ end
+
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = bus_busy_reg;
+
+endmodule
Index: /trunk/3DEES/pwm.v
===================================================================
--- /trunk/3DEES/pwm.v (revision 177)
+++ /trunk/3DEES/pwm.v (revision 177)
@@ -0,0 +1,31 @@
+module pwm
+ (
+ input wire clock,
+ input wire [47:0] cfg_data,
+ output wire [3:0] out_data
+
+ );
+
+ reg [12:0] int_data_reg [3:0];
+ wire [11:0] cfg_data_wire [3:0];
+
+ integer i;
+ genvar j;
+
+ always @ (posedge clock)
+ begin
+ for(i = 0; i <= 3; i = i + 1)
+ begin
+ int_data_reg[i] <= {1'b0, int_data_reg[i][11:0]} + {1'b0, cfg_data_wire[i]};
+ end
+ end
+
+ generate
+ for (j = 0; j <= 3; j = j + 1)
+ begin : PWM_DATA
+ assign cfg_data_wire[j] = cfg_data[j*12+11:j*12];
+ assign out_data[j] = int_data_reg[j][12] ? 1'bz : 1'b0;
+ end
+ endgenerate
+
+endmodule
Index: /trunk/3DEES/spi_fifo.v
===================================================================
--- /trunk/3DEES/spi_fifo.v (revision 177)
+++ /trunk/3DEES/spi_fifo.v (revision 177)
@@ -0,0 +1,128 @@
+module spi_fifo
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [15:0] bus_mosi,
+
+ output wire bus_busy,
+
+ output wire [1:0] spi_sel,
+ output wire spi_sdo,
+ output wire spi_clk
+ );
+
+ wire int_rdempty, int_wrfull;
+ wire [31:0] int_q;
+
+ reg int_bus_busy;
+ reg int_rdreq, int_wrreq;
+ reg int_clken, int_sdo;
+ reg [1:0] int_sel;
+ reg [15:0] int_bus_mosi;
+ reg [31:0] int_data;
+ reg [2:0] clk_cntr;
+ reg [4:0] bit_cntr;
+ reg [1:0] state;
+
+ dcfifo_mixed_widths #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(16),
+ .lpm_widthu(4),
+ .lpm_width_r(32),
+ .lpm_widthu_r(3),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("ON")) fifo_tx (
+ .data(int_bus_mosi),
+ .rdclk(clock),
+ .rdreq((~int_rdempty) & (int_rdreq) & (&clk_cntr)),
+ .wrclk(clock),
+ .wrreq(int_wrreq),
+ .q(int_q),
+ .rdempty(int_rdempty),
+ .wrfull(int_wrfull));
+
+ always @ (posedge clock)
+ begin
+ int_bus_busy <= int_wrfull;
+
+ if (bus_ssel)
+ begin
+ if (~int_wrfull & bus_wren)
+ begin
+ int_bus_mosi <= bus_mosi;
+ int_wrreq <= 1'b1;
+ end
+ end
+
+ if (~int_wrfull & int_wrreq)
+ begin
+ int_wrreq <= 1'b0;
+ end
+
+ end
+
+ always @ (posedge clock)
+ begin
+ clk_cntr <= clk_cntr + 3'd1;
+ if (&clk_cntr)
+ begin
+ case (state)
+ 0:
+ begin
+ int_sdo <= 1'b0;
+ int_sel <= 2'b11;
+ int_clken <= 1'b0;
+ int_rdreq <= 1'b1;
+ state <= 2'd1;
+ end
+
+ 1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_rdreq <= 1'b0;
+ int_data <= {int_q[15:0], int_q[31:16]};
+ bit_cntr <= 5'd0;
+ state <= 2'd2;
+ end
+ end
+
+
+ 2:
+ begin // data
+ int_clken <= 1'b1;
+ int_sel <= int_data[25:24];
+ int_sdo <= int_data[23];
+ int_data[23:0] <= {int_data[22:0], 1'b0};
+ bit_cntr <= bit_cntr + 5'd1;
+ if (bit_cntr == 5'd23)
+ begin
+ state <= 2'd3;
+ end
+ end
+
+ 3:
+ begin
+ int_sdo <= 1'b0;
+ int_clken <= 1'b0;
+ state <= 2'd0;
+ end
+
+ endcase
+ end
+ end
+
+ // output logic
+ assign bus_busy = int_bus_busy;
+ assign spi_clk = (int_clken ? clk_cntr[2] : 1'b1);
+ assign spi_sdo = int_sdo;
+ assign spi_sel = int_sel;
+
+endmodule
Index: /trunk/3DEES/sys_pll.v
===================================================================
--- /trunk/3DEES/sys_pll.v (revision 177)
+++ /trunk/3DEES/sys_pll.v (revision 177)
@@ -0,0 +1,145 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: sys_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sys_pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 10,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 17,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+endmodule
Index: /trunk/3DEES/test.mif
===================================================================
--- /trunk/3DEES/test.mif (revision 177)
+++ /trunk/3DEES/test.mif (revision 177)
@@ -0,0 +1,2584 @@
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- Quartus II generated Memory Initialization File (.mif)
+
+WIDTH=12;
+DEPTH=2560;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
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+09BD : 1185;
+09BE : 1185;
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+09C3 : 1184;
+09C4 : 1184;
+09C5 : 1185;
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+09CF : 1184;
+09D0 : 1183;
+09D1 : 1183;
+09D2 : 1183;
+09D3 : 1183;
+09D4 : 1183;
+09D5 : 1183;
+09D6 : 1182;
+09D7 : 1182;
+09D8 : 1182;
+09D9 : 1183;
+09DA : 1183;
+09DB : 1182;
+09DC : 1182;
+09DD : 1182;
+09DE : 1183;
+09DF : 1182;
+09E0 : 1181;
+09E1 : 1181;
+09E2 : 1182;
+09E3 : 1183;
+09E4 : 1182;
+09E5 : 1181;
+09E6 : 1181;
+09E7 : 1181;
+09E8 : 1182;
+09E9 : 1182;
+09EA : 1180;
+09EB : 1181;
+09EC : 1182;
+09ED : 1181;
+09EE : 1181;
+09EF : 1181;
+09F0 : 1181;
+09F1 : 1181;
+09F2 : 1181;
+09F3 : 1181;
+09F4 : 1181;
+09F5 : 1180;
+09F6 : 1181;
+09F7 : 1182;
+09F8 : 1181;
+09F9 : 1180;
+09FA : 1180;
+09FB : 1181;
+09FC : 1181;
+09FD : 1182;
+09FE : 1179;
+09FF : 1180;
+END;
Index: /trunk/3DEES/test.v
===================================================================
--- /trunk/3DEES/test.v (revision 177)
+++ /trunk/3DEES/test.v (revision 177)
@@ -0,0 +1,61 @@
+module test
+ (
+ input wire clock,
+ output wire [11:0] data
+ );
+
+ reg [11:0] int_addr;
+
+ always @(posedge clock)
+ begin
+ if (int_addr == 12'd2559)
+ begin
+ int_addr <= 12'd0;
+ end
+ else
+ begin
+ int_addr <= int_addr + 12'd1;
+ end
+
+ end
+
+ altsyncram #(
+ .address_aclr_a("NONE"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_output_a("BYPASS"),
+ .init_file("test.mif"),
+ .intended_device_family("Cyclone III"),
+ .lpm_hint("ENABLE_RUNTIME_MOD=NO"),
+ .lpm_type("altsyncram"),
+ .numwords_a(2560),
+ .operation_mode("ROM"),
+ .outdata_aclr_a("NONE"),
+ .outdata_reg_a("CLOCK0"),
+ .widthad_a(12),
+ .width_a(12),
+ .width_byteena_a(1)) test_rom_unit (
+ .clock0(clock),
+ .address_a(int_addr),
+ .q_a(data),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .address_b(1'b1),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_a({12{1'b1}}),
+ .data_b(1'b1),
+ .eccstatus(),
+ .q_b(),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_a(1'b0),
+ .wren_b(1'b0));
+
+endmodule
Index: /trunk/3DEES/trigger.v
===================================================================
--- /trunk/3DEES/trigger.v (revision 177)
+++ /trunk/3DEES/trigger.v (revision 177)
@@ -0,0 +1,32 @@
+module trigger
+ (
+ input wire clock, frame, reset,
+ input wire [11:0] cfg_data,
+ input wire [11:0] trg_data,
+ output wire trg_flag
+ );
+
+ reg trg_flag_reg;
+ reg [11:0] cfg_data_reg;
+ reg [11:0] trg_data_reg;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ trg_flag_reg <= 1'b0;
+ end
+ else
+ begin
+ if (frame)
+ begin
+ cfg_data_reg <= cfg_data;
+ trg_data_reg <= trg_data;
+ end
+ trg_flag_reg <= (trg_data_reg >= cfg_data_reg);
+ end
+ end
+
+ assign trg_flag = trg_flag_reg;
+
+endmodule
Index: /trunk/3DEES/usb_fifo.v
===================================================================
--- /trunk/3DEES/usb_fifo.v (revision 177)
+++ /trunk/3DEES/usb_fifo.v (revision 177)
@@ -0,0 +1,121 @@
+module usb_fifo
+ (
+ input wire usb_clock,
+ inout wire [7:0] usb_data,
+ input wire usb_full, usb_empty,
+ output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
+ output wire usb_addr,
+
+ input wire clock,
+ input wire tx_wrreq, rx_rdreq,
+ input wire [7:0] tx_data,
+ output wire tx_full, rx_empty,
+ output wire [7:0] rx_q
+ );
+
+ wire int_rx_full, int_tx_empty;
+ wire rx_ready, tx_ready;
+ wire int_rdreq, int_wrreq, int_pktend;
+ reg is_rx_addr_ok;
+ reg [8:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ wire [7:0] int_rx_data = usb_data;
+ wire [7:0] int_tx_q;
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF"),
+ .write_aclr_synch("OFF")) fifo_tx (
+ .aclr(1'b0),
+ .data(tx_data),
+ .rdclk(usb_clock),
+ .rdreq(int_wrreq),
+ .wrclk(clock),
+ .wrreq(tx_wrreq),
+ .q(int_tx_q),
+ .rdempty(int_tx_empty),
+ .wrfull(tx_full),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF"),
+ .write_aclr_synch("OFF")) fifo_rx (
+ .aclr(1'b0),
+ .data(int_rx_data),
+ .rdclk(clock),
+ .rdreq(rx_rdreq),
+ .wrclk(usb_clock),
+ .wrreq(int_rdreq),
+ .q(rx_q),
+ .rdempty(rx_empty),
+ .wrfull(int_rx_full),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ assign rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);
+ assign tx_ready = (~rx_ready) & (~usb_full) & (~int_tx_empty) & (~int_pktend);
+
+ assign int_rdreq = (rx_ready) & (is_rx_addr_ok);
+ assign int_wrreq = (tx_ready) & (~is_rx_addr_ok);
+
+ assign int_pktend = (&idle_counter);
+
+ always @ (posedge usb_clock)
+ begin
+ // respect 1 clock delay between fifo selection
+ // and data transfer operations
+ is_rx_addr_ok <= rx_ready;
+
+ // assert pktend if buffer contains unsent data
+ // and fifo_tx_unit stays empty for more than 30 clocks
+ if (int_pktend)
+ begin
+ byte_counter <= 9'd0;
+ idle_counter <= 5'd0;
+ end
+ else if (int_wrreq)
+ begin
+ byte_counter <= byte_counter + 9'd1;
+ idle_counter <= 5'd0;
+ end
+ else if ((|byte_counter) & (int_tx_empty) & (~rx_ready))
+ begin
+ byte_counter <= byte_counter;
+ idle_counter <= idle_counter + 5'd1;
+ end
+
+ end
+
+ assign usb_pktend = int_pktend;
+ assign usb_rdreq = int_rdreq;
+ assign usb_wrreq = int_wrreq;
+ assign usb_rden = int_rdreq;
+ assign usb_addr = rx_ready;
+ assign usb_data = int_wrreq ? int_tx_q : 8'bz;
+
+endmodule
Index: /trunk/3DEES/uwt_bior31.v
===================================================================
--- /trunk/3DEES/uwt_bior31.v (revision 177)
+++ /trunk/3DEES/uwt_bior31.v (revision 177)
@@ -0,0 +1,111 @@
+module uwt_bior31
+ #(
+ parameter level = 1, // transform level
+ parameter width = 12 // bit width of the input data (unsigned)
+
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [width-1:0] inp_data,
+ output wire [widthr-1:0] out_data,
+ output wire [1:0] out_flag
+ );
+
+ localparam widthr = width + 3;
+
+ localparam index1 = 1 << (level - 1);
+ localparam index2 = 2 << (level - 1);
+ localparam index3 = 3 << (level - 1);
+
+ // Tapped delay line
+ reg [width-1:0] tap_data_reg [index3:0], tap_data_next [index3:0];
+
+ wire [1:0] int_comp_wire;
+ reg [1:0] int_comp_reg, int_comp_next;
+
+ reg [1:0] out_flag_reg, out_flag_next;
+
+ wire [widthr-1:0] add_data_wire [1:0];
+ reg [widthr-1:0] add_data_reg [1:0], add_data_next [1:0];
+
+ reg [widthr-1:0] out_data_reg, out_data_next;
+
+ integer i;
+
+ assign add_data_wire[0] = tap_data_reg[index3] + {tap_data_reg[index2][width-2:0], 1'b0} + tap_data_reg[index2];
+ assign add_data_wire[1] = {tap_data_reg[index1][width-2:0], 1'b0} + tap_data_reg[index1] + tap_data_reg[0];
+ assign int_comp_wire[0] = (add_data_reg[0] > add_data_reg[1]);
+ assign int_comp_wire[1] = (add_data_reg[0] < add_data_reg[1]);
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ add_data_reg[0] <= {(widthr){1'b0}};
+ add_data_reg[1] <= {(widthr){1'b0}};
+ out_data_reg <= {(widthr){1'b0}};
+ int_comp_reg <= 2'd0;
+ out_flag_reg <= 2'd0;
+
+ for(i = 0; i <= index3; i = i + 1)
+ begin
+ tap_data_reg[i] <= {(width){1'b0}};
+ end
+ end
+ else
+ begin
+ add_data_reg[0] <= add_data_next[0];
+ add_data_reg[1] <= add_data_next[1];
+ out_data_reg <= out_data_next;
+ int_comp_reg <= int_comp_next;
+ out_flag_reg <= out_flag_next;
+
+ for(i = 0; i <= index3; i = i + 1)
+ begin
+ tap_data_reg[i] <= tap_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ add_data_next[0] = add_data_reg[0];
+ add_data_next[1] = add_data_reg[1];
+ out_data_next = out_data_reg;
+ int_comp_next = int_comp_reg;
+ out_flag_next = out_flag_reg;
+
+ for(i = 0; i <= index3; i = i + 1)
+ begin
+ tap_data_next[i] = tap_data_reg[i];
+ end
+
+ if (frame)
+ begin
+ // Tapped delay line: shift one
+ for(i = 0; i < index3; i = i + 1)
+ begin
+ tap_data_next[i+1] = tap_data_reg[i];
+ end
+
+ // Input in register 0
+ tap_data_next[0] = inp_data;
+
+ add_data_next[0] = add_data_wire[0];
+ add_data_next[1] = add_data_wire[1];
+
+ out_data_next = add_data_next[0] + add_data_next[1];
+
+ int_comp_next = int_comp_wire;
+ out_flag_next[0] = (~int_comp_reg[0]) & (int_comp_wire[0]);
+ out_flag_next[1] = (~int_comp_reg[1]) & (int_comp_wire[1]);
+
+ end
+
+ end
+
+ // output logic
+ assign out_data = out_data_reg;
+ assign out_flag = out_flag_reg;
+
+endmodule