Index: /trunk/MultiChannelUSB/histogram16.v
===================================================================
--- /trunk/MultiChannelUSB/histogram16.v	(revision 163)
+++ /trunk/MultiChannelUSB/histogram16.v	(revision 164)
@@ -4,8 +4,8 @@
 		
 		input	wire			hst_good,
-		input	wire	[11:0]  hst_data,
+		input	wire	[13:0]  hst_data,
 
 		input	wire			bus_ssel, bus_wren,
-		input	wire	[11:0]	bus_addr,
+		input	wire	[13:0]	bus_addr,
 		input	wire	[15:0]	bus_mosi,
 
@@ -17,8 +17,8 @@
 	reg		[3:0]	int_case_reg, int_case_next;
 	reg				int_wren_reg, int_wren_next;
-	reg		[11:0]	int_addr_reg, int_addr_next;
+	reg		[13:0]	int_addr_reg, int_addr_next;
 	reg		[15:0]	int_data_reg, int_data_next;
 
-	reg		[11:0]	bus_addr_reg, bus_addr_next;
+	reg		[13:0]	bus_addr_reg, bus_addr_next;
 	reg		[15:0]	bus_miso_reg, bus_miso_next;
 
@@ -38,6 +38,6 @@
 		.intended_device_family("Cyclone III"),
 		.lpm_type("altsyncram"),
-		.numwords_a(4096),
-		.numwords_b(4096),
+		.numwords_a(10000),
+		.numwords_b(10000),
 		.operation_mode("BIDIR_DUAL_PORT"),
 		.outdata_aclr_a("NONE"),
@@ -49,6 +49,6 @@
 		.read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
 		.read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
-		.widthad_a(12),
-		.widthad_b(12),
+		.widthad_a(14),
+		.widthad_b(14),
 		.width_a(16),
 		.width_b(16),
@@ -86,8 +86,8 @@
         begin
 			int_wren_reg <= 1'b1;
-			int_addr_reg <= 12'd0;
+			int_addr_reg <= 14'd0;
 			int_data_reg <= 16'd0;
 			int_case_reg <= 4'b0;
-			bus_addr_reg <= 12'd0;
+			bus_addr_reg <= 14'd0;
 			bus_miso_reg <= 16'd0;
 			bus_wren_reg <= 1'b0;
@@ -139,5 +139,5 @@
 			begin
 				// write zeros
-				int_addr_next = int_addr_reg + 12'd1;
+				int_addr_next = int_addr_reg + 14'd1;
 				if (&int_addr_reg)
 				begin
@@ -187,5 +187,5 @@
 			begin
 				int_wren_next = 1'b0;
-				int_addr_next = 12'd0;
+				int_addr_next = 14'd0;
 				int_data_next = 16'd0;
 				int_case_next = 4'd0;