Index: /sandbox/MultiChannelUSB/adc_lvds.v
===================================================================
--- /sandbox/MultiChannelUSB/adc_lvds.v	(revision 147)
+++ /sandbox/MultiChannelUSB/adc_lvds.v	(revision 148)
@@ -18,4 +18,5 @@
 
 	);
+	localparam	width2	=	width + 2;
 		
 	reg							state, int_rdreq, adc_frame_reg;
@@ -24,6 +25,11 @@
 	reg		[size-1:0]			int_data_p, int_data_n;
 
-	reg 	[size*width-1:0]	int_data_reg;
-	wire	[size*width-1:0]	int_data_wire;
+	reg 	[2:0]				int_edge_reg;
+
+	reg 	[size*width-1:0]	int_fifo_reg;
+	wire	[size*width-1:0]	int_fifo_wire;
+
+	reg 	[size*width2-1:0]	int_data_reg;
+	wire	[size*width2-1:0]	int_data_wire;
 
 	wire	[size*width-1:0]	int_q_wire;
@@ -40,5 +46,7 @@
 //			assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]};
 // LSB first
-			assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
+//			assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
+			assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
+			assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
 		end
 	endgenerate
@@ -56,5 +64,6 @@
 		.underflow_checking("ON"),
 		.use_eab("ON")) fifo_unit (
-		.data(int_data_wire),
+//		.data(int_data_wire),
+		.data(int_fifo_reg),
 		.rdclk(clock),
 		.rdreq((~int_rdempty) & int_rdreq),
@@ -102,5 +111,9 @@
 		int_data_p <= lvds_d;
 		int_data_reg <= int_data_wire;
-
+		int_edge_reg <= {(~int_edge_reg[1]), int_edge_reg[0], lvds_fco};
+		if (int_edge_reg[1] & int_edge_reg[2])
+		begin
+			int_fifo_reg <= int_fifo_wire;
+		end
 	end