Index: /sandbox/MultiChannelUSB/Paella.v
===================================================================
--- /sandbox/MultiChannelUSB/Paella.v	(revision 144)
+++ /sandbox/MultiChannelUSB/Paella.v	(revision 145)
@@ -1,40 +1,29 @@
 module Paella
 	(
-		input	wire			CLK_50MHz,
+		input	wire			CLK_100MHz,
 		output	wire			LED,
-
-		inout	wire	[3:0]	TRG,
-		inout	wire			I2C_SDA,
-		inout	wire			I2C_SCL,
-		inout	wire	[4:0]	CON_A,
-		input	wire	[15:0]	CON_B,
-		input	wire	[12:0]	CON_C,
-		input	wire	[1:0]	CON_BCLK,
-		input	wire	[1:0]	CON_CCLK,
 
 		input	wire			ADC_DCO,
 		input	wire			ADC_FCO,
-		input	wire	[2:0]	ADC_D,
-
-		output	wire			USB_SLRD, 
+		input	wire	[5:0]	ADC_D,
+
+		output	wire	[1:0]	SPI_SEL,
+		output	wire			SPI_SDO,
+		output	wire			SPI_CLK,
+		output	wire			ADC_RST,
+
+		output	wire			USB_SLRD,
 		output	wire			USB_SLWR,
 		input	wire			USB_IFCLK,
 		input	wire			USB_FLAGA, // EMPTY flag for EP6
 		input	wire			USB_FLAGB, // FULL flag for EP8
-		input	wire			USB_FLAGC,
-		inout	wire			USB_PA0,
-		inout	wire			USB_PA1,
 		output	wire			USB_PA2,
-		inout	wire			USB_PA3,
 		output	wire			USB_PA4,
-		output	wire			USB_PA5,
 		output	wire			USB_PA6,
-		inout	wire			USB_PA7,
 		inout	wire	[7:0]	USB_PB,
 
 		output	wire			RAM_CLK,
-		output	wire			RAM_CE1,
 		output	wire			RAM_WE,
-		output	wire	[19:0]	RAM_ADDR,
+		output	wire	[21:0]	RAM_ADDR,
 		inout	wire			RAM_DQAP,
 		inout	wire	[7:0]	RAM_DQA,
@@ -43,5 +32,5 @@
 	);
 
-	localparam	N		=	3;
+	localparam	N		=	12;
 
 	//	Turn output ports off
@@ -52,22 +41,10 @@
 	assign	RAM_ADDR	=	20'h00000;
 */
+	assign	ADC_RST = 1'b0;
+
 	assign	RAM_CLK = sys_clock;
-	assign	RAM_CE1 = 1'b0;
-
-	//	Turn inout ports to tri-state
-	assign	TRG			=	4'bz;
-	assign	CON_A		=	5'bz;
-	assign	USB_PA0		=	1'bz;
-	assign	USB_PA1		=	1'bz;
-	assign	USB_PA3		=	1'bz;
-	assign	USB_PA7		=	1'bz;
-//	assign	RAM_DQAP	=	1'bz;
-//	assign	RAM_DQA		=	8'bz;
-//	assign	RAM_DQBP	=	1'bz;
-//	assign	RAM_DQB		=	8'bz;
 
 	assign	USB_PA2		=	~usb_rden;
-	assign	USB_PA4		=	usb_addr[0];
-	assign	USB_PA5		=	usb_addr[1];
+	assign	USB_PA4		=	usb_addr;
 	assign	USB_PA6		=	~usb_pktend;
 
@@ -76,5 +53,5 @@
 	wire			usb_tx_full, usb_rx_empty;
 	wire	[7:0]	usb_tx_data, usb_rx_data;
-	wire	[1:0]	usb_addr;
+	wire			usb_addr;
 
 	assign	USB_SLRD = ~usb_rdreq;
@@ -112,13 +89,11 @@
 	wire			coi_flag;
 
-	wire	[7*12-1:0]	int_mux_data [N-1:0];
-
-	wire			ana_dead [N-1:0];
-	wire			ana_good [N-1:0];
-	wire	[11:0]	ana_data [N-1:0];
-	wire	[11:0]	ana_base [N-1:0];
-
-	wire			amp_flag [N-1:0];
-	wire	[11:0]	amp_data [N-1:0];
+	wire	[4*12-1:0]	int_mux_data [N-1:0];
+
+	wire			amp_flag1 [N-1:0];
+	wire	[11:0]	amp_data1 [N-1:0];
+
+	wire			amp_flag2 [N-1:0];
+	wire	[11:0]	amp_data2 [N-1:0];
 
 	wire			cnt_good [N-1:0];
@@ -134,21 +109,19 @@
     wire	[11:0]	del_data;
 
-	wire 	[15:0]	uwt_data1 [N-1:0];
-	wire 	[18:0]	uwt_data2 [N-1:0];
-	wire 	[1:0]	uwt_flag1 [N-1:0];
-	wire 	[1:0]	uwt_flag2 [N-1:0];
-
 	wire	[20:0]	cic_data [N-1:0];
 
 	wire	[11:0]	dec_data [N-1:0];
-	wire	[11:0]	tmp_data;
-
-	wire	[1:0]	ext_flag [N-1:0];
+	wire	[11:0]	clp_data [N-1:0];
+	wire	[11:0]	tmp_data [1:0];
 
 	wire			i2c_reset;
-
+/*
 	sys_pll sys_pll_unit(
-		.inclk0(CLK_50MHz),
-		.c0(sys_clock));
+		.inclk0(CLK_100MHz),
+		.c0(sys_clock),
+		.c1(ADC_DCO),
+		.c2(ADC_FCO));
+
+	wire			ADC_DCO, ADC_FCO;
 
 	test test_unit(
@@ -162,9 +135,26 @@
 		.lvds_dco(ADC_DCO),
 		.lvds_fco(ADC_FCO),
-		.lvds_d(ADC_D),
+		.lvds_d(36'd0),
 		.test(tst_data),
-		.trig({CON_B[9:0], TRG[1:0]}),
+		.trig(12'd0),
 		.adc_frame(sys_frame),
 		.adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
+*/
+	sys_pll sys_pll_unit(
+		.inclk0(CLK_100MHz),
+		.c0(sys_clock));
+
+	adc_lvds #(
+		.size(6),
+		.width(24)) adc_lvds_unit (
+		.clock(sys_clock),
+		.lvds_dco(ADC_DCO),
+		.lvds_fco(ADC_FCO),
+		.lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}),
+		.adc_frame(sys_frame),
+		.adc_data({
+			adc_data[11], adc_data[10], adc_data[9], adc_data[8],
+			adc_data[7], adc_data[6], adc_data[5], adc_data[4],
+			adc_data[3], adc_data[2], adc_data[1], adc_data[0]}));
 
 	wire	[15:0]	cfg_bits [31:0];
@@ -175,15 +165,15 @@
 	wire 			cfg_reset;
 
-	wire 	[11:0]	bus_ssel;
+	wire 	[12:0]	bus_ssel;
 	wire			bus_wren;
 	wire	[31:0]	bus_addr;
 	wire	[15:0]	bus_mosi;
 	wire 	[15:0]	bus_miso [10:0];
-	wire 	[11:0]	bus_busy;
+	wire 	[12:0]	bus_busy;
 
 	wire 	[15:0]	mrg_bus_miso;
 	wire 			mrg_bus_busy;
 
-	wire 	[11*16-1:0]	int_bus_miso;
+	wire 	[12*16-1:0]	int_bus_miso;
 
 	genvar j;
@@ -208,16 +198,9 @@
 
 	generate
-		for (j = 0; j < 3; j = j + 1)
+		for (j = 0; j < 12; j = j + 1)
 		begin : MUX_DATA
 			assign int_mux_data[j] = {
-//				{4'd0, amp_flag[j], 7'd0},
-//				dec_data[j][37:26],
-//				dec_data[j][36:25],
-//				dec_data[j][35:24],
+				clp_data[j][11:0],
 				dec_data[j][11:0],
-				dec_data[j][11:0],
-				amp_data[j][11:0],
-				{ext_flag[j][1], 11'd0},
-				{ext_flag[j][0], 11'd0},
 				cic_data[j][19:8],
 				sys_data[j]};
@@ -228,10 +211,13 @@
 
 	lpm_mux #(
-		.lpm_size(7*3),
+		.lpm_size(4*12),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(12),
-		.lpm_widths(5)) trg_mux_unit (
-		.sel(cfg_bits[4][12:8]),
-		.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+		.lpm_widths(6)) trg_mux_unit (
+		.sel(cfg_bits[4][13:8]),
+		.data({
+			int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
+			int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
+			int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
 		.result(trg_mux_data));
 
@@ -241,10 +227,13 @@
 		
 			lpm_mux #(
-				.lpm_size(7*3),
+				.lpm_size(4*12),
 				.lpm_type("LPM_MUX"),
 				.lpm_width(12),
-				.lpm_widths(5)) osc_mux_unit (
-				.sel(cfg_mux_selector[j*8+4:j*8]),
-				.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+				.lpm_widths(6)) osc_mux_unit (
+				.sel(cfg_mux_selector[j*8+5:j*8]),
+				.data({
+					int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
+					int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
+					int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
 				.result(osc_mux_data[j]));
 		end
@@ -276,59 +265,81 @@
 		.bus_busy(bus_busy[1]));
 
-	new_filter #(.size(3), .width(12)) filter_unit (
+	new_filter #(.size(12), .width(12)) filter_unit (
 		.clock(sys_clock),
 		.frame(sys_frame),
 		.reset(1'b0),
-		.inp_data({sys_data[2], sys_data[1], sys_data[0]}),
-		.out_data({cic_data[2], cic_data[1], cic_data[0]}));
+		.inp_data({
+			sys_data[11], sys_data[10], sys_data[9], sys_data[08],
+			sys_data[7], sys_data[6], sys_data[5], sys_data[4],
+			sys_data[3], sys_data[2], sys_data[1], sys_data[0]}),
+		.out_data({
+			cic_data[11], cic_data[10], cic_data[9], cic_data[8],
+			cic_data[7], cic_data[6], cic_data[5], cic_data[4],
+			cic_data[3], cic_data[2], cic_data[1], cic_data[0]}));
+
+	generate
+		for (j = 0; j < 3; j = j + 1)
+		begin : DECONV_CHAIN
 	
-	deconv #(.size(1), .shift(22), .width(20), .widthr(12)) deconv_unit (
-		.clock(sys_clock),
-		.frame(sys_frame),
-		.reset(1'b0),
-		.del_data({6'd14, 6'd14, 6'd14, 6'd14}),
-		.amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
-		.tau_data({16'd16660, 16'd16660, 16'd16660, 16'd16660}),
-//		.del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}),
-//		.amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}),
-//		.tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}),
-		.inp_data({cic_data[2][19:0], cic_data[1][19:0], cic_data[0][19:0], 20'd0}),
-		.out_data({dec_data[2], dec_data[1], dec_data[0], tmp_data}));
-
-
-	generate
-		for (j = 0; j < 3; j = j + 1)
-		begin : MCA_CHAIN
-
-			assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
-
-			extrema #(.width(12)) extrema_unit (
+			deconv #(.shift(22), .width(20), .widthr(12)) deconv_unit (
 				.clock(sys_clock),
 				.frame(sys_frame),
 				.reset(1'b0),
-				.inp_data(dec_data[j]),
-				.out_flag(ext_flag[j]));
-
-			analyser analyser_unit (
+				.del_data({6'd14, 6'd14, 6'd14, 6'd14}),
+				.amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
+				.tau_data({16'd16320, 16'd16320, 16'd16320, 16'd16320}),
+//				.del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}),
+//				.amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}),
+//				.tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}),
+				.inp_data({
+					cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
+					cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
+				.out_data({
+					dec_data[j*4+3], dec_data[j*4+2],
+					dec_data[j*4+1], dec_data[j*4+0]}));
+		
+		
+			clip #(.shift(22), .width(20), .widthr(12)) clip_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.del_data({6'd14, 6'd14, 6'd14, 6'd14}),
+				.amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
+				.tau_data({16'd17166, 16'd17166, 16'd17166, 16'd17166}),
+				.inp_data({
+					cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
+					cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
+				.out_data({
+					clp_data[j*4+3], clp_data[j*4+2], 
+					clp_data[j*4+1], clp_data[j*4+0]}));
+		end
+	endgenerate
+
+	generate
+		for (j = 0; j < 12; j = j + 1)
+		begin : MCA_CHAIN
+
+			assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+
+			amplitude #(.width(12)) amplitude_unit_1 (
 				.clock(sys_clock),
 				.frame(sys_frame),
 				.reset(cfg_bits[0][2+j]),
-				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
-				.uwt_flag(uwt_flag2[j]),
-				.uwt_data(uwt_data2[j][18:7]),
-				.ana_dead(ana_dead[j]),
-				.ana_good(ana_good[j]),
-				.ana_data(ana_data[j]),
-				.ana_base(ana_base[j]));
-
-			amplitude #(.width(12)) amplitude_unit (
+				.cfg_data({1'b0, 12'd0, 12'd5}),
+//				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
+				.inp_data(dec_data[j]),
+				.out_flag(amp_flag1[j]),
+				.out_data(amp_data1[j]));
+
+			amplitude #(.width(12)) amplitude_unit_2 (
 				.clock(sys_clock),
 				.frame(sys_frame),
 				.reset(cfg_bits[0][2+j]),
-//				.cfg_data(cfg_bits[12][11:0]),
-				.cfg_data(12'd5),
-				.inp_data(dec_data[j]),
-				.out_flag(amp_flag[j]),
-				.out_data(amp_data[j]));
+				.cfg_data({1'b0, 12'd0, 12'd5}),
+//				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
+//				.inp_data(dec_data[j]),
+				.inp_data(clp_data[j]),
+				.out_flag(amp_flag2[j]),
+				.out_data(amp_data2[j]));
 		end
 	endgenerate
@@ -338,6 +349,6 @@
 		.frame(sys_frame),
 		.reset(cfg_bits[0][5]),
-		.hst_good((ana_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
-		.hst_data(ana_data[0]),
+		.hst_good((amp_flag1[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
+		.hst_data(amp_data1[0]),
 /*
 		.hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
@@ -353,6 +364,6 @@
 	counter hst_counter_unit (
 		.clock(sys_clock),
-		.frame((sys_frame) & (~ana_dead[0])),
-//		.frame(sys_frame),
+//		.frame((sys_frame) & (~ana_dead[0])),
+		.frame(sys_frame),
 		.reset(cfg_bits[0][8]),
 		.setup(cfg_bits[13][0]),
@@ -385,4 +396,16 @@
 		.bus_busy(bus_busy[11]));
 
+	spi_fifo spi_unit(
+		.clock(sys_clock),
+		.reset(1'b0),
+		.spi_sel(SPI_SEL),
+		.spi_sdo(SPI_SDO),
+		.spi_clk(SPI_CLK),
+		
+		.bus_ssel(bus_ssel[12]),
+		.bus_wren(bus_wren),
+		.bus_mosi(bus_mosi),
+		.bus_busy(bus_busy[12]));
+
 	generate
 		for (j = 0; j < 11; j = j + 1)
@@ -393,5 +416,5 @@
 
 	lpm_mux #(
-		.lpm_size(11),
+		.lpm_size(12),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(16),
@@ -402,5 +425,5 @@
 
 	lpm_mux #(
-		.lpm_size(12),
+		.lpm_size(13),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(1),
@@ -411,5 +434,5 @@
 
 	lpm_decode #(
-		.lpm_decodes(12),
+		.lpm_decodes(13),
 		.lpm_type("LPM_DECODE"),
 		.lpm_width(4)) lpm_decode_unit (