Changeset 145
- Timestamp:
- May 9, 2011, 5:52:41 PM (13 years ago)
- File:
-
- 1 edited
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sandbox/MultiChannelUSB/Paella.v
r132 r145 1 1 module Paella 2 2 ( 3 input wire CLK_ 50MHz,3 input wire CLK_100MHz, 4 4 output wire LED, 5 6 inout wire [3:0] TRG,7 inout wire I2C_SDA,8 inout wire I2C_SCL,9 inout wire [4:0] CON_A,10 input wire [15:0] CON_B,11 input wire [12:0] CON_C,12 input wire [1:0] CON_BCLK,13 input wire [1:0] CON_CCLK,14 5 15 6 input wire ADC_DCO, 16 7 input wire ADC_FCO, 17 input wire [2:0] ADC_D, 18 19 output wire USB_SLRD, 8 input wire [5:0] ADC_D, 9 10 output wire [1:0] SPI_SEL, 11 output wire SPI_SDO, 12 output wire SPI_CLK, 13 output wire ADC_RST, 14 15 output wire USB_SLRD, 20 16 output wire USB_SLWR, 21 17 input wire USB_IFCLK, 22 18 input wire USB_FLAGA, // EMPTY flag for EP6 23 19 input wire USB_FLAGB, // FULL flag for EP8 24 input wire USB_FLAGC,25 inout wire USB_PA0,26 inout wire USB_PA1,27 20 output wire USB_PA2, 28 inout wire USB_PA3,29 21 output wire USB_PA4, 30 output wire USB_PA5,31 22 output wire USB_PA6, 32 inout wire USB_PA7,33 23 inout wire [7:0] USB_PB, 34 24 35 25 output wire RAM_CLK, 36 output wire RAM_CE1,37 26 output wire RAM_WE, 38 output wire [ 19:0] RAM_ADDR,27 output wire [21:0] RAM_ADDR, 39 28 inout wire RAM_DQAP, 40 29 inout wire [7:0] RAM_DQA, … … 43 32 ); 44 33 45 localparam N = 3;34 localparam N = 12; 46 35 47 36 // Turn output ports off … … 52 41 assign RAM_ADDR = 20'h00000; 53 42 */ 43 assign ADC_RST = 1'b0; 44 54 45 assign RAM_CLK = sys_clock; 55 assign RAM_CE1 = 1'b0;56 57 // Turn inout ports to tri-state58 assign TRG = 4'bz;59 assign CON_A = 5'bz;60 assign USB_PA0 = 1'bz;61 assign USB_PA1 = 1'bz;62 assign USB_PA3 = 1'bz;63 assign USB_PA7 = 1'bz;64 // assign RAM_DQAP = 1'bz;65 // assign RAM_DQA = 8'bz;66 // assign RAM_DQBP = 1'bz;67 // assign RAM_DQB = 8'bz;68 46 69 47 assign USB_PA2 = ~usb_rden; 70 assign USB_PA4 = usb_addr[0]; 71 assign USB_PA5 = usb_addr[1]; 48 assign USB_PA4 = usb_addr; 72 49 assign USB_PA6 = ~usb_pktend; 73 50 … … 76 53 wire usb_tx_full, usb_rx_empty; 77 54 wire [7:0] usb_tx_data, usb_rx_data; 78 wire [1:0]usb_addr;55 wire usb_addr; 79 56 80 57 assign USB_SLRD = ~usb_rdreq; … … 112 89 wire coi_flag; 113 90 114 wire [7*12-1:0] int_mux_data [N-1:0]; 115 116 wire ana_dead [N-1:0]; 117 wire ana_good [N-1:0]; 118 wire [11:0] ana_data [N-1:0]; 119 wire [11:0] ana_base [N-1:0]; 120 121 wire amp_flag [N-1:0]; 122 wire [11:0] amp_data [N-1:0]; 91 wire [4*12-1:0] int_mux_data [N-1:0]; 92 93 wire amp_flag1 [N-1:0]; 94 wire [11:0] amp_data1 [N-1:0]; 95 96 wire amp_flag2 [N-1:0]; 97 wire [11:0] amp_data2 [N-1:0]; 123 98 124 99 wire cnt_good [N-1:0]; … … 134 109 wire [11:0] del_data; 135 110 136 wire [15:0] uwt_data1 [N-1:0];137 wire [18:0] uwt_data2 [N-1:0];138 wire [1:0] uwt_flag1 [N-1:0];139 wire [1:0] uwt_flag2 [N-1:0];140 141 111 wire [20:0] cic_data [N-1:0]; 142 112 143 113 wire [11:0] dec_data [N-1:0]; 144 wire [11:0] tmp_data; 145 146 wire [1:0] ext_flag [N-1:0]; 114 wire [11:0] clp_data [N-1:0]; 115 wire [11:0] tmp_data [1:0]; 147 116 148 117 wire i2c_reset; 149 118 /* 150 119 sys_pll sys_pll_unit( 151 .inclk0(CLK_50MHz), 152 .c0(sys_clock)); 120 .inclk0(CLK_100MHz), 121 .c0(sys_clock), 122 .c1(ADC_DCO), 123 .c2(ADC_FCO)); 124 125 wire ADC_DCO, ADC_FCO; 153 126 154 127 test test_unit( … … 162 135 .lvds_dco(ADC_DCO), 163 136 .lvds_fco(ADC_FCO), 164 .lvds_d( ADC_D),137 .lvds_d(36'd0), 165 138 .test(tst_data), 166 .trig( {CON_B[9:0], TRG[1:0]}),139 .trig(12'd0), 167 140 .adc_frame(sys_frame), 168 141 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]})); 142 */ 143 sys_pll sys_pll_unit( 144 .inclk0(CLK_100MHz), 145 .c0(sys_clock)); 146 147 adc_lvds #( 148 .size(6), 149 .width(24)) adc_lvds_unit ( 150 .clock(sys_clock), 151 .lvds_dco(ADC_DCO), 152 .lvds_fco(ADC_FCO), 153 .lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}), 154 .adc_frame(sys_frame), 155 .adc_data({ 156 adc_data[11], adc_data[10], adc_data[9], adc_data[8], 157 adc_data[7], adc_data[6], adc_data[5], adc_data[4], 158 adc_data[3], adc_data[2], adc_data[1], adc_data[0]})); 169 159 170 160 wire [15:0] cfg_bits [31:0]; … … 175 165 wire cfg_reset; 176 166 177 wire [1 1:0] bus_ssel;167 wire [12:0] bus_ssel; 178 168 wire bus_wren; 179 169 wire [31:0] bus_addr; 180 170 wire [15:0] bus_mosi; 181 171 wire [15:0] bus_miso [10:0]; 182 wire [1 1:0] bus_busy;172 wire [12:0] bus_busy; 183 173 184 174 wire [15:0] mrg_bus_miso; 185 175 wire mrg_bus_busy; 186 176 187 wire [1 1*16-1:0] int_bus_miso;177 wire [12*16-1:0] int_bus_miso; 188 178 189 179 genvar j; … … 208 198 209 199 generate 210 for (j = 0; j < 3; j = j + 1)200 for (j = 0; j < 12; j = j + 1) 211 201 begin : MUX_DATA 212 202 assign int_mux_data[j] = { 213 // {4'd0, amp_flag[j], 7'd0}, 214 // dec_data[j][37:26], 215 // dec_data[j][36:25], 216 // dec_data[j][35:24], 203 clp_data[j][11:0], 217 204 dec_data[j][11:0], 218 dec_data[j][11:0],219 amp_data[j][11:0],220 {ext_flag[j][1], 11'd0},221 {ext_flag[j][0], 11'd0},222 205 cic_data[j][19:8], 223 206 sys_data[j]}; … … 228 211 229 212 lpm_mux #( 230 .lpm_size( 7*3),213 .lpm_size(4*12), 231 214 .lpm_type("LPM_MUX"), 232 215 .lpm_width(12), 233 .lpm_widths(5)) trg_mux_unit ( 234 .sel(cfg_bits[4][12:8]), 235 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 216 .lpm_widths(6)) trg_mux_unit ( 217 .sel(cfg_bits[4][13:8]), 218 .data({ 219 int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8], 220 int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4], 221 int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 236 222 .result(trg_mux_data)); 237 223 … … 241 227 242 228 lpm_mux #( 243 .lpm_size( 7*3),229 .lpm_size(4*12), 244 230 .lpm_type("LPM_MUX"), 245 231 .lpm_width(12), 246 .lpm_widths(5)) osc_mux_unit ( 247 .sel(cfg_mux_selector[j*8+4:j*8]), 248 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 232 .lpm_widths(6)) osc_mux_unit ( 233 .sel(cfg_mux_selector[j*8+5:j*8]), 234 .data({ 235 int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8], 236 int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4], 237 int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 249 238 .result(osc_mux_data[j])); 250 239 end … … 276 265 .bus_busy(bus_busy[1])); 277 266 278 new_filter #(.size( 3), .width(12)) filter_unit (267 new_filter #(.size(12), .width(12)) filter_unit ( 279 268 .clock(sys_clock), 280 269 .frame(sys_frame), 281 270 .reset(1'b0), 282 .inp_data({sys_data[2], sys_data[1], sys_data[0]}), 283 .out_data({cic_data[2], cic_data[1], cic_data[0]})); 271 .inp_data({ 272 sys_data[11], sys_data[10], sys_data[9], sys_data[08], 273 sys_data[7], sys_data[6], sys_data[5], sys_data[4], 274 sys_data[3], sys_data[2], sys_data[1], sys_data[0]}), 275 .out_data({ 276 cic_data[11], cic_data[10], cic_data[9], cic_data[8], 277 cic_data[7], cic_data[6], cic_data[5], cic_data[4], 278 cic_data[3], cic_data[2], cic_data[1], cic_data[0]})); 279 280 generate 281 for (j = 0; j < 3; j = j + 1) 282 begin : DECONV_CHAIN 284 283 285 deconv #(.size(1), .shift(22), .width(20), .widthr(12)) deconv_unit ( 286 .clock(sys_clock), 287 .frame(sys_frame), 288 .reset(1'b0), 289 .del_data({6'd14, 6'd14, 6'd14, 6'd14}), 290 .amp_data({6'd17, 6'd17, 6'd17, 6'd17}), 291 .tau_data({16'd16660, 16'd16660, 16'd16660, 16'd16660}), 292 // .del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}), 293 // .amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}), 294 // .tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}), 295 .inp_data({cic_data[2][19:0], cic_data[1][19:0], cic_data[0][19:0], 20'd0}), 296 .out_data({dec_data[2], dec_data[1], dec_data[0], tmp_data})); 297 298 299 generate 300 for (j = 0; j < 3; j = j + 1) 301 begin : MCA_CHAIN 302 303 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); 304 305 extrema #(.width(12)) extrema_unit ( 284 deconv #(.shift(22), .width(20), .widthr(12)) deconv_unit ( 306 285 .clock(sys_clock), 307 286 .frame(sys_frame), 308 287 .reset(1'b0), 309 .inp_data(dec_data[j]), 310 .out_flag(ext_flag[j])); 311 312 analyser analyser_unit ( 288 .del_data({6'd14, 6'd14, 6'd14, 6'd14}), 289 .amp_data({6'd17, 6'd17, 6'd17, 6'd17}), 290 .tau_data({16'd16320, 16'd16320, 16'd16320, 16'd16320}), 291 // .del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}), 292 // .amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}), 293 // .tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}), 294 .inp_data({ 295 cic_data[j*4+3][19:0], cic_data[j*4+2][19:0], 296 cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}), 297 .out_data({ 298 dec_data[j*4+3], dec_data[j*4+2], 299 dec_data[j*4+1], dec_data[j*4+0]})); 300 301 302 clip #(.shift(22), .width(20), .widthr(12)) clip_unit ( 303 .clock(sys_clock), 304 .frame(sys_frame), 305 .reset(1'b0), 306 .del_data({6'd14, 6'd14, 6'd14, 6'd14}), 307 .amp_data({6'd17, 6'd17, 6'd17, 6'd17}), 308 .tau_data({16'd17166, 16'd17166, 16'd17166, 16'd17166}), 309 .inp_data({ 310 cic_data[j*4+3][19:0], cic_data[j*4+2][19:0], 311 cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}), 312 .out_data({ 313 clp_data[j*4+3], clp_data[j*4+2], 314 clp_data[j*4+1], clp_data[j*4+0]})); 315 end 316 endgenerate 317 318 generate 319 for (j = 0; j < 12; j = j + 1) 320 begin : MCA_CHAIN 321 322 assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); 323 324 amplitude #(.width(12)) amplitude_unit_1 ( 313 325 .clock(sys_clock), 314 326 .frame(sys_frame), 315 327 .reset(cfg_bits[0][2+j]), 316 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), 317 .uwt_flag(uwt_flag2[j]), 318 .uwt_data(uwt_data2[j][18:7]), 319 .ana_dead(ana_dead[j]), 320 .ana_good(ana_good[j]), 321 .ana_data(ana_data[j]), 322 .ana_base(ana_base[j])); 323 324 amplitude #(.width(12)) amplitude_unit ( 328 .cfg_data({1'b0, 12'd0, 12'd5}), 329 // .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), 330 .inp_data(dec_data[j]), 331 .out_flag(amp_flag1[j]), 332 .out_data(amp_data1[j])); 333 334 amplitude #(.width(12)) amplitude_unit_2 ( 325 335 .clock(sys_clock), 326 336 .frame(sys_frame), 327 337 .reset(cfg_bits[0][2+j]), 328 // .cfg_data(cfg_bits[12][11:0]), 329 .cfg_data(12'd5), 330 .inp_data(dec_data[j]), 331 .out_flag(amp_flag[j]), 332 .out_data(amp_data[j])); 338 .cfg_data({1'b0, 12'd0, 12'd5}), 339 // .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), 340 // .inp_data(dec_data[j]), 341 .inp_data(clp_data[j]), 342 .out_flag(amp_flag2[j]), 343 .out_data(amp_data2[j])); 333 344 end 334 345 endgenerate … … 338 349 .frame(sys_frame), 339 350 .reset(cfg_bits[0][5]), 340 .hst_good((a na_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])),341 .hst_data(a na_data[0]),351 .hst_good((amp_flag1[0]) & (cnt_good[0]) & (cfg_bits[13][1])), 352 .hst_data(amp_data1[0]), 342 353 /* 343 354 .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])), … … 353 364 counter hst_counter_unit ( 354 365 .clock(sys_clock), 355 .frame((sys_frame) & (~ana_dead[0])),356 //.frame(sys_frame),366 // .frame((sys_frame) & (~ana_dead[0])), 367 .frame(sys_frame), 357 368 .reset(cfg_bits[0][8]), 358 369 .setup(cfg_bits[13][0]), … … 385 396 .bus_busy(bus_busy[11])); 386 397 398 spi_fifo spi_unit( 399 .clock(sys_clock), 400 .reset(1'b0), 401 .spi_sel(SPI_SEL), 402 .spi_sdo(SPI_SDO), 403 .spi_clk(SPI_CLK), 404 405 .bus_ssel(bus_ssel[12]), 406 .bus_wren(bus_wren), 407 .bus_mosi(bus_mosi), 408 .bus_busy(bus_busy[12])); 409 387 410 generate 388 411 for (j = 0; j < 11; j = j + 1) … … 393 416 394 417 lpm_mux #( 395 .lpm_size(1 1),418 .lpm_size(12), 396 419 .lpm_type("LPM_MUX"), 397 420 .lpm_width(16), … … 402 425 403 426 lpm_mux #( 404 .lpm_size(1 2),427 .lpm_size(13), 405 428 .lpm_type("LPM_MUX"), 406 429 .lpm_width(1), … … 411 434 412 435 lpm_decode #( 413 .lpm_decodes(1 2),436 .lpm_decodes(13), 414 437 .lpm_type("LPM_DECODE"), 415 438 .lpm_width(4)) lpm_decode_unit (
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