Index: sandbox/MultiChannelUSB/clip.v
===================================================================
--- sandbox/MultiChannelUSB/clip.v	(revision 139)
+++ sandbox/MultiChannelUSB/clip.v	(revision 144)
@@ -1,5 +1,4 @@
 module clip
 	#(
-		parameter	size	=	1, // number of channels
 		parameter	shift	=	24, // right shift of the result
 		parameter	width	=	27, // bit width of the input data
@@ -7,10 +6,10 @@
 	)
 	(
-		input	wire						clock, frame, reset,
-		input	wire	[4*size*6-1:0]		del_data,
-		input	wire	[4*size*6-1:0]		amp_data,
-		input	wire	[4*size*16-1:0]		tau_data,
-		input	wire	[4*size*width-1:0]	inp_data,
-		output	wire	[4*size*widthr-1:0]	out_data
+		input	wire					clock, frame, reset,
+		input	wire	[4*6-1:0]		del_data,
+		input	wire	[4*6-1:0]		amp_data,
+		input	wire	[4*16-1:0]		tau_data,
+		input	wire	[4*width-1:0]	inp_data,
+		output	wire	[4*widthr-1:0]	out_data
 	);
 
@@ -19,133 +18,93 @@
 	localparam	width3	=	width1 + 2;
 
-	reg							int_wren_reg, int_wren_next;
-	reg							int_flag_reg, int_flag_next;
-	reg		[1:0]				int_chan_reg, int_chan_next;
-	reg		[2:0]				int_case_reg, int_case_next;
-	reg		[7:0]				int_addr_reg, int_addr_next;
-
-	reg		[5:0]				del_addr_reg, del_addr_next;
-	wire	[5:0]				del_addr_wire;
-	wire	[7:0]				int_addr_wire;
-
-	reg		[size*widthr-1:0]	out_data_reg [4:0], out_data_next [4:0];
-	wire	[size*widthr-1:0]	out_data_wire;
-
-	wire	[size*width3-1:0]	add_data_wire;
-
-	wire	[size*width1-1:0]	mul_data_wire1;
-	wire	[size*width2-1:0]	mul_data_wire2;
-
-	reg		[size*width-1:0]	inp_data_reg [3:0], inp_data_next [3:0];
-	wire	[size*width-1:0]	inp_data_wire [4:0];
-
-	reg		[size*6-1:0]		amp_data_reg, amp_data_next;
-	wire	[size*6-1:0]		amp_data_wire [3:0];
-
-	reg		[size*16-1:0]		tau_data_reg, tau_data_next;
-	wire	[size*16-1:0]		tau_data_wire [3:0];
+	reg						int_wren_reg, int_wren_next;
+	reg						int_flag_reg, int_flag_next;
+	reg		[1:0]			int_chan_reg, int_chan_next;
+	reg		[2:0]			int_case_reg, int_case_next;
+	reg		[7:0]			int_addr_reg, int_addr_next;
+
+	reg		[5:0]			del_addr_reg, del_addr_next;
+	wire	[5:0]			del_addr_wire;
+	wire	[7:0]			int_addr_wire;
+
+	reg		[widthr-1:0]	out_data_reg [4:0], out_data_next [4:0];
+	wire	[widthr-1:0]	out_data_wire;
+
+	wire	[width3-1:0]	add_data_wire;
+
+	wire	[width1-1:0]	mul_data_wire1;
+	wire	[width2-1:0]	mul_data_wire2;
+
+	reg		[width-1:0]		inp_data_reg [3:0], inp_data_next [3:0];
+	wire	[width-1:0]		inp_data_wire [4:0];
+
+	reg		[5:0]			amp_data_reg, amp_data_next;
+	wire	[5:0]			amp_data_wire [3:0];
+
+	reg		[15:0]			tau_data_reg, tau_data_next;
+	wire	[15:0]			tau_data_wire [3:0];
 
 	integer i;
-	genvar j;
+	genvar j; 
 
 	generate
-		for (j = 0; j < size; j = j + 1)
-		begin : INT_DATA
-			assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(4*j+0)*width+width-1:(4*j+0)*width];
-			assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(4*j+1)*width+width-1:(4*j+1)*width];
-			assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(4*j+2)*width+width-1:(4*j+2)*width];
-			assign inp_data_wire[3][j*width+width-1:j*width] = inp_data[(4*j+3)*width+width-1:(4*j+3)*width];
-			assign amp_data_wire[0][j*6+6-1:j*6] = amp_data[(4*j+0)*6+6-1:(4*j+0)*6];
-			assign amp_data_wire[1][j*6+6-1:j*6] = amp_data[(4*j+1)*6+6-1:(4*j+1)*6];
-			assign amp_data_wire[2][j*6+6-1:j*6] = amp_data[(4*j+2)*6+6-1:(4*j+2)*6];
-			assign amp_data_wire[3][j*6+6-1:j*6] = amp_data[(4*j+3)*6+6-1:(4*j+3)*6];
-			assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(4*j+0)*16+16-1:(4*j+0)*16];
-			assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(4*j+1)*16+16-1:(4*j+1)*16];
-			assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(4*j+2)*16+16-1:(4*j+2)*16];
-			assign tau_data_wire[3][j*16+16-1:j*16] = tau_data[(4*j+3)*16+16-1:(4*j+3)*16];
-                                                                                         
-			lpm_mux #(
-				.lpm_size(4),
-				.lpm_type("LPM_MUX"),
-				.lpm_width(8),
-				.lpm_widths(2)) mux_unit_1 (
-				.sel(int_chan_next),
-				.data({
-					2'd3, del_data[(4*j+3)*6+6-1:(4*j+3)*6],
-					2'd2, del_data[(4*j+2)*6+6-1:(4*j+2)*6],
-					2'd1, del_data[(4*j+1)*6+6-1:(4*j+1)*6],
-					2'd0, del_data[(4*j+0)*6+6-1:(4*j+0)*6]}),
-				.result(int_addr_wire));
-/*
-			lpm_add_sub	#(
-				.lpm_direction("SUB"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("UNSIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(6)) add_unit_1 (
-				.dataa(del_addr_reg),
-				.datab(int_addr_wire[5:0]),
-				.result(del_addr_wire));
-*/
-			assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
-
-			lpm_mult #(
-				.lpm_hint("MAXIMIZE_SPEED=9"),
-				.lpm_representation("UNSIGNED"),
-				.lpm_type("LPM_MULT"),
-				.lpm_pipeline(3),
-				.lpm_widtha(width),
-				.lpm_widthb(16),
-				.lpm_widthp(width1)) mult_unit_1 (
-				.clock(clock),
-				.clken(int_wren_reg),
-				.dataa(inp_data_wire[4][j*width+width-1:j*width]),
-				.datab(tau_data_reg[j*16+16-1:j*16]),
-				.result(mul_data_wire1[j*width1+width1-1:j*width1]));
-
-			lpm_mult #(
-				.lpm_hint("MAXIMIZE_SPEED=9"),
-				.lpm_representation("UNSIGNED"),
-				.lpm_type("LPM_MULT"),
-				.lpm_pipeline(3),
-				.lpm_widtha(width),
-				.lpm_widthb(6),
-				.lpm_widthp(width2)) mult_unit_2 (
-				.clock(clock),
-				.clken(int_wren_reg),
-				.dataa(inp_data_reg[0][j*width+width-1:j*width]),
-				.datab(amp_data_reg[j*6+6-1:j*6]),
-				.result(mul_data_wire2[j*width2+width2-1:j*width2]));
-/*
-			lpm_add_sub	#(
-				.lpm_direction("SUB"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("UNSIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(width3)) add_unit_2 (
-				.dataa({2'b0, mul_data_wire2[j*width2+width2-1:j*width2], {(width1-width2){1'b0}}}),
-				.datab({2'b0, mul_data_wire1[j*width1+width1-1:j*width1]}),
-				.result(add_data_wire[j*width3+width3-1:j*width3]));
-*/
-			assign add_data_wire[j*width3+width3-1:j*width3] = 
-				  {2'b0, mul_data_wire2[j*width2+width2-1:j*width2], {(width1-width2){1'b0}}}
-				- {2'b0, mul_data_wire1[j*width1+width1-1:j*width1]};
-/*
-			lpm_add_sub	#(
-				.lpm_direction("ADD"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("UNSIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) add_unit_3 (
-				.dataa(add_data_wire[j*width3+shift+widthr-1:j*width3+shift]),
-				.datab({{(widthr-1){add_data_wire[j*width3+width3-1]}}, add_data_wire[j*width3+shift-1]}),
-				.result(out_data_wire[j*widthr+widthr-1:j*widthr]));
-*/
-			assign out_data_wire[j*widthr+widthr-1:j*widthr] = 
-				  add_data_wire[j*width3+shift+widthr-1:j*width3+shift]
-				+ {{(widthr-1){add_data_wire[j*width3+width3-1]}}, add_data_wire[j*width3+shift-1]};
-
+		for (j = 0; j < 4; j = j + 1)
+		begin : INT_DATA 
+			assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
+			assign amp_data_wire[j] = amp_data[j*6+6-1:j*6];
+			assign tau_data_wire[j] = tau_data[j*16+16-1:j*16];
 		end
 	endgenerate
+																				 
+	lpm_mux #(
+		.lpm_size(4),
+		.lpm_type("LPM_MUX"),
+		.lpm_width(8),
+		.lpm_widths(2)) mux_unit_1 (
+		.sel(int_chan_next),
+		.data({
+			2'd3, del_data[3*6+6-1:3*6],
+			2'd2, del_data[2*6+6-1:2*6],
+			2'd1, del_data[1*6+6-1:1*6],
+			2'd0, del_data[0*6+6-1:0*6]}),
+		.result(int_addr_wire));
+
+	assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
+
+	lpm_mult #(
+		.lpm_hint("MAXIMIZE_SPEED=9"),
+		.lpm_representation("UNSIGNED"),
+		.lpm_type("LPM_MULT"),
+		.lpm_pipeline(3),
+		.lpm_widtha(width),
+		.lpm_widthb(16),
+		.lpm_widthp(width1)) mult_unit_1 (
+		.clock(clock),
+		.clken(int_wren_reg),
+		.dataa(inp_data_wire[4]),
+		.datab(tau_data_reg),
+		.result(mul_data_wire1));
+
+	lpm_mult #(
+		.lpm_hint("MAXIMIZE_SPEED=9"),
+		.lpm_representation("UNSIGNED"),
+		.lpm_type("LPM_MULT"),
+		.lpm_pipeline(3),
+		.lpm_widtha(width),
+		.lpm_widthb(6),
+		.lpm_widthp(width2)) mult_unit_2 (
+		.clock(clock),
+		.clken(int_wren_reg),
+		.dataa(inp_data_reg[0]),
+		.datab(amp_data_reg),
+		.result(mul_data_wire2));
+
+	assign add_data_wire = 
+		  {2'b0, mul_data_wire2, {(width1-width2){1'b0}}}
+		- {2'b0, mul_data_wire1};
+
+	assign out_data_wire = 
+		  add_data_wire[shift+widthr-1:shift]
+		+ {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]};
 
 
@@ -167,6 +126,6 @@
 		.widthad_a(8),
 		.widthad_b(8),
-		.width_a(size*width),
-		.width_b(size*width),
+		.width_a(width),
+		.width_b(width),
 		.width_byteena_a(1)) ram_unit_1 (
 		.wren_a(int_wren_reg),
@@ -187,5 +146,5 @@
 		.clocken2(1'b1),
 		.clocken3(1'b1),
-		.data_b({(size*width){1'b1}}),
+		.data_b({(width){1'b1}}),
 		.eccstatus(),
 		.q_a(),
@@ -208,9 +167,9 @@
 			for(i = 0; i <= 3; i = i + 1)
 			begin
-				inp_data_reg[i] <= {(size*width){1'b0}};
+				inp_data_reg[i] <= {(width){1'b0}};
 			end
 			for(i = 0; i <= 4; i = i + 1)
 			begin
-				out_data_reg[i] <= {(size*widthr){1'b0}};
+				out_data_reg[i] <= {(widthr){1'b0}};
 			end
 		end
@@ -266,9 +225,9 @@
 				for(i = 0; i <= 3; i = i + 1)
 				begin
-					inp_data_next[i] = {(size*width){1'b0}};
+					inp_data_next[i] = {(width){1'b0}};
 				end                  
 				for(i = 0; i <= 4; i = i + 1)
 				begin
-					out_data_next[i] = {(size*widthr){1'b0}};
+					out_data_next[i] = {(widthr){1'b0}};
 				end                  
 
