Index: /sandbox/MultiChannelUSB/spi_fifo.v
===================================================================
--- /sandbox/MultiChannelUSB/spi_fifo.v	(revision 140)
+++ /sandbox/MultiChannelUSB/spi_fifo.v	(revision 141)
@@ -1,51 +1,51 @@
 module spi_fifo
 	(		
-		input		wire				clock, reset,
+		input	wire			clock, reset,
 
-		input		wire				bus_ssel, bus_wren,
-		input		wire	[15:0]	bus_mosi,
+		input	wire			bus_ssel, bus_wren,
+		input	wire	[15:0]	bus_mosi,
 
-		output	wire				bus_busy,
+		output	wire			bus_busy,
 
-		output	wire				spi_sel,
-		output	wire				spi_sdo,
-		output	wire				spi_clk
+		output	wire	[1:0]	spi_sel,
+		output	wire			spi_sdo,
+		output	wire			spi_clk
 	);
 
-	wire				int_rdempty, int_wrfull;
-	wire	[15:0]	int_q;
+	wire			int_rdempty, int_wrfull;
+	wire	[31:0]	int_q;
 
 	reg				int_bus_busy;
 	reg				int_rdreq, int_wrreq;
-	reg				int_clken, int_sdo, int_sel;
-	reg	[15:0]	int_bus_mosi;
-	reg	[15:0]	int_data;
-	reg	[2:0]		clk_cntr;
-	reg	[3:0]		bit_cntr;
-	reg	[1:0]		state;
+	reg				int_clken, int_sdo;
+	reg		[1:0]	int_sel;
+	reg		[15:0]	int_bus_mosi;
+	reg		[31:0]	int_data;
+	reg		[2:0]	clk_cntr;
+	reg		[4:0]	bit_cntr;
+	reg		[1:0]	state;
 
-	scfifo #(
-		.add_ram_output_register("OFF"),
+	dcfifo_mixed_widths #(
 		.intended_device_family("Cyclone III"),
 		.lpm_numwords(16),
 		.lpm_showahead("ON"),
-		.lpm_type("scfifo"),
+		.lpm_type("dcfifo"),
 		.lpm_width(16),
 		.lpm_widthu(4),
+		.lpm_width_r(32),
+		.lpm_widthu_r(3),
+		.rdsync_delaypipe(4),
+		.wrsync_delaypipe(4),
 		.overflow_checking("ON"),
 		.underflow_checking("ON"),
-		.use_eab("OFF")) fifo_tx (
+		.use_eab("ON")) fifo_tx (
+		.data(int_bus_mosi),
+		.rdclk(clock),
 		.rdreq((~int_rdempty) & (int_rdreq) & (&clk_cntr)),
-		.aclr(1'b0),
-		.clock(clock),
+		.wrclk(clock),
 		.wrreq(int_wrreq),
-		.data(int_bus_mosi),
-		.empty(int_rdempty),
 		.q(int_q),
-		.full(int_wrfull),
-		.almost_empty(),
-		.almost_full(),
-		.sclr(),
-		.usedw());
+		.rdempty(int_rdempty),
+		.wrfull(int_wrfull));
 	
 	always @ (posedge clock)
@@ -78,5 +78,5 @@
 				begin
 					int_sdo <= 1'b0;
-					int_sel <= 1'b1;
+					int_sel <= 2'b11;
 					int_clken <= 1'b0;
 					int_rdreq <= 1'b1;
@@ -89,6 +89,6 @@
 					begin
 						int_rdreq <= 1'b0;
-						int_data <= int_q;
-						bit_cntr <= 4'd0;
+						int_data <= {int_q[15:0], int_q[31:16]};
+						bit_cntr <= 5'd0;
 						state <= 2'd2;
 					end
@@ -99,9 +99,9 @@
 				begin // data
 					int_clken <= 1'b1;
-					int_sel <= 1'b0;
-					int_sdo <= int_data[11];
-					int_data <= {int_data[10:0], 1'b0};
-					bit_cntr <= bit_cntr + 4'd1;
-					if (bit_cntr == 4'd11)
+					int_sel <= int_data[25:24];
+					int_sdo <= int_data[23];
+					int_data[23:0] <= {int_data[22:0], 1'b0};
+					bit_cntr <= bit_cntr + 5'd1;
+					if (bit_cntr == 5'd23)
 					begin
 						state <= 2'd3;