Index: /sandbox/MultiChannelUSB/adc_lvds.v
===================================================================
--- /sandbox/MultiChannelUSB/adc_lvds.v	(revision 139)
+++ /sandbox/MultiChannelUSB/adc_lvds.v	(revision 140)
@@ -1,6 +1,6 @@
 module adc_lvds
 	#(
-		parameter	size	=	3, // number of channels
-		parameter	width	=	12 // channel resolution
+		parameter	size	=	8, // number of channels
+		parameter	width	=	24 // channel resolution
 	)
 	(
@@ -11,34 +11,41 @@
  		input	wire	[size-1:0]			lvds_d,
 
- 		input	wire	[11:0]				test,
- 		input	wire	[11:0]				trig,
-
 		output	wire						adc_frame,
-		output	wire	[size*width-1+12:0]	adc_data
+		output	wire	[size*width-1:0]	adc_data
 
 	);
-
+	localparam	width2	=	width + 1;
+		
 	reg							state, int_rdreq, adc_frame_reg;
 	wire						int_wrfull, int_rdempty;
 
-	reg		[size-1:0]			int_data_h, int_data_l;
+	reg		[size-1:0]			int_data_p, int_data_n;
 
-	reg 	[size*width-1:0]	int_data_reg;
-	wire	[size*width-1:0]	int_data_wire;
+	reg 	[2:0]				int_edge_reg;
 
-	wire	[size*width-1+12:0]	int_q_wire;
-	reg		[size*width-1+12:0]	adc_data_reg;
+	reg 	[size*width-1:0]	int_fifo_reg;
+	wire	[size*width-1:0]	int_fifo_wire;
+
+	reg 	[size*width2-1:0]	int_data_reg;
+	wire	[size*width2-1:0]	int_data_wire;
+
+	wire	[size*width-1:0]	int_q_wire;
+	reg		[size*width-1:0]	adc_data_reg;
 	
+
 
 	genvar j;
 
 	generate
-		for (j = 0; j < size-1; j = j + 1)
+		for (j = 0; j < size; j = j + 1)
 		begin : INT_DATA
-			assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_h[j], int_data_l[j]};
-//			assign int_data_wire[j*width+width-1:j*width] = test;
+// MSB first
+//			assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_p[j], int_data_n[j]};
+// LSB first
+//			assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
+			assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
+			assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-2:j*width2];
 		end
 	endgenerate
-	assign int_data_wire[(size-1)*width+width-1:(size-1)*width] = test;
 
 	dcfifo #(
@@ -47,5 +54,5 @@
 		.lpm_showahead("ON"),
 		.lpm_type("dcfifo"),
-		.lpm_width(size*width+12),
+		.lpm_width(size*width),
 		.lpm_widthu(4),
 		.rdsync_delaypipe(4),
@@ -54,5 +61,6 @@
 		.underflow_checking("ON"),
 		.use_eab("ON")) fifo_unit (
-		.data({trig, int_data_wire}),
+//		.data(int_data_wire),
+		.data(int_fifo_reg),
 		.rdclk(clock),
 		.rdreq((~int_rdempty) & int_rdreq),
@@ -93,11 +101,16 @@
 	always @ (negedge lvds_dco)
 	begin
-		int_data_l <= lvds_d;
+		int_data_n <= lvds_d;
 	end
 
 	always @ (posedge lvds_dco)
 	begin
-		int_data_h <= lvds_d;
+		int_data_p <= lvds_d;
 		int_data_reg <= int_data_wire;
+		int_edge_reg <= {int_edge_reg[1:0], lvds_fco};
+		if (int_edge_reg[1] & (~int_edge_reg[2]))
+		begin
+			int_fifo_reg <= int_fifo_wire;
+		end
 	end