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Changeset 136

Timestamp:

Mar 15, 2011, 12:16:01 PM (14 years ago)

Author:

demin

Message:

swap ep6/ep8 and reorganize usb_jtag_init

Location:

trunk/FirmwareFX2

Files:

: 3 edited

dscr.a51 (modified) (4 diffs)
usbjtag.c (modified) (1 diff)
usbjtag.hex (modified) (3 diffs)

Legend:

: Unmodified
: Added
: Removed

trunk/FirmwareFX2/dscr.a51

-              r24
+              r136
         .db        DSCR_ENDPNT_LEN
         .db        DSCR_ENDPNT
         .db        0x06                  ; bEndpointAddress (ep 6 OUT)
+        .db        0x86                  ; bEndpointAddress (ep 6 IN)
         .db        ET_BULK               ; bmAttributes
         .db        0x00                  ; wMaxPacketSize (LSB)
 …
         .db        DSCR_ENDPNT_LEN
         .db        DSCR_ENDPNT
         .db        0x88                  ; bEndpointAddress (ep 8 IN)
+        .db        0x08                  ; bEndpointAddress (ep 8 OUT)
         .db        ET_BULK               ; bmAttributes
         .db        0x00                  ; wMaxPacketSize (LSB)
 …
         .db        DSCR_ENDPNT_LEN
         .db        DSCR_ENDPNT
         .db        0x06             ; bEndpointAddress (ep 6 OUT)
+        .db        0x86             ; bEndpointAddress (ep 6 IN)
         .db        ET_BULK          ; bmAttributes
         .db        0x40             ; wMaxPacketSize (LSB)
 …
         .db        DSCR_ENDPNT_LEN
         .db        DSCR_ENDPNT
         .db        0x88             ; bEndpointAddress (ep 8 IN)
+        .db        0x08             ; bEndpointAddress (ep 8 OUT)
         .db        ET_BULK          ; bmAttributes
         .db        0x40             ; wMaxPacketSize (LSB)

trunk/FirmwareFX2/usbjtag.c

-              r135
+              r136
    // define endpoint configuration
+   REVCTL = 3; SYNCDELAY;                               // Allow FW access to FIFO buffer
+   FIFORESET = 0x80; SYNCDELAY;                         // From now on, NAK all, reset all FIFOS
+   FIFORESET  = 0x02; SYNCDELAY;                        // Reset FIFO 2
+   FIFORESET  = 0x04; SYNCDELAY;                        // Reset FIFO 4
+   FIFORESET  = 0x06; SYNCDELAY;                        // Reset FIFO 6
+   FIFORESET  = 0x08; SYNCDELAY;                        // Reset FIFO 8
+   FIFORESET  = 0x00; SYNCDELAY;                        // Restore normal behaviour
+   EP1OUTCFG  = 0xA0; SYNCDELAY;                        // Endpoint 1 Type Bulk
+   EP1INCFG   = 0xA0; SYNCDELAY;                        // Endpoint 1 Type Bulk
+   EP2FIFOCFG = 0x00; SYNCDELAY;                        // Endpoint 2
+   EP2CFG     = 0xA2; SYNCDELAY;                        // Endpoint 2 Valid, Out, Type Bulk, Double buffered
+   EP4FIFOCFG = 0x00; SYNCDELAY;                        // Endpoint 4 not used
+   EP4CFG     = 0xA0; SYNCDELAY;                        // Endpoint 4 not used
+   REVCTL = 0; SYNCDELAY;                               // Reset FW access to FIFO buffer, enable auto-arming when AUTOOUT is switched to 1
+   EP6CFG     = 0xA2; SYNCDELAY;                        // Out endpoint, Bulk, Double buffering
+   EP6FIFOCFG = 0x00; SYNCDELAY;                        // Firmware has to see a rising edge on auto bit to enable auto arming
+   EP6FIFOCFG = bmAUTOOUT; SYNCDELAY;                   // Endpoint 6 used for user communicationn, auto commitment, 8 bits data bus
+   EP8CFG     = 0xE0; SYNCDELAY;                        // In endpoint, Bulk
+   EP8FIFOCFG = 0x00; SYNCDELAY;                        // Firmware has to see a rising edge on auto bit to enable auto arming
+   EP8FIFOCFG = bmAUTOIN; SYNCDELAY;                    // Endpoint 8 used for user communication, auto commitment, 8 bits data bus
+   EP8AUTOINLENH = 0x02; SYNCDELAY;                     // Size in bytes of the IN data automatically commited (512 bytes here, but changed dynamically depending on the connection)
+   EP8AUTOINLENL = 0x00; SYNCDELAY;                     // Can use signal PKTEND if you want to commit a shorter packet
+   // Out endpoints do not come up armed
+   // Since the defaults are double buffered we must write dummy byte counts twice
+   EP2BCL = 0x80; SYNCDELAY;                            // Arm EP2OUT by writing byte count w/skip.
+   EP4BCL = 0x80; SYNCDELAY;
+   EP2BCL = 0x80; SYNCDELAY;                            // Arm EP4OUT by writing byte count w/skip.
+   EP4BCL = 0x80; SYNCDELAY;
+   PINFLAGSAB = 0xFA; SYNCDELAY;                        // 1111_1010 => FLAGA = EMPTY flag for EP6; FLAGB = FULL flag for EP8
+   // LED turned off by default
+   IOD |= (1 << 4); SYNCDELAY;
+   // Put the system in high speed by default (REM: USB-Blaster is in full speed)
+   // This can be changed by vendor commands
+   CT1 &= ~0x02;
+   REVCTL     = 0x03; SYNCDELAY;                                        // Allow FW access to FIFO buffer
+   EP1OUTCFG  = 0xA0; SYNCDELAY;                                        // Endpoint 1 Type Bulk
+   EP1INCFG   = 0xA0; SYNCDELAY;                                        // Endpoint 1 Type Bulk
+   EP2CFG     = 0xA2; SYNCDELAY;                                        // Endpoint 2 ON,  OUT, BULK, 512, Buffer 2x
+   EP6CFG     = 0xE3; SYNCDELAY;                                        // Endpoint 6 ON,  IN,  BULK, 512, Buffer 3x
+   EP8CFG     = 0xA0; SYNCDELAY;                                        // Endpoint 8 ON,  OUT, BULK, 512, Buffer 2x
+   EP4CFG     = 0x20; SYNCDELAY;                                        // Endpoint 4 OFF, OUT, BULK, 512, Buffer 2x
+   FIFORESET  = 0x80; SYNCDELAY;                                    // From now on, NAK all
+   FIFORESET  = 0x82; SYNCDELAY;                                        // Reset Endpoint 2 FIFO
+   FIFORESET  = 0x84; SYNCDELAY;                                        // Reset Endpoint 4 FIFO
+   FIFORESET  = 0x86; SYNCDELAY;                                        // Reset Endpoint 6 FIFO
+   FIFORESET  = 0x88; SYNCDELAY;                                        // Reset Endpoint 8 FIFO
+   FIFORESET  = 0x00; SYNCDELAY;                                        // Restore normal behaviour
+   OUTPKTEND  = 0x82; SYNCDELAY;                     // Arm Endpoint 2 buffers to "prime the pump"
+   OUTPKTEND  = 0x82; SYNCDELAY;
+   OUTPKTEND  = 0x88; SYNCDELAY;                     // Arm Endpoint 8 buffers to "prime the pump"
+   OUTPKTEND  = 0x88; SYNCDELAY;
+   REVCTL     = 0x00; SYNCDELAY;                                        // Reset FW access to FIFO buffer, enable auto-arming when AUTOOUT is switched to 1
+   EP2FIFOCFG = 0x00; SYNCDELAY;
+   EP4FIFOCFG = 0x00; SYNCDELAY;
+   EP6FIFOCFG = bmAUTOIN; SYNCDELAY;
+   EP8FIFOCFG = bmAUTOOUT; SYNCDELAY;
+   EP8AUTOINLENH = 0x02; SYNCDELAY;                                     // Auto-commit 512-byte packets
+   EP8AUTOINLENL = 0x00; SYNCDELAY;
+   PINFLAGSAB = 0xEB; SYNCDELAY;                   // 1111_1010 => FLAGA = EMPTY flag for EP6; FLAGB = FULL flag for EP8
+   IOD |= (1 << 4); SYNCDELAY;                     // LED turned off by default
+}

trunk/FirmwareFX2/usbjtag.hex

-              r28
+              r136
 :0600000002117702006B03
+:06000000020FD602006BA6
 :03000B0002006B85
 :0300130002006B7D
 …
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