Index: sandbox/MultiChannelUSB/Paella.v
===================================================================
--- sandbox/MultiChannelUSB/Paella.v	(revision 122)
+++ sandbox/MultiChannelUSB/Paella.v	(revision 123)
@@ -119,5 +119,5 @@
 	wire	[11:0]	ana_base [N-1:0];
 
-	wire			amp_good [N-1:0];
+	wire			amp_flag [N-1:0];
 	wire	[11:0]	amp_data [N-1:0];
 
@@ -134,20 +134,16 @@
     wire	[11:0]	del_data;
 
-	wire 	[31:0]	uwt_d1 [N-1:0];
-	wire 	[31:0]	uwt_a1 [N-1:0];
-	wire 	[31:0]	uwt_d2 [N-1:0];
-	wire 	[31:0]	uwt_a2 [N-1:0];
-	wire 	[31:0]	uwt_d3 [N-1:0];
-	wire 	[31:0]	uwt_a3 [N-1:0];
-
+	wire 	[15:0]	uwt_data1 [N-1:0];
+	wire 	[18:0]	uwt_data2 [N-1:0];
 	wire 	[1:0]	uwt_flag1 [N-1:0];
 	wire 	[1:0]	uwt_flag2 [N-1:0];
-	wire 	[1:0]	uwt_flag3 [N-1:0];
-	
-	wire	[11:0]	cic_mux_data;
-	wire	[13:0]	cic_lfsr;
-	wire	[24:0]	cic_data1 [N-1:0];
-	wire	[24:0]	cic_data2 [N-1:0];
-	wire	[24:0]	cic_data3 [N-1:0];
+
+	wire	[27:0]	cic_data1 [N-1:0];
+	wire	[27:0]	cic_data2 [N-1:0];
+	wire	[27:0]	cic_data3 [N-1:0];
+
+	wire	[11:0]	dec_data [N-1:0];
+
+	wire	[1:0]	ext_flag [N-1:0];
 
 	wire			i2c_reset;
@@ -216,14 +212,14 @@
 		begin : MUX_DATA
 			assign int_mux_data[j] = {
-				{4'd0, uwt_flag3[j][1], 7'd0},
-				{4'd0, uwt_flag3[j][0], 7'd0},
-				{12'd0},
-//				{4'd0, amp_good[j], 7'd0},
-				cic_data1[j][14:3],
-				cic_data2[j][18:7],
-				cic_data3[j][22:11],
-//				{8'd0, cic_lfsr[3:0]},
-//				{8'd0, cic_lfsr[5:2]},
-//				uwt_a3[j][20:9],
+//				{4'd0, amp_flag[j], 7'd0},
+//				dec_data[j][37:26],
+//				dec_data[j][36:25],
+//				dec_data[j][35:24],
+				dec_data[j][11:0],
+				dec_data[j][11:0],
+				amp_data[j][11:0],
+				{ext_flag[j][1], 11'd0},
+				{ext_flag[j][0], 11'd0},
+				cic_data3[j][26:15],
 				sys_data[j]};
 		end
@@ -253,5 +249,4 @@
 				.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
 				.result(osc_mux_data[j]));
-		
 		end
 	endgenerate
@@ -291,4 +286,18 @@
 		.out_data({cic_data1[2], cic_data1[1], cic_data1[0]}));
 	
+	deconv #(.size(1), .shift(25), .width(27), .widthr(12)) deconv_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(1'b0),
+		.del_data({6'd20, 6'd20, 6'd20}),
+		.amp_data({8'd1, 8'd1, 8'd1}),
+		.tau_data({16'd980, 16'd980, 16'd980}),
+//		.del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}),
+//		.amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}),
+//		.tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}),
+		.inp_data({cic_data3[2][26:0], cic_data3[1][26:0], cic_data3[0][26:0]}),
+		.out_data({dec_data[2], dec_data[1], dec_data[0]}));
+
+
 	generate
 		for (j = 0; j < 3; j = j + 1)
@@ -296,6 +305,29 @@
 
 			assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
-
-	
+/*
+			uwt_bior31 #(.level(1), .width(13)) uwt_1_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.inp_data(dec_data[j][12:0]),
+				.out_data(uwt_data1[j]),
+				.out_flag(uwt_flag1[j]));
+		
+			uwt_bior31 #(.level(1), .width(16)) uwt_2_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+				.inp_data(uwt_data1[j]),
+				.out_data(uwt_data2[j]),
+				.out_flag(uwt_flag2[j]));
+*/		
+			extrema #(.width(12)) extrema_unit (
+				.clock(sys_clock),
+				.frame(sys_frame),
+				.reset(1'b0),
+//				.inp_data(cic_data3[j][26:15]),
+				.inp_data(dec_data[j]),
+				.out_flag(ext_flag[j]));
+
 			analyser analyser_unit (
 				.clock(sys_clock),
@@ -304,5 +336,5 @@
 				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
 				.uwt_flag(uwt_flag2[j]),
-				.uwt_data(uwt_a2[j][17:6]),
+				.uwt_data(uwt_data2[j][18:7]),
 				.ana_dead(ana_dead[j]),
 				.ana_good(ana_good[j]),
@@ -310,14 +342,14 @@
 				.ana_base(ana_base[j]));
 
-			amplitude amplitude_unit (
+			amplitude #(.width(12)) amplitude_unit (
 				.clock(sys_clock),
 				.frame(sys_frame),
 				.reset(cfg_bits[0][2+j]),
-				.cfg_data(cfg_bits[12][11:0]),
-//				.cfg_data(10'd5),
-				.uwt_flag(uwt_flag3[j]),
-				.uwt_data(uwt_a3[j][20:9]),
-				.amp_good(amp_good[j]),
-				.amp_data(amp_data[j]));
+//				.cfg_data(cfg_bits[12][11:0]),
+				.cfg_data(12'd5),
+//				.inp_data(cic_data3[j][22:11]),
+				.inp_data(dec_data[j]),
+				.out_flag(amp_flag[j]),
+				.out_data(amp_data[j]));
 		end
 	endgenerate
@@ -330,5 +362,5 @@
 		.hst_data(ana_data[0]),
 /*
-		.hst_good((amp_good[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
+		.hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
 		.hst_data(amp_data[j]),
 */
Index: sandbox/MultiChannelUSB/amplitude.v
===================================================================
--- sandbox/MultiChannelUSB/amplitude.v	(revision 122)
+++ sandbox/MultiChannelUSB/amplitude.v	(revision 123)
@@ -1,17 +1,25 @@
 module amplitude
+	#(
+		parameter	width	=	12 // bit width of the input data
+	)
 	(
-		input	wire			clock, frame, reset,
-		input	wire	[11:0]	cfg_data,
-		input	wire	[1:0]	uwt_flag,
-		input	wire	[11:0]	uwt_data,
-		output	wire			amp_good,
-		output	wire	[11:0]	amp_data
+		input	wire				clock, frame, reset,
+		input	wire	[width-1:0]	cfg_data,
+		input	wire	[width-1:0]	inp_data,
+		output	wire	[width-1:0]	out_data,
+		output	wire				out_flag
 	);
 
-	reg				state_reg, state_next;
-	reg		[11:0]	minimum_reg, minimum_next;
-	reg				amp_good_reg, amp_good_next;
-	reg		[11:0]	amp_data_reg, amp_data_next;
-	reg		[11:0]	uwt_data_reg, uwt_data_next;
+	reg					int_case_reg, int_case_next;
+	reg					out_flag_reg, out_flag_next;
+	reg					int_flag_reg, int_flag_next;
+	reg		[width-1:0]	int_mini_reg, int_mini_next;
+	reg		[width-1:0]	out_data_reg, out_data_next;
+	reg		[width-1:0]	inp_data_reg, inp_data_next;
+
+	wire				int_comp_wire;
+	reg					int_comp_reg, int_comp_next;
+
+	assign int_comp_wire = (inp_data_reg < inp_data);
 
 	always @(posedge clock)
@@ -19,17 +27,21 @@
 		if (reset)
 		begin
-			state_reg <= 1'b0;
-			minimum_reg <= 12'd0;
-			amp_good_reg <= 1'b0;
-			amp_data_reg <= 12'd0;
-			uwt_data_reg <= 12'd0;
+			int_case_reg <= 1'b0;
+			int_mini_reg <= {(width){1'b0}};
+			inp_data_reg <= {(width){1'b0}};
+			out_data_reg <= {(width){1'b0}};
+			out_flag_reg <= 1'b0;
+			int_flag_reg <= 1'b0;
+			int_comp_reg <= 1'b0;
 		end
 		else
 		begin
-			state_reg <= state_next;
-			minimum_reg <= minimum_next;
-			amp_good_reg <= amp_good_next;
-			amp_data_reg <= amp_data_next;
-			uwt_data_reg <= uwt_data_next;
+			int_case_reg <= int_case_next;
+			int_mini_reg <= int_mini_next;
+			inp_data_reg <= inp_data_next;
+			out_data_reg <= out_data_next;
+			out_flag_reg <= out_flag_next;
+			int_flag_reg <= int_flag_next;
+			int_comp_reg <= int_comp_next;
 		end
 	end
@@ -37,26 +49,33 @@
 	always @*
 	begin
-		state_next = state_reg;
-		minimum_next = minimum_reg;
-		amp_good_next = amp_good_reg;
-		amp_data_next = amp_data_reg;
-		uwt_data_next = uwt_data_reg;
+		int_case_next = int_case_reg;
+		int_mini_next = int_mini_reg;
+		inp_data_next = inp_data_reg;
+		out_data_next = out_data_reg;
+		out_flag_next = out_flag_reg;
+		int_flag_next = int_flag_reg;
+		int_comp_next = int_comp_reg;
 		
-		case (state_reg)
+		case (int_case_reg)
 			0:
 			begin
 				if (frame)
 				begin
-					uwt_data_next = uwt_data;
-					amp_good_next = 1'b0;
+					inp_data_next = inp_data;
+					int_comp_next = int_comp_wire;
+					out_data_next = {(width){1'b0}};
+					out_flag_next = 1'b0;
 					// minimum
-					if (uwt_flag[0])
+					if ((~int_comp_reg) & (int_comp_wire))
 					begin
-						minimum_next = uwt_data_reg;
+						int_mini_next = inp_data_reg;
+						int_flag_next = 1'b1;
 					end
-					else if ((uwt_flag[1]) & (uwt_data > minimum_reg))
+					// maximum
+					else if ((int_comp_reg) & (~int_comp_wire) & (int_flag_reg))
 					begin
-						amp_data_next = uwt_data - minimum_reg;
-						state_next = 1'b1;
+						out_data_next = inp_data_reg - int_mini_reg;
+						int_flag_next = 1'b0;
+						int_case_next = 1'b1;
 					end
                 end
@@ -65,6 +84,6 @@
 			1:
 			begin
-				amp_good_next = (amp_data_reg >= cfg_data);
-				state_next = 1'b0;
+				out_flag_next = (out_data_reg >= cfg_data);
+				int_case_next = 1'b0;
  			end
 
@@ -72,6 +91,6 @@
 	end
 
-	assign amp_good = amp_good_reg;
-	assign amp_data = amp_data_reg;
+	assign out_data = out_data_reg;
+	assign out_flag = out_flag_reg;
 
 endmodule
Index: sandbox/MultiChannelUSB/cic_filter.v
===================================================================
--- sandbox/MultiChannelUSB/cic_filter.v	(revision 122)
+++ sandbox/MultiChannelUSB/cic_filter.v	(revision 123)
@@ -12,6 +12,5 @@
 	);
 	
-	localparam	widthr	=	width + 18;
-
+	localparam	widthr	=	width + 16;
 	/*
 	4-bit LFSR with additional bits to keep track of previous values
@@ -76,9 +75,9 @@
 		.sel(int_chan_next),
 		.data({
-			2'd3, int_lfsr_reg[2*6+3:2*6], int_lfsr_reg[6+3:6],
-			2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
-			2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
+			2'd3, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
+			2'd2, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
+			2'd1, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3],
 			2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}),
-		.result(int_addr_wire));
+		.result(int_addr_wire));                            
 
 	always @(posedge clock)
Index: sandbox/MultiChannelUSB/deconv.v
===================================================================
--- sandbox/MultiChannelUSB/deconv.v	(revision 122)
+++ sandbox/MultiChannelUSB/deconv.v	(revision 123)
@@ -2,5 +2,7 @@
 	#(
 		parameter	size	=	1, // number of channels
-		parameter	width	=	24 // bit width of the input data
+		parameter	shift	=	24, // right shift of the result
+		parameter	width	=	27, // bit width of the input data
+		parameter	widthr	=	13 // bit width of the output data
 	)
 	(
@@ -9,5 +11,4 @@
 		input	wire	[3*size*8-1:0]		amp_data,
 		input	wire	[3*size*16-1:0]		tau_data,
-		input	wire	[3*size*6-1:0]		cls_data,
 		input	wire	[3*size*width-1:0]	inp_data,
 		output	wire	[3*size*widthr-1:0]	out_data
@@ -16,5 +17,5 @@
 	localparam	width1	=	width + 1;
 	localparam	width2	=	width + 6 + 1;
-	localparam	widthr	=	width + 16 + 3;
+	localparam	width3	=	width + 16 + 3;
 
 	reg							int_wren_reg, int_wren_next;
@@ -30,7 +31,7 @@
 	wire	[size*widthr-1:0]	out_data_wire;
 
-	wire	[size*widthr-1:0]	add_data_wire;
-
-	wire	[size*widthr-1:0]	mul_data_wire [1:0];
+	wire	[size*width3-1:0]	add_data_wire;
+
+	wire	[size*width3-1:0]	mul_data_wire [1:0];
 
 	reg		[size*width2-1:0]	acc_data_reg [3:0], acc_data_next [3:0];
@@ -47,7 +48,4 @@
 	reg		[size*16-1:0]		tau_data_reg, tau_data_next;
 	wire	[size*16-1:0]		tau_data_wire [2:0];
-
-	reg		[size*6-1:0]		cls_data_reg, cls_data_next;
-	wire	[size*6-1:0]		cls_data_wire [2:0];
 
 	integer i;
@@ -66,7 +64,4 @@
 			assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16];
 			assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16];
-			assign cls_data_wire[0][j*6+6-1:j*6] = cls_data[(3*j+0)*6+6-1:(3*j+0)*6];
-			assign cls_data_wire[1][j*6+6-1:j*6] = cls_data[(3*j+1)*6+6-1:(3*j+1)*6];
-			assign cls_data_wire[2][j*6+6-1:j*6] = cls_data[(3*j+2)*6+6-1:(3*j+2)*6];
                                                                                          
 			lpm_mux #(
@@ -119,10 +114,10 @@
 				.lpm_widtha(width1),
 				.lpm_widthb(17),
-				.lpm_widthp(widthr)) mult_unit_1 (
+				.lpm_widthp(width3)) mult_unit_1 (
 				.clock(clock),
 				.clken(int_wren_reg),
 				.dataa(sub_data_wire[j*width1+width1-1:j*width1]),
 				.datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
-				.result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
+				.result(mul_data_wire[0][j*width3+width3-1:j*width3]));
 
 			lpm_mult #(
@@ -133,10 +128,10 @@
 				.lpm_widtha(width2),
 				.lpm_widthb(8),
-				.lpm_widthp(widthr)) mult_unit_2 (
+				.lpm_widthp(width3)) mult_unit_2 (
 				.clock(clock),
 				.clken(int_wren_reg),
 				.dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
 				.datab(amp_data_reg[j*8+8-1:j*8]),
-				.result(mul_data_wire[1][j*widthr+widthr-1:j*widthr]));
+				.result(mul_data_wire[1][j*width3+width3-1:j*width3]));
 
 			lpm_add_sub	#(
@@ -145,18 +140,18 @@
 				.lpm_representation("SIGNED"),
 				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) add_unit_2 (
-				.dataa(mul_data_wire[0][j*widthr+widthr-1:j*widthr]),
-				.datab(mul_data_wire[1][j*widthr+widthr-1:j*widthr]),
-				.result(add_data_wire[j*widthr+widthr-1:j*widthr]));
-
-
-			lpm_clshift	#(
-				.lpm_shifttype("LOGICAL"),
-				.lpm_type("LPM_CLSHIFT"),
-				.lpm_width(widthr),
-				.lpm_widthdist(6)) shift_unit_1 (
-				.distance(cls_data_reg[j*6+6-1:j*6]),
-				.direction(1'b1),
-				.data(add_data_wire[j*widthr+widthr-1:j*widthr]),
+				.lpm_width(width3)) add_unit_2 (
+				.dataa(mul_data_wire[0][j*width3+width3-1:j*width3]),
+				.datab(mul_data_wire[1][j*width3+width3-1:j*width3]),
+				.result(add_data_wire[j*width3+width3-1:j*width3]));
+
+
+			lpm_add_sub	#(
+				.lpm_direction("ADD"),
+				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
+				.lpm_representation("UNSIGNED"),
+				.lpm_type("LPM_ADD_SUB"),
+				.lpm_width(widthr)) add_unit_3 (
+				.dataa(add_data_wire[j*width3+shift+widthr-1:j*width3+shift]),
+				.datab({{(widthr-1){1'b0}}, add_data_wire[j*width3+shift-1]}),
 				.result(out_data_wire[j*widthr+widthr-1:j*widthr]));
 
@@ -220,5 +215,4 @@
 			amp_data_reg <= 8'd0;
 			tau_data_reg <= 16'd0;
-			cls_data_reg <= 6'd0;
 			for(i = 0; i <= 2; i = i + 1)
 			begin
@@ -240,5 +234,4 @@
 			amp_data_reg <= amp_data_next;
 			tau_data_reg <= tau_data_next;
-			cls_data_reg <= cls_data_next;
 			for(i = 0; i <= 2; i = i + 1)
 			begin
@@ -262,5 +255,4 @@
 		amp_data_next = amp_data_reg;
 		tau_data_next = tau_data_reg;
-		cls_data_next = cls_data_reg;
 		for(i = 0; i <= 2; i = i + 1)
 		begin
@@ -282,5 +274,4 @@
 				amp_data_next = 8'd0;
 				tau_data_next = 16'd0;
-				cls_data_next = 6'd0;
 				for(i = 0; i <= 2; i = i + 1)
 				begin
@@ -327,5 +318,4 @@
 					tau_data_next = tau_data_wire[0];
 					amp_data_next = amp_data_wire[0];
-					cls_data_next = cls_data_wire[0];
 					
 					int_case_next = 3'd3;
@@ -346,5 +336,4 @@
 				tau_data_next = tau_data_wire[1];
 				amp_data_next = amp_data_wire[1];
-				cls_data_next = cls_data_wire[1];
 
 				// register 1st sum
@@ -364,5 +353,4 @@
 				tau_data_next = tau_data_wire[2];
 				amp_data_next = amp_data_wire[2];
-				cls_data_next = cls_data_wire[2];
 				
 				// register 2nd sum