Index: /sandbox/MultiChannelUSB/cic_filter.v
===================================================================
--- /sandbox/MultiChannelUSB/cic_filter.v	(revision 121)
+++ /sandbox/MultiChannelUSB/cic_filter.v	(revision 122)
@@ -12,5 +12,5 @@
 	);
 	
-	localparam	widthr	=	width + 13;
+	localparam	widthr	=	width + 18;
 
 	/*
@@ -20,4 +20,5 @@
 
 	reg							int_wren_reg, int_wren_next;
+	reg							int_flag_reg, int_flag_next;
 	reg		[1:0]				int_chan_reg, int_chan_next;
 	reg		[2:0]				int_case_reg, int_case_next;
@@ -27,5 +28,5 @@
 
 	reg		[size*widthr-1:0]	acc_data_reg [3:0], acc_data_next [3:0];
-	reg		[size*widthr-1:0]	int_data_reg [8:0], int_data_next [8:0];
+	reg		[size*widthr-1:0]	int_data_reg [12:0], int_data_next [12:0];
 
 	wire	[size*widthr-1:0]	acc_data_wire [3:0], del_data_wire [1:0];
@@ -69,5 +70,5 @@
 
 	lpm_mux #(
-		.lpm_size(3),
+		.lpm_size(4),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(10),
@@ -75,4 +76,5 @@
 		.sel(int_chan_next),
 		.data({
+			2'd3, int_lfsr_reg[2*6+3:2*6], int_lfsr_reg[6+3:6],
 			2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
 			2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
@@ -85,4 +87,5 @@
         begin
 			int_wren_reg <= 1'b1;
+			int_flag_reg <= 1'b0;
 			int_chan_reg <= 2'd0;
 			int_case_reg <= 3'd0;
@@ -92,5 +95,5 @@
 				acc_data_reg[i] <= {(size*widthr){1'b0}};
 			end
-			for(i = 0; i <= 8; i = i + 1)
+			for(i = 0; i <= 12; i = i + 1)
 			begin
 				int_data_reg[i] <= {(size*widthr){1'b0}};
@@ -101,4 +104,5 @@
 		begin
 			int_wren_reg <= int_wren_next;
+			int_flag_reg <= int_flag_next;
 			int_chan_reg <= int_chan_next;
 			int_case_reg <= int_case_next;
@@ -108,5 +112,5 @@
 				acc_data_reg[i] <= acc_data_next[i];
 			end
-			for(i = 0; i <= 8; i = i + 1)
+			for(i = 0; i <= 12; i = i + 1)
 			begin
 				int_data_reg[i] <= int_data_next[i];
@@ -119,4 +123,5 @@
 	begin
 		int_wren_next = int_wren_reg;
+		int_flag_next = int_flag_reg;
 		int_chan_next = int_chan_reg;
 		int_case_next = int_case_reg;
@@ -126,5 +131,5 @@
 			acc_data_next[i] = acc_data_reg[i];
 		end
-		for(i = 0; i <= 8; i = i + 1)
+		for(i = 0; i <= 12; i = i + 1)
 		begin
 			int_data_next[i] = int_data_reg[i];
@@ -142,5 +147,5 @@
 					acc_data_next[i] = {(size*widthr){1'b0}};
 				end
-				for(i = 0; i <= 8; i = i + 1)
+				for(i = 0; i <= 12; i = i + 1)
 				begin
 					int_data_next[i] = {(size*widthr){1'b0}};
@@ -155,4 +160,5 @@
 				begin
 					int_wren_next = 1'b0;
+					int_flag_next = 1'b0;
 					int_chan_next = 2'd0;
 					int_lfsr_next = 16'h7650;
@@ -162,4 +168,5 @@
 			2: // frame
 			begin
+				int_flag_next = 1'b0;
 				if (frame)
 				begin
@@ -179,5 +186,11 @@
 					int_case_next = 3'd3;
 				end
-
+				if (int_flag_reg) // register 4th sum
+				begin
+					// register 4th sum
+					int_data_next[9] = acc_data_wire[1];
+					int_data_next[10] = acc_data_wire[2];
+					int_data_next[11] = acc_data_wire[3];
+				end
 			end
 			3:  // 1st sum
@@ -204,4 +217,7 @@
 			begin
 				int_addr_next = {4'd2, int_lfsr_reg[3:0]};
+
+				// set read addr for 4th pipeline
+				int_chan_next = 2'd3;
 
 				// prepare registers for 3rd sum	
@@ -222,8 +238,16 @@
 			5:  // 3rd sum
 			begin				
-				int_wren_next = 1'b0;
+				int_flag_next = 1'b1;
+
+				int_addr_next = {4'd3, int_lfsr_reg[4:1]};
 
 				// set read addr for 1st pipeline
 				int_chan_next = 2'd0;
+
+				// prepare registers for 4th sum	
+				acc_data_next[0] = int_data_reg[8];
+				acc_data_next[1] = int_data_reg[9];
+				acc_data_next[2] = int_data_reg[10];
+				acc_data_next[3] = int_data_reg[11];
 
 				// register 3rd sum
@@ -231,4 +255,7 @@
 				int_data_next[7] = acc_data_wire[2];
 				int_data_next[8] = acc_data_wire[3];
+				
+				// register 4th output
+				int_data_next[12] = int_data_reg[11];
 
 				int_case_next = 3'd2;
@@ -241,7 +268,7 @@
 	end
 
-	assign out_data = int_data_reg[2];
-	assign out_data2 = int_data_reg[5];
-	assign out_data3 = int_data_reg[8];
+	assign out_data = int_data_reg[5];
+	assign out_data2 = int_data_reg[8];
+	assign out_data3 = int_data_reg[12];
 
 endmodule