Changeset 122 for sandbox/MultiChannelUSB

Timestamp:

Feb 18, 2011, 12:29:10 AM (14 years ago)

Author:

demin

Message:

add 4th stage

File:

• sandbox/MultiChannelUSB/cic_filter.v (modified) (19 diffs)

sandbox/MultiChannelUSB/cic_filter.v

@@ -12 +12 @@
         );
         
-        localparam      widthr  =       width + 13;
+        localparam      widthr  =       width + 18;
 
         /*
@@ -20 +20 @@
 
         reg                                                     int_wren_reg, int_wren_next;
+        reg                                                     int_flag_reg, int_flag_next;
         reg             [1:0]                           int_chan_reg, int_chan_next;
         reg             [2:0]                           int_case_reg, int_case_next;
@@ -27 +28 @@
 
         reg             [size*widthr-1:0]       acc_data_reg [3:0], acc_data_next [3:0];
-        reg             [size*widthr-1:0]       int_data_reg [8:0], int_data_next [8:0];
+        reg             [size*widthr-1:0]       int_data_reg [12:0], int_data_next [12:0];
 
         wire    [size*widthr-1:0]       acc_data_wire [3:0], del_data_wire [1:0];
@@ -69 +70 @@
 
         lpm_mux #(
-                .lpm_size(3),
+                .lpm_size(4),
                 .lpm_type("LPM_MUX"),
                 .lpm_width(10),
@@ -75 +76 @@
                 .sel(int_chan_next),
                 .data({
+                        2'd3, int_lfsr_reg[2*6+3:2*6], int_lfsr_reg[6+3:6],
                         2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
                         2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
@@ -85 +87 @@
         begin
                         int_wren_reg <= 1'b1;
+                        int_flag_reg <= 1'b0;
                         int_chan_reg <= 2'd0;
                         int_case_reg <= 3'd0;
@@ -92 +95 @@
                                 acc_data_reg[i] <= {(size*widthr){1'b0}};
                         end
-                        for(i = 0; i <= 8; i = i + 1)
+                        for(i = 0; i <= 12; i = i + 1)
                         begin
                                 int_data_reg[i] <= {(size*widthr){1'b0}};
@@ -101 +104 @@
                 begin
                         int_wren_reg <= int_wren_next;
+                        int_flag_reg <= int_flag_next;
                         int_chan_reg <= int_chan_next;
                         int_case_reg <= int_case_next;
@@ -108 +112 @@
                                 acc_data_reg[i] <= acc_data_next[i];
                         end
-                        for(i = 0; i <= 8; i = i + 1)
+                        for(i = 0; i <= 12; i = i + 1)
                         begin
                                 int_data_reg[i] <= int_data_next[i];
@@ -119 +123 @@
         begin
                 int_wren_next = int_wren_reg;
+                int_flag_next = int_flag_reg;
                 int_chan_next = int_chan_reg;
                 int_case_next = int_case_reg;
@@ -126 +131 @@
                         acc_data_next[i] = acc_data_reg[i];
                 end
-                for(i = 0; i <= 8; i = i + 1)
+                for(i = 0; i <= 12; i = i + 1)
                 begin
                         int_data_next[i] = int_data_reg[i];
@@ -142 +147 @@
                                         acc_data_next[i] = {(size*widthr){1'b0}};
                                 end
-                                for(i = 0; i <= 8; i = i + 1)
+                                for(i = 0; i <= 12; i = i + 1)
                                 begin
                                         int_data_next[i] = {(size*widthr){1'b0}};
@@ -155 +160 @@
                                 begin
                                         int_wren_next = 1'b0;
+                                        int_flag_next = 1'b0;
                                         int_chan_next = 2'd0;
                                         int_lfsr_next = 16'h7650;
@@ -162 +168 @@
                         2: // frame
                         begin
+                                int_flag_next = 1'b0;
                                 if (frame)
                                 begin
@@ -179 +186 @@
                                         int_case_next = 3'd3;
                                 end
-
+                                if (int_flag_reg) // register 4th sum
+                                begin
+                                        // register 4th sum
+                                        int_data_next[9] = acc_data_wire[1];
+                                        int_data_next[10] = acc_data_wire[2];
+                                        int_data_next[11] = acc_data_wire[3];
+                                end
                         end
                         3:  // 1st sum
@@ -204 +217 @@
                         begin
                                 int_addr_next = {4'd2, int_lfsr_reg[3:0]};
+
+                                // set read addr for 4th pipeline
+                                int_chan_next = 2'd3;
 
                                 // prepare registers for 3rd sum        
@@ -222 +238 @@
                         5:  // 3rd sum
                         begin                           
-                                int_wren_next = 1'b0;
+                                int_flag_next = 1'b1;
+
+                                int_addr_next = {4'd3, int_lfsr_reg[4:1]};
 
                                 // set read addr for 1st pipeline
                                 int_chan_next = 2'd0;
+
+                                // prepare registers for 4th sum        
+                                acc_data_next[0] = int_data_reg[8];
+                                acc_data_next[1] = int_data_reg[9];
+                                acc_data_next[2] = int_data_reg[10];
+                                acc_data_next[3] = int_data_reg[11];
 
                                 // register 3rd sum
@@ -231 +255 @@
                                 int_data_next[7] = acc_data_wire[2];
                                 int_data_next[8] = acc_data_wire[3];
+                                
+                                // register 4th output
+                                int_data_next[12] = int_data_reg[11];
 
                                 int_case_next = 3'd2;
@@ -241 +268 @@
         end
 
-        assign out_data = int_data_reg[2];
-        assign out_data2 = int_data_reg[5];
-        assign out_data3 = int_data_reg[8];
+        assign out_data = int_data_reg[5];
+        assign out_data2 = int_data_reg[8];
+        assign out_data3 = int_data_reg[12];
 
 endmodule