Index: /sandbox/MultiChannelUSB/cic_filter.v
===================================================================
--- /sandbox/MultiChannelUSB/cic_filter.v	(revision 120)
+++ /sandbox/MultiChannelUSB/cic_filter.v	(revision 121)
@@ -26,11 +26,8 @@
 	wire	[9:0]				int_addr_wire;
 
-	reg		[size*widthr-1:0]	acc_data_reg [2:0], acc_data_next [2:0];
-	reg		[size*widthr-1:0]	int_data_reg [5:0], int_data_next [5:0];
-
-	wire	[size*widthr-1:0]	acc_data_wire [2:0], del_data_wire [1:0];
-
-	wire	[size*widthr-1:0]	add_data_wire, sub_data_wire;
-
+	reg		[size*widthr-1:0]	acc_data_reg [3:0], acc_data_next [3:0];
+	reg		[size*widthr-1:0]	int_data_reg [8:0], int_data_next [8:0];
+
+	wire	[size*widthr-1:0]	acc_data_wire [3:0], del_data_wire [1:0];
 
 	integer i;
@@ -44,43 +41,16 @@
 			// -2*del_data_1 + del_data_2 + inp_data + result
 
-			lpm_add_sub	#(
-				.lpm_direction("ADD"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("SIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) add_unit_1 (
-				.dataa(acc_data_reg[0][j*widthr+widthr-1:j*widthr]),
-				.datab(del_data_wire[1][j*widthr+widthr-1:j*widthr]),
-				.result(add_data_wire[j*widthr+widthr-1:j*widthr]));
-
-			lpm_add_sub	#(
-				.lpm_direction("SUB"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("SIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) sub_unit_1 (
-				.dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
-				.datab({del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0}),
-				.result(sub_data_wire[j*widthr+widthr-1:j*widthr]));
-
-			lpm_add_sub	#(
-				.lpm_direction("ADD"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("SIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) acc_unit_1 (
-				.dataa(add_data_wire[j*widthr+widthr-1:j*widthr]),
-				.datab(sub_data_wire[j*widthr+widthr-1:j*widthr]),
-				.result(acc_data_wire[1][j*widthr+widthr-1:j*widthr]));
-
-			lpm_add_sub	#(
-				.lpm_direction("ADD"),
-				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
-				.lpm_representation("SIGNED"),
-				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) acc_unit_2 (
-				.dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
-				.datab(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
-				.result(acc_data_wire[2][j*widthr+widthr-1:j*widthr]));
+			assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
+				  acc_data_reg[0][j*widthr+widthr-1:j*widthr]
+				+ del_data_wire[1][j*widthr+widthr-1:j*widthr]
+				- {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0};
+
+			assign acc_data_wire[2][j*widthr+widthr-1:j*widthr] =
+				  acc_data_reg[1][j*widthr+widthr-1:j*widthr]
+				+ acc_data_reg[2][j*widthr+widthr-1:j*widthr];
+
+			assign acc_data_wire[3][j*widthr+widthr-1:j*widthr] =
+				  acc_data_reg[2][j*widthr+widthr-1:j*widthr]
+				+ acc_data_reg[3][j*widthr+widthr-1:j*widthr];
 
 		end
@@ -118,9 +88,9 @@
 			int_case_reg <= 3'd0;
 			int_addr_reg <= 8'd0;
-			for(i = 0; i <= 2; i = i + 1)
+			for(i = 0; i <= 3; i = i + 1)
 			begin
 				acc_data_reg[i] <= {(size*widthr){1'b0}};
 			end
-			for(i = 0; i <= 5; i = i + 1)
+			for(i = 0; i <= 8; i = i + 1)
 			begin
 				int_data_reg[i] <= {(size*widthr){1'b0}};
@@ -134,9 +104,9 @@
 			int_case_reg <= int_case_next;
 			int_addr_reg <= int_addr_next;
-			for(i = 0; i <= 2; i = i + 1)
+			for(i = 0; i <= 3; i = i + 1)
 			begin
 				acc_data_reg[i] <= acc_data_next[i];
 			end
-			for(i = 0; i <= 5; i = i + 1)
+			for(i = 0; i <= 8; i = i + 1)
 			begin
 				int_data_reg[i] <= int_data_next[i];
@@ -152,9 +122,9 @@
 		int_case_next = int_case_reg;
 		int_addr_next = int_addr_reg;
-		for(i = 0; i <= 2; i = i + 1)
+		for(i = 0; i <= 3; i = i + 1)
 		begin
 			acc_data_next[i] = acc_data_reg[i];
 		end
-		for(i = 0; i <= 5; i = i + 1)
+		for(i = 0; i <= 8; i = i + 1)
 		begin
 			int_data_next[i] = int_data_reg[i];
@@ -168,9 +138,9 @@
 				int_wren_next = 1'b1;
 				int_addr_next = 8'd0;
-				for(i = 0; i <= 2; i = i + 1)
+				for(i = 0; i <= 3; i = i + 1)
 				begin
 					acc_data_next[i] = {(size*widthr){1'b0}};
 				end
-				for(i = 0; i <= 5; i = i + 1)
+				for(i = 0; i <= 8; i = i + 1)
 				begin
 					int_data_next[i] = {(size*widthr){1'b0}};
@@ -205,4 +175,5 @@
 					acc_data_next[1] = int_data_reg[0];
 					acc_data_next[2] = int_data_reg[1];
+					acc_data_next[3] = int_data_reg[2];
 					
 					int_case_next = 3'd3;
@@ -218,11 +189,13 @@
 
 				// prepare registers for 2nd sum	
-				acc_data_next[0] = int_data_reg[1];
-				acc_data_next[1] = int_data_reg[2];
-				acc_data_next[2] = int_data_reg[3];
+				acc_data_next[0] = int_data_reg[2];
+				acc_data_next[1] = int_data_reg[3];
+				acc_data_next[2] = int_data_reg[4];
+				acc_data_next[3] = int_data_reg[5];
 
 				// register 1st sum
 				int_data_next[0] = acc_data_wire[1];
 				int_data_next[1] = acc_data_wire[2];
+				int_data_next[2] = acc_data_wire[3];
 
 				int_case_next = 3'd4;
@@ -233,11 +206,13 @@
 
 				// prepare registers for 3rd sum	
-				acc_data_next[0] = int_data_reg[3];
-				acc_data_next[1] = int_data_reg[4];
-				acc_data_next[2] = int_data_reg[5];
+				acc_data_next[0] = int_data_reg[5];
+				acc_data_next[1] = int_data_reg[6];
+				acc_data_next[2] = int_data_reg[7];
+				acc_data_next[3] = int_data_reg[8];
 
 				// register 2nd sum
-				int_data_next[2] = acc_data_wire[1];
-				int_data_next[3] = acc_data_wire[2];
+				int_data_next[3] = acc_data_wire[1];
+				int_data_next[4] = acc_data_wire[2];
+				int_data_next[5] = acc_data_wire[3];
 				
 				int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
@@ -253,6 +228,7 @@
 
 				// register 3rd sum
-				int_data_next[4] = acc_data_wire[1];
-				int_data_next[5] = acc_data_wire[2];
+				int_data_next[6] = acc_data_wire[1];
+				int_data_next[7] = acc_data_wire[2];
+				int_data_next[8] = acc_data_wire[3];
 
 				int_case_next = 3'd2;
@@ -265,7 +241,7 @@
 	end
 
-	assign out_data = int_data_reg[1];
-	assign out_data2 = int_data_reg[3];
-	assign out_data3 = int_data_reg[5];
+	assign out_data = int_data_reg[2];
+	assign out_data2 = int_data_reg[5];
+	assign out_data3 = int_data_reg[8];
 
 endmodule