Index: /sandbox/MultiChannelUSB/deconv.v
===================================================================
--- /sandbox/MultiChannelUSB/deconv.v	(revision 116)
+++ /sandbox/MultiChannelUSB/deconv.v	(revision 117)
@@ -2,5 +2,5 @@
 	#(
 		parameter	size	=	1, // number of channels
-		parameter	width	=	16 // bit width of the input data
+		parameter	width	=	24 // bit width of the input data
 	)
 	(
@@ -29,5 +29,4 @@
 	wire	[size*widthr-1:0]	out_data_wire;
 
-	reg		[size*widthr-1:0]	mul_data_reg [7:0], mul_data_next [7:0];
 	wire	[size*widthr-1:0]	mul_data_wire [1:0];
 
@@ -35,5 +34,4 @@
 	wire	[size*width2-1:0]	acc_data_wire;
 
-	reg		[size*width1-1:0]	sub_data_reg [3:0], sub_data_next [3:0];
 	wire	[size*width1-1:0]	sub_data_wire;
 
@@ -101,5 +99,5 @@
 				.lpm_type("LPM_ADD_SUB"),
 				.lpm_width(width2)) acc_unit_1 (
-				.dataa({{(width2-width1+1){sub_data_reg[0][j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
+				.dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
 				.datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
 				.result(acc_data_wire[j*width2+width2-1:j*width2]));
@@ -115,5 +113,5 @@
 				.clock(clock),
 				.clken(int_wren_reg),
-				.dataa(sub_data_reg[0][j*width1+width1-1:j*width1]),
+				.dataa(sub_data_wire[j*width1+width1-1:j*width1]),
 				.datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
 				.result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
@@ -139,8 +137,19 @@
 				.lpm_type("LPM_ADD_SUB"),
 				.lpm_width(widthr)) add_unit_2 (
-				.dataa(mul_data_reg[0][j*widthr+widthr-1:j*widthr]),
-				.datab(mul_data_reg[1][j*widthr+widthr-1:j*widthr]),
+				.dataa(mul_data_wire[0][j*widthr+widthr-1:j*widthr]),
+				.datab(mul_data_wire[1][j*widthr+widthr-1:j*widthr]),
 				.result(out_data_wire[j*widthr+widthr-1:j*widthr]));
 
+/*
+			lpm_clshift	#(
+				.lpm_shifttype("LOGICAL"),
+				.lpm_type("LPM_CLSHIFT"),
+				.lpm_width(64),
+				.lpm_widthdist(6)) shift_unit_1 (
+				.distance(distance),
+				.direction(sub_wire1),
+				.data(data),
+				.result(sub_wire0));
+*/
 		end
 	endgenerate
@@ -209,10 +218,5 @@
 			for(i = 0; i <= 3; i = i + 1)
 			begin
-				sub_data_reg[i] <= {(size*width1){1'b0}};
 				acc_data_reg[i] <= {(size*width2){1'b0}};
-			end
-			for(i = 0; i <= 7; i = i + 1)
-			begin
-				mul_data_reg[i] <= {(size*widthr){1'b0}};
 			end
 		end
@@ -233,11 +237,6 @@
 			for(i = 0; i <= 3; i = i + 1)
 			begin
-				sub_data_reg[i] <= sub_data_next[i];
 				acc_data_reg[i] <= acc_data_next[i];
 			end                  
-			for(i = 0; i <= 7; i = i + 1)
-			begin
-				mul_data_reg[i] <= mul_data_next[i];
-			end
 		end             
 	end
@@ -259,11 +258,6 @@
 		for(i = 0; i <= 3; i = i + 1)
 		begin
-			sub_data_next[i] = sub_data_reg[i];
 			acc_data_next[i] = acc_data_reg[i];
 		end                  
-		for(i = 0; i <= 7; i = i + 1)
-		begin
-			mul_data_next[i] = mul_data_reg[i];
-		end
 
 		case (int_case_reg)		
@@ -283,11 +277,6 @@
 				for(i = 0; i <= 3; i = i + 1)
 				begin
-					sub_data_next[i] = {(size*width1){1'b0}};
 					acc_data_next[i] = {(size*width2){1'b0}};
 				end                  
-				for(i = 0; i <= 7; i = i + 1)
-				begin
-					mul_data_next[i] = {(size*widthr){1'b0}};
-				end
 
 				int_case_next = 3'd1;
@@ -321,11 +310,6 @@
 					// prepare registers for 1st sum					
 					inp_data_next[0] = inp_data_wire[0];
-
-					sub_data_next[0] = sub_data_reg[1];
 					acc_data_next[0] = acc_data_reg[1];
 
-					mul_data_next[0] = mul_data_reg[2];
-					mul_data_next[1] = mul_data_reg[3];
-					
 					tau_data_next = tau_data_wire[0];
 					amp_data_next = amp_data_wire[0];
@@ -344,19 +328,11 @@
 				// prepare registers for 2nd sum
 				inp_data_next[0] = inp_data_reg[1];
-					
-				sub_data_next[0] = sub_data_reg[2];
 				acc_data_next[0] = acc_data_reg[2];
 				
-				mul_data_next[0] = mul_data_reg[4];
-				mul_data_next[1] = mul_data_reg[5];
-
 				tau_data_next = tau_data_wire[1];
 				amp_data_next = amp_data_wire[1];
 
 				// register 1st sum
-				sub_data_next[1] = sub_data_wire;
 				acc_data_next[1] = acc_data_wire;
-				mul_data_next[2] = mul_data_wire[0];
-				mul_data_next[3] = mul_data_wire[1];
 				out_data_next[0] = out_data_wire;
 
@@ -369,10 +345,5 @@
 				// prepare registers for 3rd sum	
 				inp_data_next[0] = inp_data_reg[2];
-
-				sub_data_next[0] = sub_data_reg[3];
 				acc_data_next[0] = acc_data_reg[3];
-
-				mul_data_next[0] = mul_data_reg[6];
-				mul_data_next[1] = mul_data_reg[7];
 
 				tau_data_next = tau_data_wire[2];
@@ -380,8 +351,5 @@
 				
 				// register 2nd sum
-				sub_data_next[2] = sub_data_wire;
 				acc_data_next[2] = acc_data_wire;
-				mul_data_next[4] = mul_data_wire[0];
-				mul_data_next[5] = mul_data_wire[1];
 				out_data_next[1] = out_data_wire;
 				
@@ -398,8 +366,5 @@
 
 				// register 3rd sum
-				sub_data_next[3] = sub_data_wire;
 				acc_data_next[3] = acc_data_wire;
-				mul_data_next[6] = mul_data_wire[0];
-				mul_data_next[7] = mul_data_wire[1];
 				out_data_next[2] = out_data_wire;