Changeset 117 for sandbox/MultiChannelUSB

Timestamp:

Feb 15, 2011, 10:42:52 PM (14 years ago)

Author:

demin

Message:

remove unnecessary registers

File:

• sandbox/MultiChannelUSB/deconv.v (modified) (15 diffs)

sandbox/MultiChannelUSB/deconv.v

@@ -2 +2 @@
         #(
                 parameter       size    =       1, // number of channels
-                parameter       width   =       16 // bit width of the input data
+                parameter       width   =       24 // bit width of the input data
         )
         (
@@ -29 +29 @@
         wire    [size*widthr-1:0]       out_data_wire;
 
-        reg             [size*widthr-1:0]       mul_data_reg [7:0], mul_data_next [7:0];
         wire    [size*widthr-1:0]       mul_data_wire [1:0];
 
@@ -35 +34 @@
         wire    [size*width2-1:0]       acc_data_wire;
 
-        reg             [size*width1-1:0]       sub_data_reg [3:0], sub_data_next [3:0];
         wire    [size*width1-1:0]       sub_data_wire;
 
@@ -101 +99 @@
                                 .lpm_type("LPM_ADD_SUB"),
                                 .lpm_width(width2)) acc_unit_1 (
-                                .dataa({{(width2-width1+1){sub_data_reg[0][j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
+                                .dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
                                 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
                                 .result(acc_data_wire[j*width2+width2-1:j*width2]));
@@ -115 +113 @@
                                 .clock(clock),
                                 .clken(int_wren_reg),
-                                .dataa(sub_data_reg[0][j*width1+width1-1:j*width1]),
+                                .dataa(sub_data_wire[j*width1+width1-1:j*width1]),
                                 .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
                                 .result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
@@ -139 +137 @@
                                 .lpm_type("LPM_ADD_SUB"),
                                 .lpm_width(widthr)) add_unit_2 (
-                                .dataa(mul_data_reg[0][j*widthr+widthr-1:j*widthr]),
-                                .datab(mul_data_reg[1][j*widthr+widthr-1:j*widthr]),
+                                .dataa(mul_data_wire[0][j*widthr+widthr-1:j*widthr]),
+                                .datab(mul_data_wire[1][j*widthr+widthr-1:j*widthr]),
                                 .result(out_data_wire[j*widthr+widthr-1:j*widthr]));
 
+/*
+                        lpm_clshift     #(
+                                .lpm_shifttype("LOGICAL"),
+                                .lpm_type("LPM_CLSHIFT"),
+                                .lpm_width(64),
+                                .lpm_widthdist(6)) shift_unit_1 (
+                                .distance(distance),
+                                .direction(sub_wire1),
+                                .data(data),
+                                .result(sub_wire0));
+*/
                 end
         endgenerate
@@ -209 +218 @@
                         for(i = 0; i <= 3; i = i + 1)
                         begin
-                                sub_data_reg[i] <= {(size*width1){1'b0}};
                                 acc_data_reg[i] <= {(size*width2){1'b0}};
-                        end
-                        for(i = 0; i <= 7; i = i + 1)
-                        begin
-                                mul_data_reg[i] <= {(size*widthr){1'b0}};
                         end
                 end
@@ -233 +237 @@
                         for(i = 0; i <= 3; i = i + 1)
                         begin
-                                sub_data_reg[i] <= sub_data_next[i];
                                 acc_data_reg[i] <= acc_data_next[i];
                         end                  
-                        for(i = 0; i <= 7; i = i + 1)
-                        begin
-                                mul_data_reg[i] <= mul_data_next[i];
-                        end
                 end             
         end
@@ -259 +258 @@
                 for(i = 0; i <= 3; i = i + 1)
                 begin
-                        sub_data_next[i] = sub_data_reg[i];
                         acc_data_next[i] = acc_data_reg[i];
                 end                  
-                for(i = 0; i <= 7; i = i + 1)
-                begin
-                        mul_data_next[i] = mul_data_reg[i];
-                end
 
                 case (int_case_reg)             
@@ -283 +277 @@
                                 for(i = 0; i <= 3; i = i + 1)
                                 begin
-                                        sub_data_next[i] = {(size*width1){1'b0}};
                                         acc_data_next[i] = {(size*width2){1'b0}};
                                 end                  
-                                for(i = 0; i <= 7; i = i + 1)
-                                begin
-                                        mul_data_next[i] = {(size*widthr){1'b0}};
-                                end
 
                                 int_case_next = 3'd1;
@@ -321 +310 @@
                                         // prepare registers for 1st sum                                        
                                         inp_data_next[0] = inp_data_wire[0];
-
-                                        sub_data_next[0] = sub_data_reg[1];
                                         acc_data_next[0] = acc_data_reg[1];
 
-                                        mul_data_next[0] = mul_data_reg[2];
-                                        mul_data_next[1] = mul_data_reg[3];
-                                        
                                         tau_data_next = tau_data_wire[0];
                                         amp_data_next = amp_data_wire[0];
@@ -344 +328 @@
                                 // prepare registers for 2nd sum
                                 inp_data_next[0] = inp_data_reg[1];
-                                        
-                                sub_data_next[0] = sub_data_reg[2];
                                 acc_data_next[0] = acc_data_reg[2];
                                 
-                                mul_data_next[0] = mul_data_reg[4];
-                                mul_data_next[1] = mul_data_reg[5];
-
                                 tau_data_next = tau_data_wire[1];
                                 amp_data_next = amp_data_wire[1];
 
                                 // register 1st sum
-                                sub_data_next[1] = sub_data_wire;
                                 acc_data_next[1] = acc_data_wire;
-                                mul_data_next[2] = mul_data_wire[0];
-                                mul_data_next[3] = mul_data_wire[1];
                                 out_data_next[0] = out_data_wire;
 
@@ -369 +345 @@
                                 // prepare registers for 3rd sum        
                                 inp_data_next[0] = inp_data_reg[2];
-
-                                sub_data_next[0] = sub_data_reg[3];
                                 acc_data_next[0] = acc_data_reg[3];
-
-                                mul_data_next[0] = mul_data_reg[6];
-                                mul_data_next[1] = mul_data_reg[7];
 
                                 tau_data_next = tau_data_wire[2];
@@ -380 +351 @@
                                 
                                 // register 2nd sum
-                                sub_data_next[2] = sub_data_wire;
                                 acc_data_next[2] = acc_data_wire;
-                                mul_data_next[4] = mul_data_wire[0];
-                                mul_data_next[5] = mul_data_wire[1];
                                 out_data_next[1] = out_data_wire;
                                 
@@ -398 +366 @@
 
                                 // register 3rd sum
-                                sub_data_next[3] = sub_data_wire;
                                 acc_data_next[3] = acc_data_wire;
-                                mul_data_next[6] = mul_data_wire[0];
-                                mul_data_next[7] = mul_data_wire[1];
                                 out_data_next[2] = out_data_wire;