Changeset 116
- Timestamp:
- Feb 14, 2011, 11:53:48 PM (14 years ago)
- Location:
- sandbox/MultiChannelUSB
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
sandbox/MultiChannelUSB/average.v
r115 r116 8 8 input wire [3*size*6-1:0] del_data, 9 9 input wire [3*size*width-1:0] inp_data, 10 output wire [3*size*width 1-1:0] out_data10 output wire [3*size*width2-1:0] out_data 11 11 ); 12 12 13 14 localparam width 1= width + 6 + 1;13 localparam width1 = width + 1; 14 localparam width2 = width + 6 + 1; 15 15 16 16 reg int_wren_reg, int_wren_next; … … 23 23 wire [7:0] int_addr_wire; 24 24 25 reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0]; 26 wire [size*width2-1:0] acc_data_wire; 27 28 reg [size*width1-1:0] sub_data_reg [3:0], sub_data_next [3:0]; 29 wire [size*width1-1:0] sub_data_wire; 30 25 31 reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0]; 26 32 wire [size*width-1:0] inp_data_wire [3:0]; 27 28 reg [size*width1-1:0] out_data_reg [2:0], out_data_next [2:0];29 wire [size*width1-1:0] out_data_wire;30 31 reg [size*width1-1:0] acc_data_reg [3:0], acc_data_next [3:0];32 wire [size*width1-1:0] acc_data_wire;33 34 reg [size*width1-1:0] sub_data_reg [3:0], sub_data_next [3:0];35 wire [size*width1-1:0] sub_data_wire;36 33 37 34 integer i; … … 82 79 .lpm_representation("SIGNED"), 83 80 .lpm_type("LPM_ADD_SUB"), 84 .lpm_width(width 1)) acc_unit_1 (85 .dataa({ sub_data_reg[0][j*width1+width1-1], {(width1-width1){1'b0}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),86 .datab(acc_data_reg[0][j*width 1+width1-1:j*width1]),87 .result(acc_data_wire[j*width 1+width1-1:j*width1]));81 .lpm_width(width2)) acc_unit_1 ( 82 .dataa({{(width2-width1+1){sub_data_reg[0][j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}), 83 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]), 84 .result(acc_data_wire[j*width2+width2-1:j*width2])); 88 85 89 86 end … … 147 144 begin 148 145 inp_data_reg[i] <= {(size*width){1'b0}}; 149 out_data_reg[i] <= {(size*width1){1'b0}};150 146 end 151 147 for(i = 0; i <= 3; i = i + 1) 152 148 begin 153 149 sub_data_reg[i] <= {(size*width1){1'b0}}; 154 acc_data_reg[i] <= {(size*width 1){1'b0}};150 acc_data_reg[i] <= {(size*width2){1'b0}}; 155 151 end 156 152 end … … 165 161 begin 166 162 inp_data_reg[i] <= inp_data_next[i]; 167 out_data_reg[i] <= out_data_next[i];168 163 end 169 164 for(i = 0; i <= 3; i = i + 1) … … 185 180 begin 186 181 inp_data_next[i] = inp_data_reg[i]; 187 out_data_next[i] = out_data_reg[i];188 182 end 189 183 for(i = 0; i <= 3; i = i + 1) … … 203 197 begin 204 198 inp_data_next[i] = {(size*width){1'b0}}; 205 out_data_next[i] = {(size*width1){1'b0}};206 199 end 207 200 for(i = 0; i <= 3; i = i + 1) 208 201 begin 209 202 sub_data_next[i] = {(size*width1){1'b0}}; 210 acc_data_next[i] = {(size*width 1){1'b0}};203 acc_data_next[i] = {(size*width2){1'b0}}; 211 204 end 212 205 … … 265 258 sub_data_next[1] = sub_data_wire; 266 259 acc_data_next[1] = acc_data_wire; 267 out_data_next[0] = acc_data_wire;268 260 269 261 int_case_next = 3'd4; … … 282 274 sub_data_next[2] = sub_data_wire; 283 275 acc_data_next[2] = acc_data_wire; 284 out_data_next[1] = acc_data_wire;285 276 286 277 del_addr_next = del_addr_reg + 6'd1; … … 298 289 sub_data_next[3] = sub_data_wire; 299 290 acc_data_next[3] = acc_data_wire; 300 out_data_next[2] = acc_data_wire;301 291 302 292 int_addr_next[5:0] = del_addr_reg; … … 311 301 end 312 302 313 assign out_data = { out_data_reg[2], out_data_reg[1], out_data_reg[0]};303 assign out_data = {acc_data_reg[3], acc_data_reg[2], acc_data_reg[1]}; 314 304 315 305 endmodule -
sandbox/MultiChannelUSB/deconv.v
r114 r116 10 10 input wire [3*size*16-1:0] tau_data, 11 11 input wire [3*size*width-1:0] inp_data, 12 output wire [3*size*widthr-1:0] out_data, 13 output wire [3*size*width2-1:0] acc_data 12 output wire [3*size*widthr-1:0] out_data 14 13 ); 15 14 … … 102 101 .lpm_type("LPM_ADD_SUB"), 103 102 .lpm_width(width2)) acc_unit_1 ( 104 .dataa({sub_data_reg[0][j*width1+width1-1], {(width2-width1){1'b0}}, sub_data_reg[0][j*width1+width1-2:j*width1]}), 105 // .dataa({width2{1'b0}}), 103 .dataa({{(width2-width1+1){sub_data_reg[0][j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}), 106 104 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]), 107 105 .result(acc_data_wire[j*width2+width2-1:j*width2])); … … 418 416 419 417 assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]}; 420 assign acc_data = {acc_data_reg[3], acc_data_reg[2], acc_data_reg[1]};421 // assign acc_data = {17'd0, del_addr_wire, 17'd0, del_addr_wire, 17'd0, del_addr_wire};422 418 423 419 endmodule
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