Index: sandbox/MultiChannelUSB/deconv.v
===================================================================
--- sandbox/MultiChannelUSB/deconv.v	(revision 113)
+++ sandbox/MultiChannelUSB/deconv.v	(revision 114)
@@ -6,13 +6,15 @@
 	(
 		input	wire						clock, frame, reset,
-		input	wire	[14:0]				del_data,
-		input	wire	[3*size*32-1:0]		mul_data,
+		input	wire	[3*size*6-1:0]		del_data,
+		input	wire	[3*size*8-1:0]		amp_data,
+		input	wire	[3*size*16-1:0]		tau_data,
 		input	wire	[3*size*width-1:0]	inp_data,
-		output	wire	[3*size*widthr-1:0]	out_data
+		output	wire	[3*size*widthr-1:0]	out_data,
+		output	wire	[3*size*width2-1:0]	acc_data
 	);
 
-	localparam	width1	=	width + 6 + 1;
-	localparam	width2	=	width + 6 + 6;
-	localparam	widthr	=	2*(width + 8);
+	localparam	width1	=	width + 1;
+	localparam	width2	=	width + 6 + 1;
+	localparam	widthr	=	width + 16 + 3;
 
 	reg							int_wren_reg, int_wren_next;
@@ -21,13 +23,28 @@
 	reg		[7:0]				int_addr_reg, int_addr_next;
 
+	reg		[5:0]				del_addr_reg, del_addr_next;
+	wire	[5:0]				del_addr_wire;
 	wire	[7:0]				int_addr_wire;
-	wire	[5:0]				del_addr_wire;
-
-	reg		[size*widthr-1:0]	acc_data_reg [6:0], acc_data_next [6:0];
-	reg		[size*widthr-1:0]	int_data_reg [17:0], int_data_next [17:0];
-
-	wire	[size*widthr-1:0]	int_data_wire [8:0];
-
-	wire	[size*widthr-1:0]	mul_data_wire [5:0];
+
+	reg		[size*widthr-1:0]	out_data_reg [2:0], out_data_next [2:0];
+	wire	[size*widthr-1:0]	out_data_wire;
+
+	reg		[size*widthr-1:0]	mul_data_reg [7:0], mul_data_next [7:0];
+	wire	[size*widthr-1:0]	mul_data_wire [1:0];
+
+	reg		[size*width2-1:0]	acc_data_reg [3:0], acc_data_next [3:0];
+	wire	[size*width2-1:0]	acc_data_wire;
+
+	reg		[size*width1-1:0]	sub_data_reg [3:0], sub_data_next [3:0];
+	wire	[size*width1-1:0]	sub_data_wire;
+
+	reg		[size*width-1:0]	inp_data_reg [2:0], inp_data_next [2:0];
+	wire	[size*width-1:0]	inp_data_wire [3:0];
+
+	reg		[size*8-1:0]		amp_data_reg, amp_data_next;
+	wire	[size*8-1:0]		amp_data_wire [2:0];
+
+	reg		[size*16-1:0]		tau_data_reg, tau_data_next;
+	wire	[size*16-1:0]		tau_data_wire [2:0];
 
 	integer i;
@@ -37,21 +54,33 @@
 		for (j = 0; j < size; j = j + 1)
 		begin : INT_DATA
-			assign int_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+0)*width+width-1:(3*j+0)*width]};
-			assign int_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+1)*width+width-1:(3*j+1)*width]};
-			assign int_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[(3*j+2)*width+width-1:(3*j+2)*width]};
-			assign mul_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+0)*16+16-1:(3*j+0)*16]};
-			assign mul_data_wire[1][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+1)*16+16-1:(3*j+1)*16]};
-			assign mul_data_wire[2][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+2)*16+16-1:(3*j+2)*16]};
-			assign mul_data_wire[3][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+3)*16+16-1:(3*j+3)*16]};
-			assign mul_data_wire[4][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+4)*16+16-1:(3*j+4)*16]};
-			assign mul_data_wire[5][j*widthr+widthr-1:j*widthr] = {{(widthr-16){1'b0}}, mul_data[(3*j+5)*16+16-1:(3*j+5)*16]};
+			assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
+			assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
+			assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
+			assign amp_data_wire[0][j*8+8-1:j*8] = amp_data[(3*j+0)*8+8-1:(3*j+0)*8];
+			assign amp_data_wire[1][j*8+8-1:j*8] = amp_data[(3*j+1)*8+8-1:(3*j+1)*8];
+			assign amp_data_wire[2][j*8+8-1:j*8] = amp_data[(3*j+2)*8+8-1:(3*j+2)*8];
+			assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16];
+			assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16];
+			assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16];
                                                                                          
+			lpm_mux #(
+				.lpm_size(3),
+				.lpm_type("LPM_MUX"),
+				.lpm_width(8),
+				.lpm_widths(2)) mux_unit_1 (
+				.sel(int_chan_next),
+				.data({
+					2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
+					2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
+					2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
+				.result(int_addr_wire));
+
 			lpm_add_sub	#(
-				.lpm_direction("ADD"),
+				.lpm_direction("SUB"),
 				.lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
 				.lpm_representation("UNSIGNED"),
 				.lpm_type("LPM_ADD_SUB"),
 				.lpm_width(6)) add_unit_1 (
-				.dataa(int_addr_reg[5:0]),
+				.dataa(del_addr_reg),
 				.datab(int_addr_wire[5:0]),
 				.result(del_addr_wire));
@@ -62,8 +91,8 @@
 				.lpm_representation("SIGNED"),
 				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) sub_unit_1 (
-				.dataa(acc_data_reg[0][j*widthr+widthr-1:j*widthr]),
-				.datab(int_data_wire[3][j*widthr+widthr-1:j*widthr]),
-				.result(int_data_wire[4][j*widthr+widthr-1:j*widthr]));
+				.lpm_width(width1)) sub_unit_1 (
+				.dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
+				.datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
+				.result(sub_data_wire[j*width1+width1-1:j*width1]));
 
 			lpm_add_sub	#(
@@ -72,8 +101,9 @@
 				.lpm_representation("SIGNED"),
 				.lpm_type("LPM_ADD_SUB"),
-				.lpm_width(widthr)) acc_unit_1 (
-				.dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
-				.datab(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
-				.result(int_data_wire[5][j*widthr+widthr-1:j*widthr]));
+				.lpm_width(width2)) acc_unit_1 (
+				.dataa({sub_data_reg[0][j*width1+width1-1], {(width2-width1){1'b0}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
+//				.dataa({width2{1'b0}}),
+				.datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
+				.result(acc_data_wire[j*width2+width2-1:j*width2]));
 
 			lpm_mult #(
@@ -82,28 +112,26 @@
 				.lpm_type("LPM_MULT"),
 				.lpm_pipeline(3),
-				.lpm_widtha(18),
-				.lpm_widthb(18),
-				.lpm_widthp(36)) mult_unit_1 (
+				.lpm_widtha(width1),
+				.lpm_widthb(17),
+				.lpm_widthp(widthr)) mult_unit_1 (
 				.clock(clock),
 				.clken(int_wren_reg),
-//				.dataa(int_data_wire[4][j*widthr+widthr-1:j*widthr]),
-				.dataa(acc_data_reg[1][j*widthr+widthr-1:j*widthr]),
-				.datab(acc_data_reg[5][j*widthr+widthr-1:j*widthr]),
-				.result(int_data_wire[6][j*widthr+widthr-1:j*widthr]));
+				.dataa(sub_data_reg[0][j*width1+width1-1:j*width1]),
+				.datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
+				.result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
 
 			lpm_mult #(
 				.lpm_hint("MAXIMIZE_SPEED=9"),
-				.lpm_representation("SIGNED"),
+				.lpm_representation("UNSIGNED"),
 				.lpm_type("LPM_MULT"),
 				.lpm_pipeline(3),
-				.lpm_widtha(widthr),
-				.lpm_widthb(widthr),
+				.lpm_widtha(width2),
+				.lpm_widthb(8),
 				.lpm_widthp(widthr)) mult_unit_2 (
 				.clock(clock),
 				.clken(int_wren_reg),
-//				.dataa(int_data_wire[5][j*widthr+widthr-1:j*widthr]),
-				.dataa(acc_data_reg[2][j*widthr+widthr-1:j*widthr]),
-				.datab(acc_data_reg[6][j*widthr+widthr-1:j*widthr]),
-				.result(int_data_wire[7][j*widthr+widthr-1:j*widthr]));
+				.dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
+				.datab(amp_data_reg[j*8+8-1:j*8]),
+				.result(mul_data_wire[1][j*widthr+widthr-1:j*widthr]));
 
 			lpm_add_sub	#(
@@ -113,7 +141,7 @@
 				.lpm_type("LPM_ADD_SUB"),
 				.lpm_width(widthr)) add_unit_2 (
-				.dataa(acc_data_reg[3][j*widthr+widthr-1:j*widthr]),
-				.datab(acc_data_reg[4][j*widthr+widthr-1:j*widthr]),
-				.result(int_data_wire[8][j*widthr+widthr-1:j*widthr]));
+				.dataa(mul_data_reg[0][j*widthr+widthr-1:j*widthr]),
+				.datab(mul_data_reg[1][j*widthr+widthr-1:j*widthr]),
+				.result(out_data_wire[j*widthr+widthr-1:j*widthr]));
 
 		end
@@ -138,6 +166,6 @@
 		.widthad_a(8),
 		.widthad_b(8),
-		.width_a(size*widthr),
-		.width_b(size*widthr),
+		.width_a(size*width),
+		.width_b(size*width),
 		.width_byteena_a(1)) ram_unit_1 (
 		.wren_a(int_wren_reg),
@@ -145,6 +173,6 @@
 		.address_a(int_addr_reg),
 		.address_b({int_addr_wire[7:6], del_addr_wire}),
-		.data_a(acc_data_reg[0]),
-		.q_b(int_data_wire[3]),
+		.data_a(inp_data_reg[0]),
+		.q_b(inp_data_wire[3]),
 		.aclr0(1'b0),
 		.aclr1(1'b0),
@@ -158,5 +186,5 @@
 		.clocken2(1'b1),
 		.clocken3(1'b1),
-		.data_b({widthr{1'b1}}),
+		.data_b({(size*width){1'b1}}),
 		.eccstatus(),
 		.q_a(),
@@ -164,16 +192,4 @@
 		.rden_b(1'b1),
 		.wren_b(1'b0));
-
-	lpm_mux #(
-		.lpm_size(3),
-		.lpm_type("LPM_MUX"),
-		.lpm_width(8),
-		.lpm_widths(2)) mux_unit_1 (
-		.sel(int_chan_next),
-		.data({
-			2'd2, 1'b0, del_data[14:10],
-			2'd1, 1'b0, del_data[9:5],
-			2'd0, 1'b0, del_data[4:0]}),
-		.result(int_addr_wire));
 
 	always @(posedge clock)
@@ -184,12 +200,21 @@
 			int_chan_reg <= 2'd0;
 			int_case_reg <= 3'd0;
+			del_addr_reg <= 6'd0;
 			int_addr_reg <= 8'd0;
-			for(i = 0; i <= 6; i = i + 1)
-			begin
-				acc_data_reg[i] <= {(size*widthr){1'b0}};
-			end
-			for(i = 0; i <= 17; i = i + 1)
-			begin
-				int_data_reg[i] <= {(size*widthr){1'b0}};
+			amp_data_reg <= 8'd0;
+			tau_data_reg <= 16'd0;
+			for(i = 0; i <= 2; i = i + 1)
+			begin
+				inp_data_reg[i] <= {(size*width){1'b0}};
+				out_data_reg[i] <= {(size*widthr){1'b0}};
+			end
+			for(i = 0; i <= 3; i = i + 1)
+			begin
+				sub_data_reg[i] <= {(size*width1){1'b0}};
+				acc_data_reg[i] <= {(size*width2){1'b0}};
+			end
+			for(i = 0; i <= 7; i = i + 1)
+			begin
+				mul_data_reg[i] <= {(size*widthr){1'b0}};
 			end
 		end
@@ -199,12 +224,21 @@
 			int_chan_reg <= int_chan_next;
 			int_case_reg <= int_case_next;
+			del_addr_reg <= del_addr_next;
 			int_addr_reg <= int_addr_next;
-			for(i = 0; i <= 6; i = i + 1)
-			begin
+			amp_data_reg <= amp_data_next;
+			tau_data_reg <= tau_data_next;
+			for(i = 0; i <= 2; i = i + 1)
+			begin
+				inp_data_reg[i] <= inp_data_next[i];
+				out_data_reg[i] <= out_data_next[i];
+			end                  
+			for(i = 0; i <= 3; i = i + 1)
+			begin
+				sub_data_reg[i] <= sub_data_next[i];
 				acc_data_reg[i] <= acc_data_next[i];
-			end
-			for(i = 0; i <= 17; i = i + 1)
-			begin
-				int_data_reg[i] <= int_data_next[i];
+			end                  
+			for(i = 0; i <= 7; i = i + 1)
+			begin
+				mul_data_reg[i] <= mul_data_next[i];
 			end
 		end             
@@ -216,12 +250,21 @@
 		int_chan_next = int_chan_reg;
 		int_case_next = int_case_reg;
+		del_addr_next = del_addr_reg;
 		int_addr_next = int_addr_reg;
-		for(i = 0; i <= 6; i = i + 1)
+		amp_data_next = amp_data_reg;
+		tau_data_next = tau_data_reg;
+		for(i = 0; i <= 2; i = i + 1)
 		begin
+			inp_data_next[i] = inp_data_reg[i];
+			out_data_next[i] = out_data_reg[i];
+		end                  
+		for(i = 0; i <= 3; i = i + 1)
+		begin
+			sub_data_next[i] = sub_data_reg[i];
 			acc_data_next[i] = acc_data_reg[i];
-		end
-		for(i = 0; i <= 17; i = i + 1)
+		end                  
+		for(i = 0; i <= 7; i = i + 1)
 		begin
-			int_data_next[i] = int_data_reg[i];
+			mul_data_next[i] = mul_data_reg[i];
 		end
 
@@ -231,13 +274,23 @@
 				// write zeros
 				int_wren_next = 1'b1;
+				del_addr_next = 6'd0;
 				int_addr_next = 8'd0;
-				for(i = 0; i <= 6; i = i + 1)
+				amp_data_next = 8'd0;
+				tau_data_next = 16'd0;
+				for(i = 0; i <= 2; i = i + 1)
 				begin
-					acc_data_next[i] = {(size*widthr){1'b0}};
+					inp_data_next[i] = {(size*width){1'b0}};
+					out_data_next[i] = {(size*widthr){1'b0}};
+				end                  
+				for(i = 0; i <= 3; i = i + 1)
+				begin
+					sub_data_next[i] = {(size*width1){1'b0}};
+					acc_data_next[i] = {(size*width2){1'b0}};
+				end                  
+				for(i = 0; i <= 7; i = i + 1)
+				begin
+					mul_data_next[i] = {(size*widthr){1'b0}};
 				end
-				for(i = 0; i <= 17; i = i + 1)
-				begin
-					int_data_next[i] = {(size*widthr){1'b0}};
-				end
+
 				int_case_next = 3'd1;
 			end	
@@ -265,15 +318,18 @@
 
 					// register input data for 2nd and 3rd sums
-					int_data_next[0] = int_data_wire[1];
-					int_data_next[1] = int_data_wire[2];
+					inp_data_next[1] = inp_data_wire[1];
+					inp_data_next[2] = inp_data_wire[2];
 
 					// prepare registers for 1st sum					
-					acc_data_next[0] = int_data_wire[0];
-					acc_data_next[1] = int_data_reg[2];
-					acc_data_next[2] = int_data_reg[3];
-					acc_data_next[3] = int_data_reg[4];
-					acc_data_next[4] = int_data_reg[5];
-					acc_data_next[5] = mul_data_wire[0];
-					acc_data_next[6] = mul_data_wire[1];
+					inp_data_next[0] = inp_data_wire[0];
+
+					sub_data_next[0] = sub_data_reg[1];
+					acc_data_next[0] = acc_data_reg[1];
+
+					mul_data_next[0] = mul_data_reg[2];
+					mul_data_next[1] = mul_data_reg[3];
+					
+					tau_data_next = tau_data_wire[0];
+					amp_data_next = amp_data_wire[0];
 					
 					int_case_next = 3'd3;
@@ -289,18 +345,21 @@
 
 				// prepare registers for 2nd sum
-				acc_data_next[0] = int_data_reg[0];
-				acc_data_next[1] = int_data_reg[7];
-				acc_data_next[2] = int_data_reg[8];
-				acc_data_next[3] = int_data_reg[9];
-				acc_data_next[4] = int_data_reg[10];
-				acc_data_next[5] = mul_data_wire[2];
-				acc_data_next[6] = mul_data_wire[3];
+				inp_data_next[0] = inp_data_reg[1];
+					
+				sub_data_next[0] = sub_data_reg[2];
+				acc_data_next[0] = acc_data_reg[2];
+				
+				mul_data_next[0] = mul_data_reg[4];
+				mul_data_next[1] = mul_data_reg[5];
+
+				tau_data_next = tau_data_wire[1];
+				amp_data_next = amp_data_wire[1];
 
 				// register 1st sum
-				int_data_next[2] = int_data_wire[4];
-				int_data_next[3] = int_data_wire[5];
-				int_data_next[4] = int_data_wire[6];
-				int_data_next[5] = int_data_wire[7];
-				int_data_next[6] = int_data_wire[8];
+				sub_data_next[1] = sub_data_wire;
+				acc_data_next[1] = acc_data_wire;
+				mul_data_next[2] = mul_data_wire[0];
+				mul_data_next[3] = mul_data_wire[1];
+				out_data_next[0] = out_data_wire;
 
 				int_case_next = 3'd4;
@@ -311,19 +370,24 @@
 
 				// prepare registers for 3rd sum	
-				acc_data_next[0] = int_data_reg[1];
-				acc_data_next[1] = int_data_reg[12];
-				acc_data_next[2] = int_data_reg[13];
-				acc_data_next[3] = int_data_reg[14];
-				acc_data_next[4] = int_data_reg[15];
-				acc_data_next[5] = mul_data_wire[4];
-				acc_data_next[6] = mul_data_wire[5];
+				inp_data_next[0] = inp_data_reg[2];
+
+				sub_data_next[0] = sub_data_reg[3];
+				acc_data_next[0] = acc_data_reg[3];
+
+				mul_data_next[0] = mul_data_reg[6];
+				mul_data_next[1] = mul_data_reg[7];
+
+				tau_data_next = tau_data_wire[2];
+				amp_data_next = amp_data_wire[2];
 				
 				// register 2nd sum
-				int_data_next[7] = int_data_wire[4];
-				int_data_next[8] = int_data_wire[5];
-				int_data_next[9] = int_data_wire[6];
-				int_data_next[10] = int_data_wire[7];
-				int_data_next[11] = int_data_wire[8];
+				sub_data_next[2] = sub_data_wire;
+				acc_data_next[2] = acc_data_wire;
+				mul_data_next[4] = mul_data_wire[0];
+				mul_data_next[5] = mul_data_wire[1];
+				out_data_next[1] = out_data_wire;
 				
+				del_addr_next = del_addr_reg + 6'd1;
+
 				int_case_next = 3'd5;
 			end
@@ -336,11 +400,11 @@
 
 				// register 3rd sum
-				int_data_next[12] = int_data_wire[4];
-				int_data_next[13] = int_data_wire[5];
-				int_data_next[14] = int_data_wire[6];
-				int_data_next[15] = int_data_wire[7];
-				int_data_next[16] = int_data_wire[8];
+				sub_data_next[3] = sub_data_wire;
+				acc_data_next[3] = acc_data_wire;
+				mul_data_next[6] = mul_data_wire[0];
+				mul_data_next[7] = mul_data_wire[1];
+				out_data_next[2] = out_data_wire;
                                              
-				int_addr_next[5:0] = int_addr_reg[5:0] + 6'd1;
+				int_addr_next[5:0] = del_addr_reg;
 
 				int_case_next = 3'd2;
@@ -353,5 +417,7 @@
 	end
 
-	assign out_data = {int_data_next[16], int_data_next[11], int_data_next[6]};
+	assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]};
+	assign acc_data = {acc_data_reg[3], acc_data_reg[2], acc_data_reg[1]};
+//	assign acc_data = {17'd0, del_addr_wire, 17'd0, del_addr_wire, 17'd0, del_addr_wire};
 
 endmodule