Index: /sandbox/MultiChannelUSB/Paella.qsf =================================================================== --- /sandbox/MultiChannelUSB/Paella.qsf (revision 106) +++ /sandbox/MultiChannelUSB/Paella.qsf (revision 107) @@ -42,5 +42,5 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 9.0 +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 @@ -49,13 +49,20 @@ set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF set_global_assignment -name MISC_FILE Paella.dpf +set_global_assignment -name MISC_FILE "C:/altera/project_12/Paella.dpf" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name VERILOG_FILE cic_pipeline.v +set_global_assignment -name VERILOG_FILE cic_filter.v set_global_assignment -name VERILOG_FILE Paella.v -set_global_assignment -name VERILOG_FILE adc_fifo.v set_global_assignment -name VERILOG_FILE adc_lvds.v -set_global_assignment -name VERILOG_FILE adc_para.v -set_global_assignment -name VERILOG_FILE adc_pll.v +set_global_assignment -name VERILOG_FILE sys_pll.v set_global_assignment -name VERILOG_FILE control.v +set_global_assignment -name VERILOG_FILE uwt_bior31.v set_global_assignment -name VERILOG_FILE analyser.v +set_global_assignment -name VERILOG_FILE amplitude.v +set_global_assignment -name VERILOG_FILE delay.v +set_global_assignment -name VERILOG_FILE coincidence.v set_global_assignment -name VERILOG_FILE counter.v -set_global_assignment -name VERILOG_FILE histogram.v +set_global_assignment -name VERILOG_FILE histogram32.v +set_global_assignment -name VERILOG_FILE histogram16.v set_global_assignment -name VERILOG_FILE trigger.v set_global_assignment -name VERILOG_FILE oscilloscope.v @@ -63,8 +70,6 @@ set_global_assignment -name VERILOG_FILE usb_fifo.v set_global_assignment -name VERILOG_FILE i2c_fifo.v -set_global_assignment -name VERILOG_FILE uwt_bior31.v set_global_assignment -name VERILOG_FILE test.v -set_global_assignment -name VERILOG_FILE test_pll.v -set_global_assignment -name VERILOG_FILE sys_pll.v +set_global_assignment -name MIF_FILE test.mif set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF set_global_assignment -name ENABLE_CLOCK_LATENCY ON Index: /sandbox/MultiChannelUSB/Paella.v =================================================================== --- /sandbox/MultiChannelUSB/Paella.v (revision 106) +++ /sandbox/MultiChannelUSB/Paella.v (revision 107) @@ -83,5 +83,5 @@ usb_fifo usb_unit ( - .usb_clk(USB_IFCLK), + .usb_clock(USB_IFCLK), .usb_data(USB_PB), .usb_full(~USB_FLAGB), @@ -93,5 +93,5 @@ .usb_addr(usb_addr), - .clk(sys_clock), + .clock(sys_clock), .tx_full(usb_tx_full), @@ -104,4 +104,14 @@ ); + wire [11:0] osc_mux_data [4:0]; + + wire [11:0] trg_mux_data; + wire trg_flag; + + wire [2:0] coi_data; + wire coi_flag; + + wire [7*12-1:0] int_mux_data [N-1:0]; + wire ana_dead [N-1:0]; wire ana_good [N-1:0]; @@ -109,30 +119,25 @@ wire [11:0] ana_base [N-1:0]; + wire amp_good [N-1:0]; + wire [11:0] amp_data [N-1:0]; + wire cnt_good [N-1:0]; - - wire [11:0] osc_mux_data [N-1:0]; - - wire [11:0] trg_mux_data; - wire trg_flag; - - wire [83:0] int_mux_data [N-1:0]; + wire [15:0] cnt_bits_wire; wire sys_clock, sys_frame; - wire [11:0] adc_data [N-1:0]; - wire [11:0] int_data [N-1:0]; + wire [11:0] adc_data [N-1:0]; wire [11:0] sys_data [N-1:0]; + wire [11:0] tst_data; + wire [11:0] cmp_data; - wire [11:0] nowhere; + wire [11:0] del_data; wire [31:0] uwt_d1 [N-1:0]; wire [31:0] uwt_a1 [N-1:0]; - wire [31:0] uwt_peak1 [N-1:0]; wire [31:0] uwt_d2 [N-1:0]; wire [31:0] uwt_a2 [N-1:0]; - wire [31:0] uwt_peak2 [N-1:0]; wire [31:0] uwt_d3 [N-1:0]; wire [31:0] uwt_a3 [N-1:0]; - wire [31:0] uwt_peak3 [N-1:0]; wire [1:0] uwt_flag1 [N-1:0]; @@ -140,22 +145,11 @@ wire [1:0] uwt_flag3 [N-1:0]; + wire [11:0] cic_mux_data; + wire [13:0] cic_lfsr; + wire [24:0] cic_data1 [N-1:0]; + wire [24:0] cic_data2 [N-1:0]; + wire [24:0] cic_data3 [N-1:0]; + wire i2c_reset; - -/* - adc_para adc_para_unit ( - .lvds_dco(ADC_DCO), - .lvds_fco(ADC_FCO), - .para_good(CON_CCLK[0]), - .para_data(CON_C[11:0]), - .adc_data(adc_data[2])); -*/ - - wire adc_pll_clk; - -/* - adc_pll adc_pll_unit( - .inclk0(ADC_FCO), - .c0(adc_pll_clk)); -*/ sys_pll sys_pll_unit( @@ -164,44 +158,37 @@ test test_unit( - .clk(ADC_FCO), - .data(adc_data[2])); -// .data(nowhere)); + .clock(ADC_FCO), + .data(tst_data)); adc_lvds #( .size(3), .width(12)) adc_lvds_unit ( + .clock(sys_clock), .lvds_dco(ADC_DCO), -// .lvds_dco(adc_pll_clk), .lvds_fco(ADC_FCO), - .lvds_d(ADC_D[2:0]), -// .adc_data({ adc_data[2], - .adc_data({ nowhere, - adc_data[1], - adc_data[0] })); - -/* - assign cmp_data = CON_B[11:0]; - assign sys_clock = ADC_DCO; - assign sys_frame = ADC_FCO; -*/ + .lvds_d(ADC_D), + .test(tst_data), + .trig({CON_B[9:0], TRG[1:0]}), + .adc_frame(sys_frame), + .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]})); wire [15:0] cfg_bits [31:0]; wire [511:0] int_cfg_bits; - wire [31:0] cfg_mux_selector; + wire [39:0] cfg_mux_selector; wire cfg_reset; - wire [8:0] bus_ssel; + wire [11:0] bus_ssel; wire bus_wren; wire [31:0] bus_addr; wire [15:0] bus_mosi; - wire [15:0] bus_miso [7:0]; - wire [8:0] bus_busy; + wire [15:0] bus_miso [10:0]; + wire [11:0] bus_busy; wire [15:0] mrg_bus_miso; wire mrg_bus_busy; - wire [127:0] int_bus_miso; + wire [11*16-1:0] int_bus_miso; genvar j; @@ -229,31 +216,35 @@ begin : MUX_DATA assign int_mux_data[j] = { - {ana_good[j], 11'd0}, - ana_data[j], - ana_base[j], - uwt_a3[j][20:9], - uwt_a2[j][17:6], - uwt_a1[j][14:3], + {4'd0, uwt_flag3[j][1], 7'd0}, + {4'd0, uwt_flag3[j][0], 7'd0}, + {12'd0}, +// {4'd0, amp_good[j], 7'd0}, + cic_data1[j][14:3], + cic_data2[j][18:7], + cic_data3[j][22:11], +// {8'd0, cic_lfsr[3:0]}, +// {8'd0, cic_lfsr[5:2]}, +// uwt_a3[j][20:9], sys_data[j]}; end endgenerate - assign cfg_mux_selector = {cfg_bits[3], cfg_bits[2]}; + assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]}; lpm_mux #( - .lpm_size(21), + .lpm_size(7*3), .lpm_type("LPM_MUX"), .lpm_width(12), .lpm_widths(5)) trg_mux_unit ( - .sel(cfg_mux_selector[28:24]), + .sel(cfg_bits[4][12:8]), .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), .result(trg_mux_data)); generate - for (j = 0; j < 3; j = j + 1) + for (j = 0; j < 5; j = j + 1) begin : OSC_CHAIN lpm_mux #( - .lpm_size(21), + .lpm_size(7*3), .lpm_type("LPM_MUX"), .lpm_width(12), @@ -278,7 +269,7 @@ .frame(sys_frame), .reset(cfg_bits[0][1]), - .cfg_data(cfg_bits[4][0]), + .cfg_data(cfg_bits[5][12]), .trg_flag(trg_flag), - .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), + .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), .ram_wren(RAM_WE), .ram_addr(RAM_ADDR), @@ -291,18 +282,18 @@ .bus_busy(bus_busy[1])); - - adc_fifo #(.W(48)) adc_fifo_unit ( - .adc_clock(ADC_FCO), - .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}), - .sys_clock(sys_clock), - .sys_frame(sys_frame), - .sys_data({cmp_data, int_data[2], int_data[1], int_data[0]})); - - + cic1 #(.size(3), .width(12)) cic3_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(1'b0), + .inp_data({sys_data[2], sys_data[1], sys_data[0]}), + .out_data2({cic_data2[2], cic_data2[1], cic_data2[0]}), + .out_data3({cic_data3[2], cic_data3[1], cic_data3[0]}), + .out_data({cic_data1[2], cic_data1[1], cic_data1[0]})); + generate for (j = 0; j < 3; j = j + 1) begin : MCA_CHAIN - assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]); + assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); uwt_bior31 #(.L(1)) uwt_1_unit ( @@ -313,5 +304,4 @@ .d(uwt_d1[j]), .a(uwt_a1[j]), - .peak(uwt_peak1[j]), .flag(uwt_flag1[j])); @@ -323,5 +313,4 @@ .d(uwt_d2[j]), .a(uwt_a2[j]), - .peak(uwt_peak2[j]), .flag(uwt_flag2[j])); @@ -333,5 +322,4 @@ .d(uwt_d3[j]), .a(uwt_a3[j]), - .peak(uwt_peak3[j]), .flag(uwt_flag3[j])); @@ -341,6 +329,6 @@ .reset(cfg_bits[0][2+j]), .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), - .uwt_flag(uwt_flag3[j]), - .uwt_data(uwt_peak3[j]), + .uwt_flag(uwt_flag2[j]), + .uwt_data(uwt_a2[j][17:6]), .ana_dead(ana_dead[j]), .ana_good(ana_good[j]), @@ -348,32 +336,49 @@ .ana_base(ana_base[j])); - histogram histogram_unit ( + amplitude amplitude_unit ( .clock(sys_clock), .frame(sys_frame), - .reset(cfg_bits[0][5+j]), - .hst_good((ana_good[j]) & (cnt_good[j])), - .hst_data(ana_data[j]), - .bus_ssel(bus_ssel[2+j]), - .bus_wren(bus_wren), - .bus_addr(bus_addr[12:0]), - .bus_mosi(bus_mosi), - .bus_miso(bus_miso[2+j]), - .bus_busy(bus_busy[2+j])); - - counter counter_unit ( - .clock(sys_clock), - .frame((sys_frame) & (~ana_dead[j])), - .reset(cfg_bits[0][8+j]), - .cfg_data(cfg_bits[12+j]), - .bus_ssel(bus_ssel[5+j]), - .bus_wren(bus_wren), - .bus_addr(bus_addr[1:0]), - .bus_mosi(bus_mosi), - .bus_miso(bus_miso[5+j]), - .bus_busy(bus_busy[5+j]), - .cnt_good(cnt_good[j])); - + .reset(cfg_bits[0][2+j]), + .cfg_data(cfg_bits[12][11:0]), +// .cfg_data(10'd5), + .uwt_flag(uwt_flag3[j]), + .uwt_data(uwt_a3[j][20:9]), + .amp_good(amp_good[j]), + .amp_data(amp_data[j])); end endgenerate + + histogram32 histogram32_unit ( + .clock(sys_clock), + .frame(sys_frame), + .reset(cfg_bits[0][5]), + .hst_good((ana_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])), + .hst_data(ana_data[0]), +/* + .hst_good((amp_good[j]) & (cnt_good[j]) & (cfg_bits[13][1])), + .hst_data(amp_data[j]), +*/ + .bus_ssel(bus_ssel[2]), + .bus_wren(bus_wren), + .bus_addr(bus_addr[12:0]), + .bus_mosi(bus_mosi), + .bus_miso(bus_miso[2]), + .bus_busy(bus_busy[2])); + + counter hst_counter_unit ( + .clock(sys_clock), + .frame((sys_frame) & (~ana_dead[0])), +// .frame(sys_frame), + .reset(cfg_bits[0][8]), + .setup(cfg_bits[13][0]), + .count(cfg_bits[13][1]), + .bus_ssel(bus_ssel[5]), + .bus_wren(bus_wren), + .bus_addr(bus_addr[1:0]), + .bus_mosi(bus_mosi), + .bus_miso(bus_miso[5]), + .bus_busy(bus_busy[5]), + .cnt_good(cnt_good[0])); + i2c_fifo i2c_unit( @@ -390,11 +395,11 @@ .i2c_scl(I2C_SDA), - .bus_ssel(bus_ssel[8]), - .bus_wren(bus_wren), - .bus_mosi(bus_mosi), - .bus_busy(bus_busy[8])); + .bus_ssel(bus_ssel[11]), + .bus_wren(bus_wren), + .bus_mosi(bus_mosi), + .bus_busy(bus_busy[11])); generate - for (j = 0; j < 8; j = j + 1) + for (j = 0; j < 11; j = j + 1) begin : BUS_OUTPUT assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; @@ -403,14 +408,14 @@ lpm_mux #( - .lpm_size(8), + .lpm_size(11), .lpm_type("LPM_MUX"), .lpm_width(16), - .lpm_widths(3)) bus_miso_mux_unit ( - .sel(bus_addr[30:28]), + .lpm_widths(4)) bus_miso_mux_unit ( + .sel(bus_addr[31:28]), .data(int_bus_miso), .result(mrg_bus_miso)); lpm_mux #( - .lpm_size(9), + .lpm_size(12), .lpm_type("LPM_MUX"), .lpm_width(1), @@ -420,23 +425,11 @@ .result(mrg_bus_busy)); -/* - lpm_or #( - .lpm_size(6), - .lpm_type("LPM_OR"), - .lpm_width(16)) bus_miso_or_unit ( - .data(int_bus_miso), - .result(mrg_bus_miso)); -*/ - lpm_decode #( - .lpm_decodes(9), + .lpm_decodes(12), .lpm_type("LPM_DECODE"), .lpm_width(4)) lpm_decode_unit ( .data(bus_addr[31:28]), - .eq(bus_ssel), - .aclr(), - .clken(), - .clock(), - .enable()); + .eq(bus_ssel)); + control control_unit ( Index: ndbox/MultiChannelUSB/adc_fifo.v =================================================================== --- /sandbox/MultiChannelUSB/adc_fifo.v (revision 106) +++ (revision ) @@ -1,73 +1,0 @@ -module adc_fifo - #( - parameter W = 48 // fifo width - ) - ( - input wire adc_clock, - input wire [W-1:0] adc_data, - - input wire sys_clock, - output wire sys_frame, - output wire [W-1:0] sys_data - ); - - wire [W-1:0] int_q; - reg [W-1:0] int_data; - - reg state, int_rdreq, int_frame; - wire int_wrfull, int_rdempty; - - dcfifo #( - .intended_device_family("Cyclone III"), - .lpm_numwords(16), - .lpm_showahead("ON"), - .lpm_type("dcfifo"), - .lpm_width(W), - .lpm_widthu(4), - .rdsync_delaypipe(4), - .wrsync_delaypipe(4), - .overflow_checking("ON"), - .underflow_checking("ON"), - .use_eab("ON"), - .write_aclr_synch("OFF")) fifo_unit ( - .aclr(1'b0), - .data(adc_data), - .rdclk(sys_clock), - .rdreq((~int_rdempty) & int_rdreq), - .wrclk(adc_clock), - .wrreq(~int_wrfull), - .q(int_q), - .rdempty(int_rdempty), - .wrfull(int_wrfull), - .rdfull(), - .rdusedw(), - .wrempty(), - .wrusedw()); - - always @(posedge sys_clock) - begin - case (state) - 1'b0: - begin - int_rdreq <= 1'b1; - int_frame <= 1'b0; - state <= 1'b1; - end - - 1'b1: - begin - if (~int_rdempty) - begin - int_data <= int_q; - int_rdreq <= 1'b0; - int_frame <= 1'b1; - state <= 1'b0; - end - end - endcase - end - - assign sys_frame = int_frame; - assign sys_data = int_data; - -endmodule Index: /sandbox/MultiChannelUSB/adc_lvds.v =================================================================== --- /sandbox/MultiChannelUSB/adc_lvds.v (revision 106) +++ /sandbox/MultiChannelUSB/adc_lvds.v (revision 107) @@ -5,70 +5,103 @@ ) ( + input wire clock, + input wire lvds_dco, input wire lvds_fco, input wire [size-1:0] lvds_d, - output wire [size*width-1:0] adc_data + input wire [11:0] test, + input wire [11:0] trig, + + output wire adc_frame, + output wire [size*width-1+12:0] adc_data + ); - wire [size-1:0] int_data_h, int_data_l; - reg [width-1:0] int_data_next [size-1:0]; -// reg [2*width:0] int_data_next [size-1:0]; - reg [width-1:0] int_data_reg [size-1:0]; -// reg [2*width:0] int_data_reg [size-1:0]; + reg state, int_rdreq, adc_frame_reg; + wire int_wrfull, int_rdempty; - reg [width-1:0] int_adc_data [size-1:0]; + reg [size-1:0] int_data_h, int_data_l; - integer i; + reg [size*width-1:0] int_data_reg; + wire [size*width-1:0] int_data_wire; + + wire [size*width-1+12:0] int_q_wire; + reg [size*width-1+12:0] adc_data_reg; + + genvar j; - altddio_in #( + generate + for (j = 0; j < size-1; j = j + 1) + begin : INT_DATA + assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_h[j], int_data_l[j]}; +// assign int_data_wire[j*width+width-1:j*width] = test; + end + endgenerate + assign int_data_wire[(size-1)*width+width-1:(size-1)*width] = test; + + dcfifo #( .intended_device_family("Cyclone III"), - .invert_input_clocks("ON"), -// .invert_input_clocks("OFF"), - .lpm_type("altddio_in"), - .width(size)) altddio_in_unit ( - .datain(lvds_d), - .inclock(lvds_dco), - .aclr(1'b0), - .dataout_h(int_data_h), - .dataout_l(int_data_l), - .aset(1'b0), - .inclocken(1'b1), - .sclr(1'b0), - .sset(1'b0)); + .lpm_numwords(16), + .lpm_showahead("ON"), + .lpm_type("dcfifo"), + .lpm_width(size*width+12), + .lpm_widthu(4), + .rdsync_delaypipe(4), + .wrsync_delaypipe(4), + .overflow_checking("ON"), + .underflow_checking("ON"), + .use_eab("ON")) fifo_unit ( + .data({trig, int_data_wire}), + .rdclk(clock), + .rdreq((~int_rdempty) & int_rdreq), + .wrclk(lvds_fco), + .wrreq(~int_wrfull), + .q(int_q_wire), + .rdempty(int_rdempty), + .wrfull(int_wrfull), + .aclr(), + .rdfull(), + .rdusedw(), + .wrempty(), + .wrusedw()); + + always @ (posedge clock) + begin + case (state) + 1'b0: + begin + int_rdreq <= 1'b1; + adc_frame_reg <= 1'b0; + state <= 1'b1; + end + + 1'b1: + begin + if (~int_rdempty) + begin + int_rdreq <= 1'b0; + adc_frame_reg <= 1'b1; + adc_data_reg <= int_q_wire; + state <= 1'b0; + end + end + endcase + end + + always @ (negedge lvds_dco) + begin + int_data_l <= lvds_d; + end always @ (posedge lvds_dco) begin - for (i = 0; i < size; i = i + 1) - begin - int_data_reg[i] <= int_data_next[i]; - end + int_data_h <= lvds_d; + int_data_reg <= int_data_wire; end - always @ (posedge lvds_fco) - begin - for (i = 0; i < size; i = i + 1) - begin - int_adc_data[i] <= int_data_next[i]; -// int_data_next[i] = {int_data_reg[i][2*width-2:0], int_data_l[i], int_data_h[i]}; - end - end - - always @* - begin - for (i = 0; i < size; i = i + 1) - begin - int_data_next[i] = {int_data_reg[i][width-3:0], int_data_l[i], int_data_h[i]}; -// int_data_next[i] = {int_data_reg[i][2*width-2:0], int_data_l[i], int_data_h[i]}; - end - end - - generate - for (j = 0; j < size; j = j + 1) - begin : ADC_LVDS_OUTPUT - assign adc_data[j*width+width-1:j*width] = int_adc_data[j]; - end - endgenerate + assign adc_frame = adc_frame_reg; + assign adc_data = adc_data_reg; endmodule Index: ndbox/MultiChannelUSB/adc_para.v =================================================================== --- /sandbox/MultiChannelUSB/adc_para.v (revision 106) +++ (revision ) @@ -1,31 +1,0 @@ -module adc_para - ( - input wire lvds_dco, - input wire lvds_fco, - input wire para_data_ready, - input wire [11:0] para_data, - - output wire [11:0] adc_data - ); - - reg [1:0] int_data_ready; - reg [11:0] int_data, int_adc_data; - - always @ (posedge lvds_dco) - begin - int_data_ready[1] <= int_data_ready[0]; - int_data_ready[0] <= para_data_ready; - if ((int_data_ready[0]) & (~int_data_ready[1])) - begin - int_data <= para_data; - end - end - - always @ (posedge lvds_fco) - begin - int_adc_data <= int_data; - end - - assign adc_data = int_adc_data; - -endmodule Index: ndbox/MultiChannelUSB/adc_pll.v =================================================================== --- /sandbox/MultiChannelUSB/adc_pll.v (revision 106) +++ (revision ) @@ -1,146 +1,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: adc_pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module adc_pll ( - inclk0, - c0); - - input inclk0; - output c0; - - wire [4:0] sub_wire0; - wire [0:0] sub_wire4 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire sub_wire2 = inclk0; - wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; - - altpll altpll_component ( - .inclk (sub_wire3), - .clk (sub_wire0), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .locked (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 1, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 6, - altpll_component.clk0_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 50000, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=adc_pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_UNUSED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_UNUSED", - altpll_component.port_clk2 = "PORT_UNUSED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.width_clock = 5; - - -endmodule Index: /sandbox/MultiChannelUSB/amplitude.v =================================================================== --- /sandbox/MultiChannelUSB/amplitude.v (revision 107) +++ /sandbox/MultiChannelUSB/amplitude.v (revision 107) @@ -0,0 +1,77 @@ +module amplitude + ( + input wire clock, frame, reset, + input wire [11:0] cfg_data, + input wire [1:0] uwt_flag, + input wire [11:0] uwt_data, + output wire amp_good, + output wire [11:0] amp_data + ); + + reg state_reg, state_next; + reg [11:0] minimum_reg, minimum_next; + reg amp_good_reg, amp_good_next; + reg [11:0] amp_data_reg, amp_data_next; + reg [11:0] uwt_data_reg, uwt_data_next; + + always @(posedge clock) + begin + if (reset) + begin + state_reg <= 1'b0; + minimum_reg <= 12'd0; + amp_good_reg <= 1'b0; + amp_data_reg <= 12'd0; + uwt_data_reg <= 12'd0; + end + else + begin + state_reg <= state_next; + minimum_reg <= minimum_next; + amp_good_reg <= amp_good_next; + amp_data_reg <= amp_data_next; + uwt_data_reg <= uwt_data_next; + end + end + + always @* + begin + state_next = state_reg; + minimum_next = minimum_reg; + amp_good_next = amp_good_reg; + amp_data_next = amp_data_reg; + uwt_data_next = uwt_data_reg; + + case (state_reg) + 0: + begin + if (frame) + begin + uwt_data_next = uwt_data; + amp_good_next = 1'b0; + // minimum + if (uwt_flag[0]) + begin + minimum_next = uwt_data_reg; + end + else if ((uwt_flag[1]) & (uwt_data > minimum_reg)) + begin + amp_data_next = uwt_data - minimum_reg; + state_next = 1'b1; + end + end + end + + 1: + begin + amp_good_next = (amp_data_reg >= cfg_data); + state_next = 1'b0; + end + + endcase + end + + assign amp_good = amp_good_reg; + assign amp_data = amp_data_reg; + +endmodule Index: /sandbox/MultiChannelUSB/analyser.v =================================================================== --- /sandbox/MultiChannelUSB/analyser.v (revision 106) +++ /sandbox/MultiChannelUSB/analyser.v (revision 107) @@ -33,5 +33,5 @@ state_reg <= 3'd0; counter_reg <= 5'd0; - sample_reg = 20'd0; + sample_reg <= 20'd0; dead_reg <= 1'b0; good_reg <= 1'b0; @@ -160,5 +160,5 @@ if (counter_max) begin - if (uwt_flag[0]) + if (uwt_flag[1]) begin counter_next = 5'd0; Index: /sandbox/MultiChannelUSB/cic_filter.v =================================================================== --- /sandbox/MultiChannelUSB/cic_filter.v (revision 107) +++ /sandbox/MultiChannelUSB/cic_filter.v (revision 107) @@ -0,0 +1,256 @@ +module cic1 + #( + parameter size = 3, // number of channels + parameter width = 12 // bit width of the input data (unsigned) + ) + ( + input wire clock, frame, reset, + input wire [size*width-1:0] inp_data, + output wire [size*widthr-1:0] out_data, + output wire [size*widthr-1:0] out_data2, + output wire [size*widthr-1:0] out_data3 + ); + + localparam widthr = width + 13; + + /* + 4-bit LFSR with additional bits to keep track of previous values + */ + reg [15:0] int_lfsr_reg, int_lfsr_next; + + reg int_wren_reg, int_wren_next; + reg [1:0] int_chan_reg, int_chan_next; + reg [2:0] int_case_reg, int_case_next; + reg [7:0] int_addr_reg, int_addr_next; + + wire [9:0] int_addr_wire; + + reg [size*widthr-1:0] acc_data_reg [2:0], acc_data_next [2:0]; + reg [size*widthr-1:0] int_data_reg [5:0], int_data_next [5:0]; + + wire [size*widthr-1:0] acc_data_wire [2:0], del_data_wire [1:0]; + + + integer i; + genvar j; + + generate + for (j = 0; j < size; j = j + 1) + begin : INT_DATA + assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]}; + + // -2*del_data_1 + del_data_2 + inp_data + result + parallel_add #( + .msw_subtract("YES"), + .representation("SIGNED"), + .result_alignment("LSB"), + .shift(0), + .size(4), + .width(widthr), + .widthr(widthr)) acc_unit_1 ( + .data({ + {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0}, + {del_data_wire[1][j*widthr+widthr-1:j*widthr]}, + {acc_data_reg[0][j*widthr+widthr-1:j*widthr]}, + {acc_data_reg[1][j*widthr+widthr-1:j*widthr]}}), + .result(acc_data_wire[1][j*widthr+widthr-1:j*widthr])); + + parallel_add #( + .msw_subtract("NO"), + .representation("SIGNED"), + .result_alignment("LSB"), + .shift(0), + .size(2), + .width(widthr), + .widthr(widthr)) acc_unit_2 ( + .data({ + {acc_data_reg[1][j*widthr+widthr-1:j*widthr]}, + {acc_data_reg[2][j*widthr+widthr-1:j*widthr]}}), + .result(acc_data_wire[2][j*widthr+widthr-1:j*widthr])); + + end + endgenerate + + cic_pipeline #( + .width(size*widthr)) cic_pipeline_unit ( + .clock(clock), + .data(acc_data_reg[0]), + .rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}), + .rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}), + .wraddress(int_addr_reg), + .wren(int_wren_reg), + .qa(del_data_wire[0]), + .qb(del_data_wire[1])); + + lpm_mux #( + .lpm_size(3), + .lpm_type("LPM_MUX"), + .lpm_width(10), + .lpm_widths(2)) mux_unit_1 ( + .sel(int_chan_next), + .data({ + 2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5], + 2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4], + 2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}), + .result(int_addr_wire)); + + always @(posedge clock) + begin + if (reset) + begin + int_wren_reg <= 1'b1; + int_chan_reg <= 2'd0; + int_case_reg <= 3'd0; + int_addr_reg <= 8'd0; + for(i = 0; i <= 2; i = i + 1) + begin + acc_data_reg[i] <= {(size*widthr){1'b0}}; + end + for(i = 0; i <= 5; i = i + 1) + begin + int_data_reg[i] <= {(size*widthr){1'b0}}; + end + int_lfsr_reg <= 16'd0; + end + else + begin + int_wren_reg <= int_wren_next; + int_chan_reg <= int_chan_next; + int_case_reg <= int_case_next; + int_addr_reg <= int_addr_next; + for(i = 0; i <= 2; i = i + 1) + begin + acc_data_reg[i] <= acc_data_next[i]; + end + for(i = 0; i <= 5; i = i + 1) + begin + int_data_reg[i] <= int_data_next[i]; + end + int_lfsr_reg <= int_lfsr_next; + end + end + + always @* + begin + int_wren_next = int_wren_reg; + int_chan_next = int_chan_reg; + int_case_next = int_case_reg; + int_addr_next = int_addr_reg; + for(i = 0; i <= 2; i = i + 1) + begin + acc_data_next[i] = acc_data_reg[i]; + end + for(i = 0; i <= 5; i = i + 1) + begin + int_data_next[i] = int_data_reg[i]; + end + int_lfsr_next = int_lfsr_reg; + + case (int_case_reg) + 0: + begin + // write zeros + int_wren_next = 1'b1; + int_addr_next = 8'd0; + for(i = 0; i <= 2; i = i + 1) + begin + acc_data_next[i] = {(size*widthr){1'b0}}; + end + for(i = 0; i <= 5; i = i + 1) + begin + int_data_next[i] = {(size*widthr){1'b0}}; + end + int_case_next = 3'd1; + end + 1: + begin + // write zeros + int_addr_next = int_addr_reg + 8'd1; + if (&int_addr_reg) + begin + int_wren_next = 1'b0; + int_chan_next = 2'd0; + int_lfsr_next = 16'h7650; + int_case_next = 3'd2; + end + end + 2: // frame + begin + if (frame) + begin + int_wren_next = 1'b1; + + int_addr_next = {4'd0, int_lfsr_reg[3:0]}; + + // set read addr for 2nd pipeline + int_chan_next = 2'd1; + + // prepare registers for 1st sum + acc_data_next[0] = acc_data_wire[0]; + acc_data_next[1] = int_data_reg[0]; + acc_data_next[2] = int_data_reg[1]; + + int_case_next = 3'd3; + end + + end + 3: // 1st sum + begin + int_addr_next = {4'd1, int_lfsr_reg[3:0]}; + + // set read addr for 3rd pipeline + int_chan_next = 2'd2; + + // prepare registers for 2nd sum + acc_data_next[0] = int_data_reg[1]; + acc_data_next[1] = int_data_reg[2]; + acc_data_next[2] = int_data_reg[3]; + + // register 1st sum + int_data_next[0] = acc_data_wire[1]; + int_data_next[1] = acc_data_wire[2]; + + int_case_next = 3'd4; + end + 4: // 2nd sum + begin + int_addr_next = {4'd2, int_lfsr_reg[3:0]}; + + // prepare registers for 3rd sum + acc_data_next[0] = int_data_reg[3]; + acc_data_next[1] = int_data_reg[4]; + acc_data_next[2] = int_data_reg[5]; + + // register 2nd sum + int_data_next[2] = acc_data_wire[1]; + int_data_next[3] = acc_data_wire[2]; + + int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]}; + + int_case_next = 3'd5; + end + 5: // 3rd sum + begin + int_wren_next = 1'b0; + + // set read addr for 1st pipeline + int_chan_next = 2'd0; + + // register 3rd sum + int_data_next[4] = acc_data_wire[1]; + int_data_next[5] = acc_data_wire[2]; + + int_case_next = 3'd2; + end + default: + begin + int_case_next = 3'd0; + end + endcase + end + + assign out_data = int_data_reg[1]; + assign out_data2 = int_data_reg[3]; + assign out_data3 = int_data_reg[5]; + +endmodule Index: /sandbox/MultiChannelUSB/cic_pipeline.v =================================================================== --- /sandbox/MultiChannelUSB/cic_pipeline.v (revision 107) +++ /sandbox/MultiChannelUSB/cic_pipeline.v (revision 107) @@ -0,0 +1,104 @@ +module cic_pipeline + #( + parameter width = 192 + ) + ( + input wire clock, + input wire [width-1:0] data, + input wire [7:0] rdaddress_a, + input wire [7:0] rdaddress_b, + input wire [7:0] wraddress, + input wire wren, + output wire [width-1:0] qa, + output wire [width-1:0] qb + ); + + altsyncram #( + .address_aclr_b("NONE"), + .address_reg_b("CLOCK0"), + .clock_enable_input_a("BYPASS"), + .clock_enable_input_b("BYPASS"), + .clock_enable_output_b("BYPASS"), + .intended_device_family("Cyclone III"), + .lpm_type("altsyncram"), + .numwords_a(256), + .numwords_b(256), + .operation_mode("DUAL_PORT"), + .outdata_aclr_b("NONE"), + .outdata_reg_b("CLOCK0"), + .power_up_uninitialized("FALSE"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .widthad_a(8), + .widthad_b(8), + .width_a(width), + .width_b(width), + .width_byteena_a(1)) ram_unit_a( + .wren_a(wren), + .clock0(clock), + .address_a(wraddress), + .address_b(rdaddress_a), + .data_a(data), + .q_b(qa), + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .data_b({width{1'b1}}), + .eccstatus(), + .q_a(), + .rden_a(1'b1), + .rden_b(1'b1), + .wren_b(1'b0)); + + altsyncram #( + .address_aclr_b("NONE"), + .address_reg_b("CLOCK0"), + .clock_enable_input_a("BYPASS"), + .clock_enable_input_b("BYPASS"), + .clock_enable_output_b("BYPASS"), + .intended_device_family("Cyclone III"), + .lpm_type("altsyncram"), + .numwords_a(256), + .numwords_b(256), + .operation_mode("DUAL_PORT"), + .outdata_aclr_b("NONE"), + .outdata_reg_b("CLOCK0"), + .power_up_uninitialized("FALSE"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .widthad_a(8), + .widthad_b(8), + .width_a(width), + .width_b(width), + .width_byteena_a(1)) ram_unit_b( + .wren_a(wren), + .clock0(clock), + .address_a(wraddress), + .address_b(rdaddress_b), + .data_a(data), + .q_b(qb), + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .data_b({width{1'b1}}), + .eccstatus(), + .q_a(), + .rden_a(1'b1), + .rden_b(1'b1), + .wren_b(1'b0)); + +endmodule Index: /sandbox/MultiChannelUSB/coincidence.v =================================================================== --- /sandbox/MultiChannelUSB/coincidence.v (revision 107) +++ /sandbox/MultiChannelUSB/coincidence.v (revision 107) @@ -0,0 +1,79 @@ +module coincidence + #( + parameter input_width = 4, + parameter window_size = 10, + parameter output_width = 3 + ) + ( + input wire clock, frame, reset, + input wire [output_width-1:0] cfg_data, + input wire [input_width-1:0] trg_data, + output wire [output_width-1:0] coi_data, + output wire coi_flag + ); + + reg [window_size-1:0] coi_pipe_reg [input_width-1:0]; + reg coi_flag_reg; + + wire [output_width-1:0] coi_data_wire; + wire [input_width-1:0] int_data_wire; + + integer i; + genvar j; + + always @(posedge clock) + begin + if (reset) + begin + coi_flag_reg <= 1'b0; + for(i = 0; i <= 3; i = i + 1) + begin + coi_pipe_reg[i] <= 0; + end + end + else if (frame) + begin + if (coi_data_wire >= cfg_data) + begin + coi_flag_reg <= 1'b1; + for(i = 0; i < input_width; i = i + 1) + begin + coi_pipe_reg[i] <= 0; + end + end + else + begin + coi_flag_reg <= 1'b0; + for(i = 0; i < input_width; i = i + 1) + begin + coi_pipe_reg[i] <= {coi_pipe_reg[i][window_size-2:0], trg_data[i]}; + end + end + end + end + + generate + for (j = 0; j < input_width; j = j + 1) + begin : INT_DATA + assign int_data_wire[j] = (|coi_pipe_reg[j]); + end + endgenerate + + parallel_add #( + .msw_subtract("NO"), + .representation("UNSIGNED"), + .result_alignment("LSB"), + .pipeline(1), + .shift(0), + .size(input_width), + .width(1), + .widthr(output_width)) parallel_add_unit ( + .clock(clock), + .data(int_data_wire), + .result(coi_data_wire)); + + + assign coi_data = coi_data_wire; + assign coi_flag = coi_flag_reg; + +endmodule Index: /sandbox/MultiChannelUSB/counter.v =================================================================== --- /sandbox/MultiChannelUSB/counter.v (revision 106) +++ /sandbox/MultiChannelUSB/counter.v (revision 107) @@ -1,7 +1,7 @@ module counter ( - input wire clock, frame, reset, + input wire clock, frame, - input wire [15:0] cfg_data, + input wire reset, setup, count, input wire bus_ssel, bus_wren, @@ -23,4 +23,6 @@ wire [63:0] reg_bits_wire; wire [63:0] cnt_bits_wire; + + reg int_load_reg; integer i; @@ -32,20 +34,10 @@ .lpm_type("LPM_COUNTER"), .lpm_width(64)) lpm_counter_component ( - .sload(cfg_data[0]), + .sload(int_load_reg | setup), .sclr(reset), .clock(clock), .data(reg_bits_wire), -// .cnt_en(frame & cfg_data[1]), - .cnt_en((frame) & (|cnt_bits_wire) & (cfg_data[1])), - .q(cnt_bits_wire), - .aclr(1'b0), - .aload(1'b0), - .aset(1'b0), - .cin(1'b1), - .clk_en(1'b1), - .cout(), - .eq(), - .sset(1'b0), - .updown(1'b1)); + .cnt_en((frame) & (count) & (|cnt_bits_wire)), + .q(cnt_bits_wire)); generate @@ -60,10 +52,5 @@ .clock(clock), .data(bus_mosi), - .q(reg_bits_wire[j*16+15:j*16]), - .aclr(), - .aload(), - .aset(), - .sload(), - .sset()); + .q(reg_bits_wire[j*16+15:j*16])); end endgenerate @@ -84,9 +71,5 @@ .lpm_width(2)) lpm_decode_unit ( .data(bus_addr), - .eq(int_ssel_wire), - .aclr(), - .clken(), - .clock(), - .enable()); + .eq(int_ssel_wire)); always @(posedge clock) @@ -96,9 +79,11 @@ int_miso_reg <= 16'd0; cnt_good_reg <= 1'b0; + int_load_reg <= 1'b0; end else begin int_miso_reg <= int_miso_wire; - cnt_good_reg <= (|cnt_bits_wire) & (cfg_data[1]); + cnt_good_reg <= |cnt_bits_wire; + int_load_reg <= bus_ssel & bus_wren; end end Index: /sandbox/MultiChannelUSB/delay.v =================================================================== --- /sandbox/MultiChannelUSB/delay.v (revision 107) +++ /sandbox/MultiChannelUSB/delay.v (revision 107) @@ -0,0 +1,37 @@ +module delay + #( + parameter width = 12, + parameter length = 32 + ) + ( + input wire clock, frame, reset, + input wire [width-1:0] inp_data, + output wire [width-1:0] out_data + ); + + reg [width-1:0] int_pipe_reg [length-1:0]; + + integer i; + + always @(posedge clock) + begin + if (reset) + begin + for(i = 0; i < length; i = i + 1) + begin + int_pipe_reg[i] <= 0; + end + end + else if (frame) + begin + for(i = 0; i <= 30; i = i + 1) + begin + int_pipe_reg[i+1] <= int_pipe_reg[i]; + end + int_pipe_reg[0] <= inp_data; + end + end + + assign out_data = int_pipe_reg[length-1]; + +endmodule Index: ndbox/MultiChannelUSB/histogram.v =================================================================== --- /sandbox/MultiChannelUSB/histogram.v (revision 106) +++ (revision ) @@ -1,199 +1,0 @@ -module histogram - ( - input wire clock, frame, reset, - - input wire hst_good, - input wire [11:0] hst_data, - - input wire bus_ssel, bus_wren, - input wire [12:0] bus_addr, - input wire [15:0] bus_mosi, - - output wire [15:0] bus_miso, - output wire bus_busy - ); - - // signal declaration - reg [3:0] int_case_reg, int_case_next; - reg int_wren_reg, int_wren_next; - reg [11:0] int_addr_reg, int_addr_next; - reg [31:0] int_data_reg, int_data_next; - - reg [12:0] bus_addr_reg, bus_addr_next; - reg [15:0] bus_miso_reg, bus_miso_next; - - reg bus_wren_reg, bus_wren_next; - reg [15:0] bus_mosi_reg, bus_mosi_next; - - wire [31:0] q_a_wire; - wire [15:0] q_b_wire; - - altsyncram #( - .address_reg_b("CLOCK0"), - .clock_enable_input_a("BYPASS"), - .clock_enable_input_b("BYPASS"), - .clock_enable_output_a("BYPASS"), - .clock_enable_output_b("BYPASS"), - .indata_reg_b("CLOCK0"), - .intended_device_family("Cyclone III"), - .lpm_type("altsyncram"), - .numwords_a(4096), - .numwords_b(8192), - .operation_mode("BIDIR_DUAL_PORT"), - .outdata_aclr_a("NONE"), - .outdata_aclr_b("NONE"), - .outdata_reg_a("CLOCK0"), - .outdata_reg_b("CLOCK0"), - .power_up_uninitialized("FALSE"), - .read_during_write_mode_mixed_ports("OLD_DATA"), - .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), - .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), - .widthad_a(12), - .widthad_b(13), - .width_a(32), - .width_b(16), - .width_byteena_a(1), - .width_byteena_b(1), - .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( - .wren_a(int_wren_reg), - .clock0(clock), - .wren_b(bus_wren_reg), - .address_a(int_addr_reg), - .address_b(bus_addr_reg), - .data_a(int_data_reg), - .data_b(bus_mosi_reg), - .q_a(q_a_wire), - .q_b(q_b_wire), - .aclr0(1'b0), - .aclr1(1'b0), - .addressstall_a(1'b0), - .addressstall_b(1'b0), - .byteena_a(1'b1), - .byteena_b(1'b1), - .clock1(1'b1), - .clocken0(1'b1), - .clocken1(1'b1), - .clocken2(1'b1), - .clocken3(1'b1), - .eccstatus(), - .rden_a(1'b1), - .rden_b(1'b1)); - - // body - always @(posedge clock) - begin - if (reset) - begin - int_wren_reg <= 1'b1; - int_addr_reg <= 12'd0; - int_data_reg <= 32'd0; - int_case_reg <= 4'b0; - bus_addr_reg <= 13'd0; - bus_miso_reg <= 16'd0; - bus_wren_reg <= 1'b0; - bus_mosi_reg <= 16'd0; - end - else - begin - int_wren_reg <= int_wren_next; - int_addr_reg <= int_addr_next; - int_data_reg <= int_data_next; - int_case_reg <= int_case_next; - bus_addr_reg <= bus_addr_next; - bus_miso_reg <= bus_miso_next; - bus_wren_reg <= bus_wren_next; - bus_mosi_reg <= bus_mosi_next; - end - end - - always @* - begin - bus_addr_next = bus_addr_reg; - bus_miso_next = bus_miso_reg; - - bus_wren_next = 1'b0; - bus_mosi_next = bus_mosi_reg; - - if (bus_ssel) - begin - bus_miso_next = q_b_wire; - bus_addr_next = bus_addr; - bus_wren_next = bus_wren; - if (bus_wren) - begin - bus_mosi_next = bus_mosi; - end - end - end - - always @* - begin - int_wren_next = int_wren_reg; - int_addr_next = int_addr_reg; - int_data_next = int_data_reg; - int_case_next = int_case_reg; - - case (int_case_reg) - - 0: - begin - // write zeros - int_addr_next = int_addr_reg + 12'd1; - if (&int_addr_reg) - begin - int_wren_next = 1'b0; - int_case_next = 4'd1; - end - end - - 1: - begin - int_wren_next = 1'b0; -/* - if (&int_data_reg) - begin - int_case_next = 4'd0; - end - else if (frame & hst_good) -*/ - if (frame & hst_good) - begin - int_addr_next = hst_data; - int_case_next = 4'd2; - end - end - - 2: - begin - int_case_next = 4'd3; - end - - 3: - begin - int_case_next = 4'd4; - end - - 4: - begin - int_case_next = 4'd1; - if (~&q_a_wire) - begin - int_wren_next = 1'b1; - int_data_next = q_a_wire + 32'd1; - end - end - - default: - begin - int_wren_next = 1'b0; - int_addr_next = 12'd0; - int_data_next = 32'd0; - int_case_next = 4'd0; - end - endcase - end - - // output logic - assign bus_miso = bus_miso_reg; - assign bus_busy = 1'b0; -endmodule Index: /sandbox/MultiChannelUSB/histogram16.v =================================================================== --- /sandbox/MultiChannelUSB/histogram16.v (revision 107) +++ /sandbox/MultiChannelUSB/histogram16.v (revision 107) @@ -0,0 +1,199 @@ +module histogram16 + ( + input wire clock, frame, reset, + + input wire hst_good, + input wire [13:0] hst_data, + + input wire bus_ssel, bus_wren, + input wire [13:0] bus_addr, + input wire [15:0] bus_mosi, + + output wire [15:0] bus_miso, + output wire bus_busy + ); + + // signal declaration + reg [3:0] int_case_reg, int_case_next; + reg int_wren_reg, int_wren_next; + reg [13:0] int_addr_reg, int_addr_next; + reg [15:0] int_data_reg, int_data_next; + + reg [13:0] bus_addr_reg, bus_addr_next; + reg [15:0] bus_miso_reg, bus_miso_next; + + reg bus_wren_reg, bus_wren_next; + reg [15:0] bus_mosi_reg, bus_mosi_next; + + wire [15:0] q_a_wire; + wire [15:0] q_b_wire; + + altsyncram #( + .address_reg_b("CLOCK0"), + .clock_enable_input_a("BYPASS"), + .clock_enable_input_b("BYPASS"), + .clock_enable_output_a("BYPASS"), + .clock_enable_output_b("BYPASS"), + .indata_reg_b("CLOCK0"), + .intended_device_family("Cyclone III"), + .lpm_type("altsyncram"), + .numwords_a(16384), + .numwords_b(16384), + .operation_mode("BIDIR_DUAL_PORT"), + .outdata_aclr_a("NONE"), + .outdata_aclr_b("NONE"), + .outdata_reg_a("CLOCK0"), + .outdata_reg_b("CLOCK0"), + .power_up_uninitialized("FALSE"), + .read_during_write_mode_mixed_ports("OLD_DATA"), + .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), + .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), + .widthad_a(14), + .widthad_b(14), + .width_a(16), + .width_b(16), + .width_byteena_a(1), + .width_byteena_b(1), + .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( + .wren_a(int_wren_reg), + .clock0(clock), + .wren_b(bus_wren_reg), + .address_a(int_addr_reg), + .address_b(bus_addr_reg), + .data_a(int_data_reg), + .data_b(bus_mosi_reg), + .q_a(q_a_wire), + .q_b(q_b_wire), + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .eccstatus(), + .rden_a(1'b1), + .rden_b(1'b1)); + + // body + always @(posedge clock) + begin + if (reset) + begin + int_wren_reg <= 1'b1; + int_addr_reg <= 14'd0; + int_data_reg <= 16'd0; + int_case_reg <= 4'b0; + bus_addr_reg <= 14'd0; + bus_miso_reg <= 16'd0; + bus_wren_reg <= 1'b0; + bus_mosi_reg <= 16'd0; + end + else + begin + int_wren_reg <= int_wren_next; + int_addr_reg <= int_addr_next; + int_data_reg <= int_data_next; + int_case_reg <= int_case_next; + bus_addr_reg <= bus_addr_next; + bus_miso_reg <= bus_miso_next; + bus_wren_reg <= bus_wren_next; + bus_mosi_reg <= bus_mosi_next; + end + end + + always @* + begin + bus_addr_next = bus_addr_reg; + bus_miso_next = bus_miso_reg; + + bus_wren_next = 1'b0; + bus_mosi_next = bus_mosi_reg; + + if (bus_ssel) + begin + bus_miso_next = q_b_wire; + bus_addr_next = bus_addr; + bus_wren_next = bus_wren; + if (bus_wren) + begin + bus_mosi_next = bus_mosi; + end + end + end + + always @* + begin + int_wren_next = int_wren_reg; + int_addr_next = int_addr_reg; + int_data_next = int_data_reg; + int_case_next = int_case_reg; + + case (int_case_reg) + + 0: + begin + // write zeros + int_addr_next = int_addr_reg + 14'd1; + if (&int_addr_reg) + begin + int_wren_next = 1'b0; + int_case_next = 4'd1; + end + end + + 1: + begin + int_wren_next = 1'b0; +/* + if (&int_data_reg) + begin + int_case_next = 4'd0; + end + else if (frame & hst_good) +*/ + if (frame & hst_good) + begin + int_addr_next = hst_data; + int_case_next = 4'd2; + end + end + + 2: + begin + int_case_next = 4'd3; + end + + 3: + begin + int_case_next = 4'd4; + end + + 4: + begin + int_case_next = 4'd1; + if (~&q_a_wire) + begin + int_wren_next = 1'b1; + int_data_next = q_a_wire + 16'd1; + end + end + + default: + begin + int_wren_next = 1'b0; + int_addr_next = 14'd0; + int_data_next = 16'd0; + int_case_next = 4'd0; + end + endcase + end + + // output logic + assign bus_miso = bus_miso_reg; + assign bus_busy = 1'b0; +endmodule Index: /sandbox/MultiChannelUSB/histogram32.v =================================================================== --- /sandbox/MultiChannelUSB/histogram32.v (revision 107) +++ /sandbox/MultiChannelUSB/histogram32.v (revision 107) @@ -0,0 +1,199 @@ +module histogram32 + ( + input wire clock, frame, reset, + + input wire hst_good, + input wire [11:0] hst_data, + + input wire bus_ssel, bus_wren, + input wire [12:0] bus_addr, + input wire [15:0] bus_mosi, + + output wire [15:0] bus_miso, + output wire bus_busy + ); + + // signal declaration + reg [3:0] int_case_reg, int_case_next; + reg int_wren_reg, int_wren_next; + reg [11:0] int_addr_reg, int_addr_next; + reg [31:0] int_data_reg, int_data_next; + + reg [12:0] bus_addr_reg, bus_addr_next; + reg [15:0] bus_miso_reg, bus_miso_next; + + reg bus_wren_reg, bus_wren_next; + reg [15:0] bus_mosi_reg, bus_mosi_next; + + wire [31:0] q_a_wire; + wire [15:0] q_b_wire; + + altsyncram #( + .address_reg_b("CLOCK0"), + .clock_enable_input_a("BYPASS"), + .clock_enable_input_b("BYPASS"), + .clock_enable_output_a("BYPASS"), + .clock_enable_output_b("BYPASS"), + .indata_reg_b("CLOCK0"), + .intended_device_family("Cyclone III"), + .lpm_type("altsyncram"), + .numwords_a(4096), + .numwords_b(8192), + .operation_mode("BIDIR_DUAL_PORT"), + .outdata_aclr_a("NONE"), + .outdata_aclr_b("NONE"), + .outdata_reg_a("CLOCK0"), + .outdata_reg_b("CLOCK0"), + .power_up_uninitialized("FALSE"), + .read_during_write_mode_mixed_ports("OLD_DATA"), + .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), + .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), + .widthad_a(12), + .widthad_b(13), + .width_a(32), + .width_b(16), + .width_byteena_a(1), + .width_byteena_b(1), + .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit( + .wren_a(int_wren_reg), + .clock0(clock), + .wren_b(bus_wren_reg), + .address_a(int_addr_reg), + .address_b(bus_addr_reg), + .data_a(int_data_reg), + .data_b(bus_mosi_reg), + .q_a(q_a_wire), + .q_b(q_b_wire), + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .eccstatus(), + .rden_a(1'b1), + .rden_b(1'b1)); + + // body + always @(posedge clock) + begin + if (reset) + begin + int_wren_reg <= 1'b1; + int_addr_reg <= 12'd0; + int_data_reg <= 32'd0; + int_case_reg <= 4'b0; + bus_addr_reg <= 13'd0; + bus_miso_reg <= 16'd0; + bus_wren_reg <= 1'b0; + bus_mosi_reg <= 16'd0; + end + else + begin + int_wren_reg <= int_wren_next; + int_addr_reg <= int_addr_next; + int_data_reg <= int_data_next; + int_case_reg <= int_case_next; + bus_addr_reg <= bus_addr_next; + bus_miso_reg <= bus_miso_next; + bus_wren_reg <= bus_wren_next; + bus_mosi_reg <= bus_mosi_next; + end + end + + always @* + begin + bus_addr_next = bus_addr_reg; + bus_miso_next = bus_miso_reg; + + bus_wren_next = 1'b0; + bus_mosi_next = bus_mosi_reg; + + if (bus_ssel) + begin + bus_miso_next = q_b_wire; + bus_addr_next = bus_addr; + bus_wren_next = bus_wren; + if (bus_wren) + begin + bus_mosi_next = bus_mosi; + end + end + end + + always @* + begin + int_wren_next = int_wren_reg; + int_addr_next = int_addr_reg; + int_data_next = int_data_reg; + int_case_next = int_case_reg; + + case (int_case_reg) + + 0: + begin + // write zeros + int_addr_next = int_addr_reg + 12'd1; + if (&int_addr_reg) + begin + int_wren_next = 1'b0; + int_case_next = 4'd1; + end + end + + 1: + begin + int_wren_next = 1'b0; +/* + if (&int_data_reg) + begin + int_case_next = 4'd0; + end + else if (frame & hst_good) +*/ + if (frame & hst_good) + begin + int_addr_next = hst_data; + int_case_next = 4'd2; + end + end + + 2: + begin + int_case_next = 4'd3; + end + + 3: + begin + int_case_next = 4'd4; + end + + 4: + begin + int_case_next = 4'd1; + if (~&q_a_wire) + begin + int_wren_next = 1'b1; + int_data_next = q_a_wire + 32'd1; + end + end + + default: + begin + int_wren_next = 1'b0; + int_addr_next = 12'd0; + int_data_next = 32'd0; + int_case_next = 4'd0; + end + endcase + end + + // output logic + assign bus_miso = bus_miso_reg; + assign bus_busy = 1'b0; +endmodule Index: /sandbox/MultiChannelUSB/spi_fifo.v =================================================================== --- /sandbox/MultiChannelUSB/spi_fifo.v (revision 107) +++ /sandbox/MultiChannelUSB/spi_fifo.v (revision 107) @@ -0,0 +1,128 @@ +module spi_fifo + ( + input wire clock, reset, + + input wire bus_ssel, bus_wren, + input wire [15:0] bus_mosi, + + output wire bus_busy, + + output wire spi_sel, + output wire spi_sdo, + output wire spi_clk + ); + + wire int_rdempty, int_wrfull; + wire [15:0] int_q; + + reg int_bus_busy; + reg int_rdreq, int_wrreq; + reg int_clken, int_sdo, int_sel; + reg [15:0] int_bus_mosi; + reg [15:0] int_data; + reg [2:0] clk_cntr; + reg [3:0] bit_cntr; + reg [1:0] state; + + scfifo #( + .add_ram_output_register("OFF"), + .intended_device_family("Cyclone III"), + .lpm_numwords(16), + .lpm_showahead("ON"), + .lpm_type("scfifo"), + .lpm_width(16), + .lpm_widthu(4), + .overflow_checking("ON"), + .underflow_checking("ON"), + .use_eab("OFF")) fifo_tx ( + .rdreq((~int_rdempty) & (int_rdreq) & (&clk_cntr)), + .aclr(1'b0), + .clock(clock), + .wrreq(int_wrreq), + .data(int_bus_mosi), + .empty(int_rdempty), + .q(int_q), + .full(int_wrfull), + .almost_empty(), + .almost_full(), + .sclr(), + .usedw()); + + always @ (posedge clock) + begin + int_bus_busy <= int_wrfull; + + if (bus_ssel) + begin + if (~int_wrfull & bus_wren) + begin + int_bus_mosi <= bus_mosi; + int_wrreq <= 1'b1; + end + end + + if (~int_wrfull & int_wrreq) + begin + int_wrreq <= 1'b0; + end + + end + + always @ (posedge clock) + begin + clk_cntr <= clk_cntr + 3'd1; + if (&clk_cntr) + begin + case (state) + 0: + begin + int_sdo <= 1'b0; + int_sel <= 1'b1; + int_clken <= 1'b0; + int_rdreq <= 1'b1; + state <= 2'd1; + end + + 1: + begin + if (~int_rdempty) + begin + int_rdreq <= 1'b0; + int_data <= int_q; + bit_cntr <= 4'd0; + state <= 2'd2; + end + end + + + 2: + begin // data + int_clken <= 1'b1; + int_sel <= 1'b0; + int_sdo <= int_data[11]; + int_data <= {int_data[10:0], 1'b0}; + bit_cntr <= bit_cntr + 4'd1; + if (bit_cntr == 4'd11) + begin + state <= 2'd3; + end + end + + 3: + begin + int_sdo <= 1'b0; + int_clken <= 1'b0; + state <= 2'd0; + end + + endcase + end + end + + // output logic + assign bus_busy = int_bus_busy; + assign spi_clk = (int_clken ? clk_cntr[2] : 1'b1); + assign spi_sdo = int_sdo; + assign spi_sel = int_sel; + +endmodule Index: /sandbox/MultiChannelUSB/test.mif =================================================================== --- /sandbox/MultiChannelUSB/test.mif (revision 107) +++ /sandbox/MultiChannelUSB/test.mif (revision 107) @@ -0,0 +1,2584 @@ +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=12; +DEPTH=2560; + +ADDRESS_RADIX=HEX; +DATA_RADIX=UNS; + +CONTENT BEGIN +0000 : 1176; +0001 : 1178; +0002 : 1178; +0003 : 1177; +0004 : 1177; +0005 : 1176; +0006 : 1177; +0007 : 1179; +0008 : 1178; +0009 : 1178; +000A : 1178; +000B : 1177; +000C : 1179; +000D : 1178; +000E : 1178; +000F : 1176; +0010 : 1177; +0011 : 1178; +0012 : 1177; +0013 : 1177; +0014 : 1176; +0015 : 1177; +0016 : 1177; +0017 : 1177; +0018 : 1177; +0019 : 1177; +001A : 1178; +001B : 1178; +001C : 1178; +001D : 1178; +001E : 1178; +001F : 1178; +0020 : 1178; +0021 : 1178; +0022 : 1177; +0023 : 1177; +0024 : 1178; +0025 : 1178; +0026 : 1179; +0027 : 1177; +0028 : 1177; +0029 : 1177; +002A : 1178; +002B : 1178; +002C : 1176; +002D : 1177; +002E : 1178; +002F : 1179; +0030 : 1179; +0031 : 1178; +0032 : 1177; +0033 : 1176; +0034 : 1179; +0035 : 1178; +0036 : 1177; +0037 : 1177; +0038 : 1177; +0039 : 1177; +003A : 1178; +003B : 1178; +003C : 1177; +003D : 1177; +003E : 1178; +003F : 1178; +0040 : 1179; +0041 : 1177; +0042 : 1177; +0043 : 1179; +0044 : 1179; +0045 : 1179; +0046 : 1179; +0047 : 1178; +0048 : 1178; +0049 : 1179; +004A : 1178; +004B : 1178; +004C : 1178; +004D : 1178; +004E : 1178; +004F : 1178; +0050 : 1178; +0051 : 1177; +0052 : 1178; +0053 : 1179; +0054 : 1178; +0055 : 1178; +0056 : 1177; +0057 : 1178; +0058 : 1178; +0059 : 1178; +005A : 1177; +005B : 1177; +005C : 1177; +005D : 1272; +005E : 1649; +005F : 1845; +0060 : 1893; +0061 : 1903; +0062 : 1905; +0063 : 1904; +0064 : 1899; +0065 : 1897; +0066 : 1895; +0067 : 1896; +0068 : 1894; +0069 : 1893; +006A : 1891; +006B : 1891; +006C : 1890; +006D : 1889; +006E : 1888; +006F : 1887; +0070 : 1887; +0071 : 1887; +0072 : 1886; +0073 : 1885; +0074 : 1884; +0075 : 1883; +0076 : 1884; +0077 : 1883; +0078 : 1881; +0079 : 1880; +007A : 1880; +007B : 1880; +007C : 1876; +007D : 1873; +007E : 1874; +007F : 1875; +0080 : 1874; +0081 : 1875; +0082 : 1873; +0083 : 1873; +0084 : 1874; +0085 : 1872; +0086 : 1871; +0087 : 1870; +0088 : 1870; +0089 : 1869; +008A : 1869; +008B : 1868; +008C : 1866; +008D : 1865; +008E : 1866; +008F : 1865; +0090 : 1864; +0091 : 1863; +0092 : 1861; +0093 : 1861; +0094 : 1861; +0095 : 1860; +0096 : 1858; +0097 : 1857; +0098 : 1856; +0099 : 1858; +009A : 1857; +009B : 1856; +009C : 1855; +009D : 1855; +009E : 1854; +009F : 1854; +00A0 : 1852; +00A1 : 1851; +00A2 : 1851; +00A3 : 1852; +00A4 : 1850; +00A5 : 1849; +00A6 : 1847; +00A7 : 1847; +00A8 : 1847; +00A9 : 1847; +00AA : 1845; +00AB : 1844; +00AC : 1843; +00AD : 1844; +00AE : 1843; +00AF : 1842; +00B0 : 1840; +00B1 : 1840; +00B2 : 1841; +00B3 : 1840; +00B4 : 1838; +00B5 : 1837; +00B6 : 1837; +00B7 : 1837; +00B8 : 1836; +00B9 : 1835; +00BA : 1834; +00BB : 1833; +00BC : 1832; +00BD : 1833; +00BE : 1832; +00BF : 1831; +00C0 : 1830; +00C1 : 1830; +00C2 : 1829; +00C3 : 1828; +00C4 : 1826; +00C5 : 1827; +00C6 : 1827; +00C7 : 1826; +00C8 : 1825; +00C9 : 1823; +00CA : 1823; +00CB : 1823; +00CC : 1823; +00CD : 1821; +00CE : 1820; +00CF : 1820; +00D0 : 1820; +00D1 : 1820; +00D2 : 1819; +00D3 : 1818; +00D4 : 1816; +00D5 : 1817; +00D6 : 1816; +00D7 : 1815; +00D8 : 1813; +00D9 : 1813; +00DA : 1813; +00DB : 1812; +00DC : 1811; +00DD : 1810; +00DE : 1810; +00DF : 1810; +00E0 : 1810; +00E1 : 1808; +00E2 : 1807; +00E3 : 1805; +00E4 : 1806; +00E5 : 1807; +00E6 : 1806; +00E7 : 1803; +00E8 : 1802; +00E9 : 1803; +00EA : 1803; +00EB : 1802; +00EC : 1799; +00ED : 1799; +00EE : 1799; +00EF : 1799; +00F0 : 1797; +00F1 : 1796; +00F2 : 1796; +00F3 : 1796; +00F4 : 1796; +00F5 : 1795; +00F6 : 1794; +00F7 : 1792; +00F8 : 1793; +00F9 : 1792; +00FA : 1792; +00FB : 1791; +00FC : 1789; +00FD : 1789; +00FE : 1789; +00FF : 1788; +0100 : 1787; +0101 : 1787; +0102 : 1787; +0103 : 1786; +0104 : 1785; +0105 : 1783; +0106 : 1782; +0107 : 1782; +0108 : 1783; +0109 : 1782; +010A : 1781; +010B : 1779; +010C : 1779; +010D : 1779; +010E : 1778; +010F : 1777; +0110 : 1777; +0111 : 1777; +0112 : 1776; +0113 : 1775; +0114 : 1774; +0115 : 1774; +0116 : 1773; +0117 : 1773; +0118 : 1772; +0119 : 1772; +011A : 1771; +011B : 1770; +011C : 1769; +011D : 1769; +011E : 1768; +011F : 1767; +0120 : 1767; +0121 : 1766; +0122 : 1766; +0123 : 1765; +0124 : 1764; +0125 : 1763; +0126 : 1763; +0127 : 1762; +0128 : 1761; +0129 : 1760; +012A : 1761; +012B : 1760; +012C : 1760; +012D : 1759; +012E : 1757; +012F : 1757; +0130 : 1758; +0131 : 1757; +0132 : 1755; +0133 : 1753; +0134 : 1754; +0135 : 1753; +0136 : 1754; +0137 : 1752; +0138 : 1752; +0139 : 1751; +013A : 1752; +013B : 1751; +013C : 1750; +013D : 1749; +013E : 1749; +013F : 1748; +0140 : 1748; +0141 : 1747; +0142 : 1746; +0143 : 1745; +0144 : 1745; +0145 : 1745; +0146 : 1743; +0147 : 1742; +0148 : 1742; +0149 : 1742; +014A : 1741; +014B : 1740; +014C : 1740; +014D : 1740; +014E : 1739; +014F : 1739; +0150 : 1737; +0151 : 1736; +0152 : 1736; +0153 : 1736; +0154 : 1735; +0155 : 1734; +0156 : 1732; +0157 : 1732; +0158 : 1733; +0159 : 1732; +015A : 1732; +015B : 1730; +015C : 1730; +015D : 1730; +015E : 1729; +015F : 1728; +0160 : 1727; +0161 : 1727; +0162 : 1726; +0163 : 1726; +0164 : 1725; +0165 : 1723; +0166 : 1723; +0167 : 1724; +0168 : 1723; +0169 : 1722; +016A : 1720; +016B : 1720; +016C : 1721; +016D : 1721; +016E : 1719; +016F : 1718; +0170 : 1716; +0171 : 1718; +0172 : 1718; +0173 : 1716; +0174 : 1716; +0175 : 1714; +0176 : 1715; +0177 : 1715; +0178 : 1714; +0179 : 1711; +017A : 1710; +017B : 1711; +017C : 1710; +017D : 1710; +017E : 1710; +017F : 1708; +0180 : 1708; +0181 : 1708; +0182 : 1708; +0183 : 1707; +0184 : 1705; +0185 : 1705; +0186 : 1705; +0187 : 1704; +0188 : 1703; +0189 : 1703; +018A : 1702; +018B : 1702; +018C : 1702; +018D : 1701; +018E : 1700; +018F : 1700; +0190 : 1700; +0191 : 1699; +0192 : 1697; +0193 : 1697; +0194 : 1697; +0195 : 1697; +0196 : 1696; +0197 : 1696; +0198 : 1693; +0199 : 1695; +019A : 1694; +019B : 1694; +019C : 1691; +019D : 1691; +019E : 1691; +019F : 1690; +01A0 : 1691; +01A1 : 1690; +01A2 : 1689; +01A3 : 1688; +01A4 : 1688; +01A5 : 1688; +01A6 : 1687; +01A7 : 1685; +01A8 : 1686; +01A9 : 1686; +01AA : 1686; +01AB : 1684; +01AC : 1684; +01AD : 1684; +01AE : 1683; +01AF : 1683; +01B0 : 1682; +01B1 : 1681; +01B2 : 1681; +01B3 : 1681; +01B4 : 1680; +01B5 : 1679; +01B6 : 1678; +01B7 : 1676; +01B8 : 1677; +01B9 : 1677; +01BA : 1676; +01BB : 1675; +01BC : 1675; +01BD : 1674; +01BE : 1674; +01BF : 1673; +01C0 : 1672; +01C1 : 1673; +01C2 : 1672; +01C3 : 1672; +01C4 : 1670; +01C5 : 1669; +01C6 : 1668; +01C7 : 1669; +01C8 : 1669; +01C9 : 1668; +01CA : 1667; +01CB : 1667; +01CC : 1666; +01CD : 1666; +01CE : 1665; +01CF : 1664; +01D0 : 1664; +01D1 : 1665; +01D2 : 1663; +01D3 : 1663; +01D4 : 1661; +01D5 : 1661; +01D6 : 1660; +01D7 : 1661; +01D8 : 1660; +01D9 : 1657; +01DA : 1657; +01DB : 1659; +01DC : 1658; +01DD : 1657; +01DE : 1656; +01DF : 1656; +01E0 : 1656; +01E1 : 1656; +01E2 : 1654; +01E3 : 1653; +01E4 : 1653; +01E5 : 1654; +01E6 : 1653; +01E7 : 1651; +01E8 : 1650; +01E9 : 1650; +01EA : 1651; +01EB : 1651; +01EC : 1649; +01ED : 1648; +01EE : 1648; +01EF : 1648; +01F0 : 1648; +01F1 : 1647; +01F2 : 1646; +01F3 : 1645; +01F4 : 1645; +01F5 : 1645; +01F6 : 1644; +01F7 : 1643; +01F8 : 1643; +01F9 : 1643; +01FA : 1642; +01FB : 1642; +01FC : 1640; +01FD : 1640; +01FE : 1640; +01FF : 1640; +0200 : 1639; +0201 : 1637; +0202 : 1637; +0203 : 1637; +0204 : 1638; +0205 : 1636; +0206 : 1635; +0207 : 1634; +0208 : 1634; +0209 : 1634; +020A : 1634; +020B : 1633; +020C : 1632; +020D : 1631; +020E : 1631; +020F : 1631; +0210 : 1631; +0211 : 1630; +0212 : 1630; +0213 : 1629; +0214 : 1629; +0215 : 1627; +0216 : 1627; +0217 : 1628; +0218 : 1628; +0219 : 1627; +021A : 1626; +021B : 1626; +021C : 1625; +021D : 1625; +021E : 1625; +021F : 1622; +0220 : 1622; +0221 : 1621; +0222 : 1622; +0223 : 1622; +0224 : 1621; +0225 : 1620; +0226 : 1620; +0227 : 1620; +0228 : 1620; +0229 : 1618; +022A : 1616; +022B : 1617; +022C : 1617; +022D : 1618; +022E : 1617; +022F : 1615; +0230 : 1615; +0231 : 1615; +0232 : 1615; +0233 : 1613; +0234 : 1613; +0235 : 1611; +0236 : 1613; +0237 : 1613; +0238 : 1611; +0239 : 1609; +023A : 1610; +023B : 1610; +023C : 1610; +023D : 1609; +023E : 1608; +023F : 1607; +0240 : 1607; +0241 : 1608; +0242 : 1606; +0243 : 1606; +0244 : 1606; +0245 : 1605; +0246 : 1605; +0247 : 1604; +0248 : 1602; +0249 : 1602; +024A : 1602; +024B : 1602; +024C : 1602; +024D : 1601; +024E : 1599; +024F : 1599; +0250 : 1600; +0251 : 1598; +0252 : 1596; +0253 : 1596; +0254 : 1598; +0255 : 1597; +0256 : 1596; +0257 : 1595; +0258 : 1595; +0259 : 1595; +025A : 1595; +025B : 1593; +025C : 1592; +025D : 1593; +025E : 1592; +025F : 1592; +0260 : 1592; +0261 : 1590; +0262 : 1590; +0263 : 1591; +0264 : 1590; +0265 : 1589; +0266 : 1588; +0267 : 1587; +0268 : 1588; +0269 : 1587; +026A : 1587; +026B : 1586; +026C : 1585; +026D : 1586; +026E : 1586; +026F : 1584; +0270 : 1584; +0271 : 1582; +0272 : 1583; +0273 : 1583; +0274 : 1583; +0275 : 1581; +0276 : 1580; +0277 : 1581; +0278 : 1581; +0279 : 1580; +027A : 1579; +027B : 1579; +027C : 1579; +027D : 1580; +027E : 1578; +027F : 1577; +0280 : 1576; +0281 : 1577; +0282 : 1576; +0283 : 1575; +0284 : 1573; +0285 : 1574; +0286 : 1575; +0287 : 1575; +0288 : 1573; +0289 : 1572; +028A : 1572; +028B : 1573; +028C : 1572; +028D : 1572; +028E : 1570; +028F : 1569; +0290 : 1569; +0291 : 1570; +0292 : 1569; +0293 : 1568; +0294 : 1568; +0295 : 1568; +0296 : 1569; +0297 : 1568; +0298 : 1565; +0299 : 1565; +029A : 1565; +029B : 1565; +029C : 1566; +029D : 1565; +029E : 1563; +029F : 1562; +02A0 : 1563; +02A1 : 1563; +02A2 : 1562; +02A3 : 1561; +02A4 : 1562; +02A5 : 1561; +02A6 : 1560; +02A7 : 1559; +02A8 : 1558; +02A9 : 1558; +02AA : 1558; +02AB : 1557; +02AC : 1556; +02AD : 1555; +02AE : 1557; +02AF : 1556; +02B0 : 1557; +02B1 : 1554; +02B2 : 1554; +02B3 : 1554; +02B4 : 1554; +02B5 : 1553; +02B6 : 1552; +02B7 : 1552; +02B8 : 1552; +02B9 : 1552; +02BA : 1551; +02BB : 1551; +02BC : 1549; +02BD : 1550; +02BE : 1550; +02BF : 1549; +02C0 : 1548; +02C1 : 1548; +02C2 : 1547; +02C3 : 1548; +02C4 : 1548; +02C5 : 1547; +02C6 : 1546; +02C7 : 1545; +02C8 : 1546; +02C9 : 1546; +02CA : 1544; +02CB : 1543; +02CC : 1543; +02CD : 1543; +02CE : 1543; +02CF : 1542; +02D0 : 1541; +02D1 : 1541; +02D2 : 1542; +02D3 : 1541; +02D4 : 1540; +02D5 : 1538; +02D6 : 1539; +02D7 : 1540; +02D8 : 1539; +02D9 : 1538; +02DA : 1536; +02DB : 1537; +02DC : 1537; +02DD : 1537; +02DE : 1536; +02DF : 1535; +02E0 : 1535; +02E1 : 1536; +02E2 : 1535; +02E3 : 1533; +02E4 : 1532; +02E5 : 1533; +02E6 : 1532; +02E7 : 1532; +02E8 : 1532; +02E9 : 1531; +02EA : 1530; +02EB : 1531; +02EC : 1532; +02ED : 1530; +02EE : 1529; +02EF : 1529; +02F0 : 1529; +02F1 : 1529; +02F2 : 1528; +02F3 : 1527; +02F4 : 1527; +02F5 : 1528; +02F6 : 1527; +02F7 : 1526; +02F8 : 1525; +02F9 : 1525; +02FA : 1526; +02FB : 1526; +02FC : 1525; +02FD : 1523; +02FE : 1522; +02FF : 1523; +0300 : 1523; +0301 : 1522; +0302 : 1521; +0303 : 1520; +0304 : 1520; +0305 : 1521; +0306 : 1520; +0307 : 1519; +0308 : 1519; +0309 : 1519; +030A : 1518; +030B : 1518; +030C : 1517; +030D : 1516; +030E : 1518; +030F : 1516; +0310 : 1516; +0311 : 1515; +0312 : 1515; +0313 : 1515; +0314 : 1516; +0315 : 1515; +0316 : 1514; +0317 : 1512; +0318 : 1513; +0319 : 1513; +031A : 1512; +031B : 1510; +031C : 1510; +031D : 1509; +031E : 1511; +031F : 1510; +0320 : 1509; +0321 : 1510; +0322 : 1508; +0323 : 1509; +0324 : 1508; +0325 : 1507; +0326 : 1507; +0327 : 1506; +0328 : 1507; +0329 : 1506; +032A : 1505; +032B : 1504; +032C : 1504; +032D : 1504; +032E : 1504; +032F : 1503; +0330 : 1503; +0331 : 1503; +0332 : 1504; +0333 : 1502; +0334 : 1500; +0335 : 1499; +0336 : 1501; +0337 : 1501; +0338 : 1501; +0339 : 1500; +033A : 1499; +033B : 1499; +033C : 1499; +033D : 1499; +033E : 1499; +033F : 1498; +0340 : 1497; +0341 : 1498; +0342 : 1497; +0343 : 1496; +0344 : 1496; +0345 : 1495; +0346 : 1495; +0347 : 1495; +0348 : 1494; +0349 : 1493; +034A : 1494; +034B : 1494; +034C : 1494; +034D : 1492; +034E : 1491; +034F : 1492; +0350 : 1492; +0351 : 1492; +0352 : 1491; +0353 : 1490; +0354 : 1490; +0355 : 1490; +0356 : 1490; +0357 : 1489; +0358 : 1488; +0359 : 1487; +035A : 1488; +035B : 1489; +035C : 1487; +035D : 1486; +035E : 1486; +035F : 1486; +0360 : 1487; +0361 : 1485; +0362 : 1484; +0363 : 1485; +0364 : 1485; +0365 : 1485; +0366 : 1483; +0367 : 1482; +0368 : 1482; +0369 : 1482; +036A : 1482; +036B : 1482; +036C : 1481; +036D : 1480; +036E : 1480; +036F : 1480; +0370 : 1479; +0371 : 1479; +0372 : 1478; +0373 : 1479; +0374 : 1479; +0375 : 1478; +0376 : 1477; +0377 : 1477; +0378 : 1477; +0379 : 1477; +037A : 1476; +037B : 1475; +037C : 1475; +037D : 1476; +037E : 1475; +037F : 1474; +0380 : 1473; +0381 : 1472; +0382 : 1473; +0383 : 1473; +0384 : 1472; +0385 : 1471; +0386 : 1471; +0387 : 1471; +0388 : 1471; +0389 : 1470; +038A : 1470; +038B : 1468; +038C : 1469; +038D : 1471; +038E : 1469; +038F : 1468; +0390 : 1467; +0391 : 1467; +0392 : 1467; +0393 : 1468; +0394 : 1466; +0395 : 1466; +0396 : 1466; +0397 : 1466; +0398 : 1466; +0399 : 1464; +039A : 1464; +039B : 1464; +039C : 1464; +039D : 1463; +039E : 1462; +039F : 1462; +03A0 : 1461; +03A1 : 1462; +03A2 : 1462; +03A3 : 1461; +03A4 : 1460; +03A5 : 1461; +03A6 : 1462; +03A7 : 1461; +03A8 : 1459; +03A9 : 1459; +03AA : 1459; +03AB : 1459; +03AC : 1458; +03AD : 1458; +03AE : 1457; +03AF : 1457; +03B0 : 1458; +03B1 : 1457; +03B2 : 1455; +03B3 : 1456; +03B4 : 1456; +03B5 : 1457; +03B6 : 1455; +03B7 : 1454; +03B8 : 1454; +03B9 : 1454; +03BA : 1454; +03BB : 1454; +03BC : 1452; +03BD : 1451; +03BE : 1451; +03BF : 1452; +03C0 : 1451; +03C1 : 1451; +03C2 : 1450; +03C3 : 1450; +03C4 : 1450; +03C5 : 1450; +03C6 : 1448; +03C7 : 1447; +03C8 : 1448; +03C9 : 1449; +03CA : 1449; +03CB : 1447; +03CC : 1446; +03CD : 1447; +03CE : 1447; +03CF : 1447; +03D0 : 1447; +03D1 : 1446; +03D2 : 1445; +03D3 : 1445; +03D4 : 1445; +03D5 : 1444; +03D6 : 1444; +03D7 : 1444; +03D8 : 1444; +03D9 : 1444; +03DA : 1442; +03DB : 1442; +03DC : 1442; +03DD : 1442; +03DE : 1442; +03DF : 1441; +03E0 : 1440; +03E1 : 1441; +03E2 : 1441; +03E3 : 1440; +03E4 : 1439; +03E5 : 1439; +03E6 : 1439; +03E7 : 1439; +03E8 : 1439; +03E9 : 1438; +03EA : 1437; +03EB : 1437; +03EC : 1438; +03ED : 1438; +03EE : 1437; +03EF : 1436; +03F0 : 1435; +03F1 : 1436; +03F2 : 1435; +03F3 : 1435; +03F4 : 1434; +03F5 : 1434; +03F6 : 1435; +03F7 : 1435; +03F8 : 1433; +03F9 : 1432; +03FA : 1432; +03FB : 1433; +03FC : 1433; +03FD : 1431; +03FE : 1431; +03FF : 1431; +0400 : 1431; +0401 : 1433; +0402 : 1431; +0403 : 1430; +0404 : 1429; +0405 : 1429; +0406 : 1430; +0407 : 1429; +0408 : 1428; +0409 : 1427; +040A : 1428; +040B : 1428; +040C : 1427; +040D : 1426; +040E : 1427; +040F : 1427; +0410 : 1427; +0411 : 1426; +0412 : 1425; +0413 : 1425; +0414 : 1425; +0415 : 1425; +0416 : 1424; +0417 : 1423; +0418 : 1423; +0419 : 1423; +041A : 1424; +041B : 1422; +041C : 1422; +041D : 1422; +041E : 1421; +041F : 1421; +0420 : 1420; +0421 : 1420; +0422 : 1419; +0423 : 1420; +0424 : 1420; +0425 : 1420; +0426 : 1419; +0427 : 1418; +0428 : 1418; +0429 : 1418; +042A : 1418; +042B : 1417; +042C : 1416; +042D : 1417; +042E : 1417; +042F : 1417; +0430 : 1416; +0431 : 1415; +0432 : 1416; +0433 : 1416; +0434 : 1416; +0435 : 1415; +0436 : 1413; +0437 : 1414; +0438 : 1414; +0439 : 1414; +043A : 1414; +043B : 1413; +043C : 1413; +043D : 1414; +043E : 1413; +043F : 1411; +0440 : 1411; +0441 : 1411; +0442 : 1411; +0443 : 1412; +0444 : 1410; +0445 : 1409; +0446 : 1409; +0447 : 1409; +0448 : 1410; +0449 : 1409; +044A : 1408; +044B : 1408; +044C : 1408; +044D : 1408; +044E : 1407; +044F : 1406; +0450 : 1406; +0451 : 1407; +0452 : 1407; +0453 : 1406; +0454 : 1405; +0455 : 1406; +0456 : 1406; +0457 : 1405; +0458 : 1405; +0459 : 1403; +045A : 1404; +045B : 1403; +045C : 1403; +045D : 1403; +045E : 1402; +045F : 1402; +0460 : 1403; +0461 : 1403; +0462 : 1401; +0463 : 1400; +0464 : 1401; +0465 : 1401; +0466 : 1401; +0467 : 1400; +0468 : 1398; +0469 : 1399; +046A : 1400; +046B : 1400; +046C : 1398; +046D : 1398; +046E : 1398; +046F : 1398; +0470 : 1398; +0471 : 1398; +0472 : 1396; +0473 : 1396; +0474 : 1397; +0475 : 1398; +0476 : 1395; +0477 : 1394; +0478 : 1395; +0479 : 1394; +047A : 1396; +047B : 1395; +047C : 1394; +047D : 1393; +047E : 1394; +047F : 1395; +0480 : 1393; +0481 : 1392; +0482 : 1392; +0483 : 1392; +0484 : 1393; +0485 : 1393; +0486 : 1392; +0487 : 1390; +0488 : 1391; +0489 : 1391; +048A : 1391; +048B : 1389; +048C : 1389; +048D : 1390; +048E : 1390; +048F : 1389; +0490 : 1388; +0491 : 1387; +0492 : 1389; +0493 : 1389; +0494 : 1389; +0495 : 1387; +0496 : 1386; +0497 : 1387; +0498 : 1387; +0499 : 1387; +049A : 1386; +049B : 1385; +049C : 1387; +049D : 1387; +049E : 1386; +049F : 1384; +04A0 : 1384; +04A1 : 1385; +04A2 : 1385; +04A3 : 1385; +04A4 : 1383; +04A5 : 1383; +04A6 : 1383; +04A7 : 1384; +04A8 : 1383; +04A9 : 1381; +04AA : 1380; +04AB : 1381; +04AC : 1382; +04AD : 1381; +04AE : 1380; +04AF : 1381; +04B0 : 1381; +04B1 : 1381; +04B2 : 1380; +04B3 : 1378; +04B4 : 1379; +04B5 : 1379; +04B6 : 1379; +04B7 : 1379; +04B8 : 1379; +04B9 : 1378; +04BA : 1378; +04BB : 1377; +04BC : 1377; +04BD : 1377; +04BE : 1376; +04BF : 1376; +04C0 : 1377; +04C1 : 1377; +04C2 : 1375; +04C3 : 1375; +04C4 : 1375; +04C5 : 1376; +04C6 : 1376; +04C7 : 1375; +04C8 : 1374; +04C9 : 1374; +04CA : 1374; +04CB : 1373; +04CC : 1372; +04CD : 1372; +04CE : 1372; +04CF : 1373; +04D0 : 1373; +04D1 : 1371; +04D2 : 1371; +04D3 : 1372; +04D4 : 1371; +04D5 : 1372; +04D6 : 1370; +04D7 : 1370; +04D8 : 1371; +04D9 : 1371; +04DA : 1370; +04DB : 1369; +04DC : 1368; +04DD : 1368; +04DE : 1369; +04DF : 1368; +04E0 : 1369; +04E1 : 1367; +04E2 : 1367; +04E3 : 1368; +04E4 : 1367; +04E5 : 1366; +04E6 : 1366; +04E7 : 1365; +04E8 : 1367; +04E9 : 1366; +04EA : 1365; +04EB : 1365; +04EC : 1365; +04ED : 1366; +04EE : 1365; +04EF : 1365; +04F0 : 1363; +04F1 : 1363; +04F2 : 1364; +04F3 : 1363; +04F4 : 1363; +04F5 : 1361; +04F6 : 1362; +04F7 : 1362; +04F8 : 1362; +04F9 : 1362; +04FA : 1360; +04FB : 1361; +04FC : 1361; +04FD : 1361; +04FE : 1359; +04FF : 1359; +0500 : 1359; +0501 : 1360; +0502 : 1360; +0503 : 1358; +0504 : 1358; +0505 : 1359; +0506 : 1359; +0507 : 1358; +0508 : 1357; +0509 : 1357; +050A : 1358; +050B : 1357; +050C : 1358; +050D : 1357; +050E : 1355; +050F : 1356; +0510 : 1355; +0511 : 1357; +0512 : 1356; +0513 : 1355; +0514 : 1355; +0515 : 1355; +0516 : 1355; +0517 : 1354; +0518 : 1352; +0519 : 1353; +051A : 1354; +051B : 1354; +051C : 1353; +051D : 1352; +051E : 1352; +051F : 1353; +0520 : 1353; +0521 : 1351; +0522 : 1351; +0523 : 1351; +0524 : 1351; +0525 : 1351; +0526 : 1351; +0527 : 1349; +0528 : 1349; +0529 : 1349; +052A : 1349; +052B : 1349; +052C : 1348; +052D : 1348; +052E : 1349; +052F : 1349; +0530 : 1348; +0531 : 1346; +0532 : 1346; +0533 : 1347; +0534 : 1346; +0535 : 1346; +0536 : 1346; +0537 : 1345; +0538 : 1345; +0539 : 1346; +053A : 1345; +053B : 1344; +053C : 1343; +053D : 1344; +053E : 1344; +053F : 1343; +0540 : 1343; +0541 : 1342; +0542 : 1342; +0543 : 1343; +0544 : 1342; +0545 : 1341; +0546 : 1342; +0547 : 1342; +0548 : 1341; +0549 : 1341; +054A : 1341; +054B : 1341; +054C : 1340; +054D : 1341; +054E : 1341; +054F : 1339; +0550 : 1339; +0551 : 1339; +0552 : 1340; +0553 : 1339; +0554 : 1338; +0555 : 1337; +0556 : 1338; +0557 : 1339; +0558 : 1338; +0559 : 1337; +055A : 1337; +055B : 1337; +055C : 1338; +055D : 1337; +055E : 1336; +055F : 1335; +0560 : 1337; +0561 : 1336; +0562 : 1336; +0563 : 1335; +0564 : 1334; +0565 : 1334; +0566 : 1335; +0567 : 1335; +0568 : 1334; +0569 : 1334; +056A : 1333; +056B : 1334; +056C : 1334; +056D : 1333; +056E : 1332; +056F : 1332; +0570 : 1332; +0571 : 1333; +0572 : 1332; +0573 : 1331; +0574 : 1331; +0575 : 1332; +0576 : 1332; +0577 : 1331; +0578 : 1330; +0579 : 1331; +057A : 1331; +057B : 1330; +057C : 1329; +057D : 1328; +057E : 1328; +057F : 1329; +0580 : 1330; +0581 : 1329; +0582 : 1328; +0583 : 1327; +0584 : 1328; +0585 : 1328; +0586 : 1328; +0587 : 1328; +0588 : 1327; +0589 : 1328; +058A : 1327; +058B : 1326; +058C : 1326; +058D : 1326; +058E : 1327; +058F : 1326; +0590 : 1325; +0591 : 1325; +0592 : 1324; +0593 : 1325; +0594 : 1324; +0595 : 1324; +0596 : 1323; +0597 : 1322; +0598 : 1323; +0599 : 1323; +059A : 1322; +059B : 1321; +059C : 1322; +059D : 1322; +059E : 1323; +059F : 1321; +05A0 : 1322; +05A1 : 1320; +05A2 : 1321; +05A3 : 1320; +05A4 : 1322; +05A5 : 1320; +05A6 : 1320; +05A7 : 1320; +05A8 : 1321; +05A9 : 1319; +05AA : 1319; +05AB : 1318; +05AC : 1319; +05AD : 1320; +05AE : 1319; +05AF : 1318; +05B0 : 1318; +05B1 : 1318; +05B2 : 1318; +05B3 : 1317; +05B4 : 1317; +05B5 : 1318; +05B6 : 1317; +05B7 : 1317; +05B8 : 1318; +05B9 : 1316; +05BA : 1316; +05BB : 1317; +05BC : 1317; +05BD : 1316; +05BE : 1315; +05BF : 1314; +05C0 : 1315; +05C1 : 1315; +05C2 : 1315; +05C3 : 1314; +05C4 : 1313; +05C5 : 1313; +05C6 : 1315; +05C7 : 1314; +05C8 : 1314; +05C9 : 1313; +05CA : 1312; +05CB : 1313; +05CC : 1313; +05CD : 1312; +05CE : 1313; +05CF : 1312; +05D0 : 1313; +05D1 : 1312; +05D2 : 1312; +05D3 : 1311; +05D4 : 1312; +05D5 : 1312; +05D6 : 1312; +05D7 : 1311; +05D8 : 1310; +05D9 : 1310; +05DA : 1311; +05DB : 1310; +05DC : 1309; +05DD : 1309; +05DE : 1309; +05DF : 1310; +05E0 : 1310; +05E1 : 1309; +05E2 : 1308; +05E3 : 1308; +05E4 : 1308; +05E5 : 1308; +05E6 : 1307; +05E7 : 1306; +05E8 : 1307; +05E9 : 1307; +05EA : 1308; +05EB : 1306; +05EC : 1306; +05ED : 1306; +05EE : 1307; +05EF : 1306; +05F0 : 1305; +05F1 : 1305; +05F2 : 1304; +05F3 : 1305; +05F4 : 1305; +05F5 : 1305; +05F6 : 1304; +05F7 : 1305; +05F8 : 1304; +05F9 : 1304; +05FA : 1304; +05FB : 1302; +05FC : 1304; +05FD : 1304; +05FE : 1303; +05FF : 1302; +0600 : 1302; +0601 : 1302; +0602 : 1302; +0603 : 1303; +0604 : 1303; +0605 : 1302; +0606 : 1302; +0607 : 1302; +0608 : 1302; +0609 : 1301; +060A : 1301; +060B : 1301; +060C : 1301; +060D : 1301; +060E : 1300; +060F : 1300; +0610 : 1300; +0611 : 1300; +0612 : 1300; +0613 : 1300; +0614 : 1297; +0615 : 1299; +0616 : 1299; +0617 : 1299; +0618 : 1299; +0619 : 1298; +061A : 1298; +061B : 1298; +061C : 1299; +061D : 1298; +061E : 1297; +061F : 1297; +0620 : 1296; +0621 : 1298; +0622 : 1297; +0623 : 1296; +0624 : 1295; +0625 : 1297; +0626 : 1296; +0627 : 1296; +0628 : 1294; +0629 : 1296; +062A : 1295; +062B : 1295; +062C : 1294; +062D : 1294; +062E : 1294; +062F : 1294; +0630 : 1294; +0631 : 1294; +0632 : 1293; +0633 : 1293; +0634 : 1292; +0635 : 1294; +0636 : 1294; +0637 : 1291; +0638 : 1292; +0639 : 1293; +063A : 1293; +063B : 1292; +063C : 1291; +063D : 1291; +063E : 1292; +063F : 1292; +0640 : 1291; +0641 : 1290; +0642 : 1290; +0643 : 1290; +0644 : 1291; +0645 : 1291; +0646 : 1290; +0647 : 1290; +0648 : 1290; +0649 : 1290; +064A : 1290; +064B : 1289; +064C : 1287; +064D : 1289; +064E : 1289; +064F : 1289; +0650 : 1288; +0651 : 1288; +0652 : 1287; +0653 : 1288; +0654 : 1289; +0655 : 1288; +0656 : 1287; +0657 : 1286; +0658 : 1287; +0659 : 1287; +065A : 1286; +065B : 1286; +065C : 1286; +065D : 1287; +065E : 1286; +065F : 1286; +0660 : 1284; +0661 : 1285; +0662 : 1285; +0663 : 1287; +0664 : 1284; +0665 : 1284; +0666 : 1285; +0667 : 1285; +0668 : 1285; +0669 : 1283; +066A : 1283; +066B : 1283; +066C : 1284; +066D : 1284; +066E : 1282; +066F : 1282; +0670 : 1281; +0671 : 1283; +0672 : 1283; +0673 : 1282; +0674 : 1282; +0675 : 1281; +0676 : 1282; +0677 : 1282; +0678 : 1281; +0679 : 1281; +067A : 1281; +067B : 1280; +067C : 1282; +067D : 1281; +067E : 1281; +067F : 1281; +0680 : 1281; +0681 : 1280; +0682 : 1280; +0683 : 1280; +0684 : 1280; +0685 : 1279; +0686 : 1280; +0687 : 1278; +0688 : 1278; +0689 : 1280; +068A : 1279; +068B : 1279; +068C : 1279; +068D : 1278; +068E : 1278; +068F : 1278; +0690 : 1278; +0691 : 1278; +0692 : 1277; +0693 : 1277; +0694 : 1277; +0695 : 1277; +0696 : 1277; +0697 : 1276; +0698 : 1275; +0699 : 1276; +069A : 1276; +069B : 1276; +069C : 1275; +069D : 1275; +069E : 1275; +069F : 1276; +06A0 : 1275; +06A1 : 1275; +06A2 : 1275; +06A3 : 1276; +06A4 : 1276; +06A5 : 1275; +06A6 : 1273; +06A7 : 1274; +06A8 : 1275; +06A9 : 1275; +06AA : 1274; +06AB : 1273; +06AC : 1272; +06AD : 1274; +06AE : 1273; +06AF : 1272; +06B0 : 1272; +06B1 : 1271; +06B2 : 1273; +06B3 : 1273; +06B4 : 1272; +06B5 : 1272; +06B6 : 1272; +06B7 : 1272; +06B8 : 1272; +06B9 : 1271; +06BA : 1271; +06BB : 1271; +06BC : 1270; +06BD : 1271; +06BE : 1271; +06BF : 1271; +06C0 : 1269; +06C1 : 1270; +06C2 : 1270; +06C3 : 1269; +06C4 : 1268; +06C5 : 1268; +06C6 : 1269; +06C7 : 1270; +06C8 : 1269; +06C9 : 1268; +06CA : 1267; +06CB : 1268; +06CC : 1268; +06CD : 1269; +06CE : 1268; +06CF : 1267; +06D0 : 1268; +06D1 : 1267; +06D2 : 1267; +06D3 : 1267; +06D4 : 1267; +06D5 : 1267; +06D6 : 1268; +06D7 : 1268; +06D8 : 1266; +06D9 : 1266; +06DA : 1266; +06DB : 1266; +06DC : 1266; +06DD : 1266; +06DE : 1266; +06DF : 1266; +06E0 : 1266; +06E1 : 1266; +06E2 : 1265; +06E3 : 1263; +06E4 : 1265; +06E5 : 1266; +06E6 : 1265; +06E7 : 1265; +06E8 : 1264; +06E9 : 1264; +06EA : 1265; +06EB : 1264; +06EC : 1263; +06ED : 1263; +06EE : 1263; +06EF : 1263; +06F0 : 1263; +06F1 : 1262; +06F2 : 1262; +06F3 : 1263; +06F4 : 1263; +06F5 : 1263; +06F6 : 1261; +06F7 : 1261; +06F8 : 1261; +06F9 : 1261; +06FA : 1261; +06FB : 1262; +06FC : 1260; +06FD : 1260; +06FE : 1260; +06FF : 1261; +0700 : 1260; +0701 : 1260; +0702 : 1259; +0703 : 1261; +0704 : 1261; +0705 : 1259; +0706 : 1258; +0707 : 1259; +0708 : 1259; +0709 : 1260; +070A : 1257; +070B : 1257; +070C : 1258; +070D : 1258; +070E : 1258; +070F : 1258; +0710 : 1257; +0711 : 1257; +0712 : 1259; +0713 : 1258; +0714 : 1257; +0715 : 1257; +0716 : 1257; +0717 : 1258; +0718 : 1257; +0719 : 1256; +071A : 1256; +071B : 1255; +071C : 1256; +071D : 1257; +071E : 1255; +071F : 1255; +0720 : 1255; +0721 : 1256; +0722 : 1256; +0723 : 1256; +0724 : 1254; +0725 : 1254; +0726 : 1256; +0727 : 1255; +0728 : 1254; +0729 : 1253; +072A : 1254; +072B : 1254; +072C : 1255; +072D : 1253; +072E : 1253; +072F : 1253; +0730 : 1253; +0731 : 1254; +0732 : 1253; +0733 : 1252; +0734 : 1251; +0735 : 1252; +0736 : 1253; +0737 : 1252; +0738 : 1251; +0739 : 1251; +073A : 1252; +073B : 1253; +073C : 1252; +073D : 1251; +073E : 1250; +073F : 1251; +0740 : 1251; +0741 : 1251; +0742 : 1250; +0743 : 1249; +0744 : 1251; +0745 : 1252; +0746 : 1250; +0747 : 1249; +0748 : 1250; +0749 : 1250; +074A : 1250; +074B : 1249; +074C : 1249; +074D : 1248; +074E : 1249; +074F : 1249; +0750 : 1249; +0751 : 1248; +0752 : 1248; +0753 : 1248; +0754 : 1248; +0755 : 1248; +0756 : 1247; +0757 : 1247; +0758 : 1247; +0759 : 1248; +075A : 1248; +075B : 1247; +075C : 1247; +075D : 1247; +075E : 1246; +075F : 1247; +0760 : 1246; +0761 : 1246; +0762 : 1246; +0763 : 1246; +0764 : 1247; +0765 : 1246; +0766 : 1245; +0767 : 1245; +0768 : 1246; +0769 : 1246; +076A : 1246; +076B : 1244; +076C : 1245; +076D : 1245; +076E : 1246; +076F : 1245; +0770 : 1244; +0771 : 1244; +0772 : 1244; +0773 : 1245; +0774 : 1244; +0775 : 1243; +0776 : 1243; +0777 : 1244; +0778 : 1244; +0779 : 1243; +077A : 1242; +077B : 1243; +077C : 1243; +077D : 1243; +077E : 1242; +077F : 1242; +0780 : 1243; +0781 : 1243; +0782 : 1243; +0783 : 1242; +0784 : 1241; +0785 : 1242; +0786 : 1242; +0787 : 1241; +0788 : 1241; +0789 : 1241; +078A : 1241; +078B : 1241; +078C : 1241; +078D : 1241; +078E : 1240; +078F : 1240; +0790 : 1241; +0791 : 1240; +0792 : 1241; +0793 : 1239; +0794 : 1239; +0795 : 1240; +0796 : 1240; +0797 : 1239; +0798 : 1239; +0799 : 1239; +079A : 1238; +079B : 1239; +079C : 1238; +079D : 1238; +079E : 1239; +079F : 1238; +07A0 : 1239; +07A1 : 1237; +07A2 : 1236; +07A3 : 1237; +07A4 : 1237; +07A5 : 1238; +07A6 : 1238; +07A7 : 1236; +07A8 : 1237; +07A9 : 1237; +07AA : 1237; +07AB : 1237; +07AC : 1235; +07AD : 1236; +07AE : 1237; +07AF : 1236; +07B0 : 1236; +07B1 : 1236; +07B2 : 1235; +07B3 : 1236; +07B4 : 1236; +07B5 : 1236; +07B6 : 1234; +07B7 : 1235; +07B8 : 1235; +07B9 : 1235; +07BA : 1235; +07BB : 1235; +07BC : 1234; +07BD : 1234; +07BE : 1235; +07BF : 1234; +07C0 : 1234; +07C1 : 1234; +07C2 : 1233; +07C3 : 1235; +07C4 : 1234; +07C5 : 1234; +07C6 : 1233; +07C7 : 1234; +07C8 : 1234; +07C9 : 1234; +07CA : 1232; +07CB : 1232; +07CC : 1233; +07CD : 1233; +07CE : 1232; +07CF : 1231; +07D0 : 1231; +07D1 : 1232; +07D2 : 1232; +07D3 : 1231; +07D4 : 1231; +07D5 : 1231; +07D6 : 1231; +07D7 : 1231; +07D8 : 1231; +07D9 : 1230; +07DA : 1230; +07DB : 1230; +07DC : 1230; +07DD : 1230; +07DE : 1229; +07DF : 1229; +07E0 : 1229; +07E1 : 1231; +07E2 : 1231; +07E3 : 1229; +07E4 : 1227; +07E5 : 1229; +07E6 : 1228; +07E7 : 1229; +07E8 : 1229; +07E9 : 1229; +07EA : 1229; +07EB : 1229; +07EC : 1228; +07ED : 1227; +07EE : 1227; +07EF : 1228; +07F0 : 1228; +07F1 : 1228; +07F2 : 1227; +07F3 : 1227; +07F4 : 1227; +07F5 : 1228; +07F6 : 1228; +07F7 : 1227; +07F8 : 1227; +07F9 : 1227; +07FA : 1228; +07FB : 1227; +07FC : 1226; +07FD : 1226; +07FE : 1226; +07FF : 1227; +0800 : 1227; +0801 : 1225; +0802 : 1226; +0803 : 1226; +0804 : 1225; +0805 : 1226; +0806 : 1226; +0807 : 1225; +0808 : 1225; +0809 : 1225; +080A : 1226; +080B : 1225; +080C : 1224; +080D : 1225; +080E : 1225; +080F : 1225; +0810 : 1224; +0811 : 1224; +0812 : 1225; +0813 : 1224; +0814 : 1224; +0815 : 1223; +0816 : 1224; +0817 : 1223; +0818 : 1224; +0819 : 1224; +081A : 1223; +081B : 1222; +081C : 1222; +081D : 1223; +081E : 1223; +081F : 1222; +0820 : 1222; +0821 : 1222; +0822 : 1223; +0823 : 1223; +0824 : 1222; +0825 : 1221; +0826 : 1222; +0827 : 1223; +0828 : 1222; +0829 : 1222; +082A : 1221; +082B : 1221; +082C : 1220; +082D : 1221; +082E : 1221; +082F : 1220; +0830 : 1220; +0831 : 1221; +0832 : 1222; +0833 : 1220; +0834 : 1220; +0835 : 1220; +0836 : 1220; +0837 : 1221; +0838 : 1221; +0839 : 1220; +083A : 1219; +083B : 1219; +083C : 1220; +083D : 1219; +083E : 1219; +083F : 1218; +0840 : 1219; +0841 : 1221; +0842 : 1220; +0843 : 1218; +0844 : 1218; +0845 : 1219; +0846 : 1219; +0847 : 1219; +0848 : 1217; +0849 : 1217; +084A : 1217; +084B : 1218; +084C : 1218; +084D : 1217; +084E : 1217; +084F : 1219; +0850 : 1218; +0851 : 1218; +0852 : 1217; +0853 : 1217; +0854 : 1217; +0855 : 1218; +0856 : 1216; +0857 : 1216; +0858 : 1215; +0859 : 1216; +085A : 1217; +085B : 1217; +085C : 1216; +085D : 1215; +085E : 1215; +085F : 1216; +0860 : 1216; +0861 : 1215; +0862 : 1215; +0863 : 1215; +0864 : 1216; +0865 : 1216; +0866 : 1215; +0867 : 1214; +0868 : 1216; +0869 : 1216; +086A : 1215; +086B : 1215; +086C : 1215; +086D : 1215; +086E : 1215; +086F : 1215; +0870 : 1213; +0871 : 1214; +0872 : 1214; +0873 : 1214; +0874 : 1215; +0875 : 1214; +0876 : 1213; +0877 : 1213; +0878 : 1214; +0879 : 1214; +087A : 1214; +087B : 1212; +087C : 1212; +087D : 1215; +087E : 1214; +087F : 1212; +0880 : 1212; +0881 : 1212; +0882 : 1212; +0883 : 1213; +0884 : 1212; +0885 : 1211; +0886 : 1211; +0887 : 1212; +0888 : 1212; +0889 : 1211; +088A : 1211; +088B : 1211; +088C : 1211; +088D : 1211; +088E : 1211; +088F : 1210; +0890 : 1211; +0891 : 1212; +0892 : 1212; +0893 : 1211; +0894 : 1210; +0895 : 1210; +0896 : 1210; +0897 : 1211; +0898 : 1210; +0899 : 1209; +089A : 1209; +089B : 1210; +089C : 1211; +089D : 1210; +089E : 1208; +089F : 1209; +08A0 : 1210; +08A1 : 1211; +08A2 : 1210; +08A3 : 1208; +08A4 : 1208; +08A5 : 1208; +08A6 : 1209; +08A7 : 1207; +08A8 : 1207; +08A9 : 1208; +08AA : 1208; +08AB : 1209; +08AC : 1209; +08AD : 1208; +08AE : 1207; +08AF : 1208; +08B0 : 1209; +08B1 : 1207; +08B2 : 1206; +08B3 : 1208; +08B4 : 1208; +08B5 : 1208; +08B6 : 1208; +08B7 : 1207; +08B8 : 1207; +08B9 : 1207; +08BA : 1208; +08BB : 1207; +08BC : 1206; +08BD : 1206; +08BE : 1206; +08BF : 1207; +08C0 : 1207; +08C1 : 1205; +08C2 : 1205; +08C3 : 1205; +08C4 : 1206; +08C5 : 1205; +08C6 : 1205; +08C7 : 1205; +08C8 : 1206; +08C9 : 1206; +08CA : 1207; +08CB : 1205; +08CC : 1205; +08CD : 1205; +08CE : 1206; +08CF : 1205; +08D0 : 1205; +08D1 : 1203; +08D2 : 1205; +08D3 : 1206; +08D4 : 1204; +08D5 : 1204; +08D6 : 1204; +08D7 : 1204; +08D8 : 1205; +08D9 : 1205; +08DA : 1203; +08DB : 1203; +08DC : 1203; +08DD : 1204; +08DE : 1204; +08DF : 1203; +08E0 : 1202; +08E1 : 1203; +08E2 : 1205; +08E3 : 1204; +08E4 : 1203; +08E5 : 1202; +08E6 : 1203; +08E7 : 1203; +08E8 : 1202; +08E9 : 1201; +08EA : 1201; +08EB : 1202; +08EC : 1203; +08ED : 1203; +08EE : 1202; +08EF : 1201; +08F0 : 1203; +08F1 : 1203; +08F2 : 1201; +08F3 : 1201; +08F4 : 1201; +08F5 : 1201; +08F6 : 1202; +08F7 : 1202; +08F8 : 1201; +08F9 : 1201; +08FA : 1200; +08FB : 1202; +08FC : 1202; +08FD : 1200; +08FE : 1200; +08FF : 1200; +0900 : 1200; +0901 : 1201; +0902 : 1200; +0903 : 1199; +0904 : 1200; +0905 : 1200; +0906 : 1200; +0907 : 1200; +0908 : 1199; +0909 : 1200; +090A : 1200; +090B : 1200; +090C : 1199; +090D : 1199; +090E : 1199; +090F : 1200; +0910 : 1200; +0911 : 1199; +0912 : 1198; +0913 : 1197; +0914 : 1198; +0915 : 1200; +0916 : 1198; +0917 : 1198; +0918 : 1199; +0919 : 1198; +091A : 1198; +091B : 1198; +091C : 1197; +091D : 1197; +091E : 1198; +091F : 1198; +0920 : 1197; +0921 : 1196; +0922 : 1196; +0923 : 1197; +0924 : 1197; +0925 : 1196; +0926 : 1196; +0927 : 1196; +0928 : 1197; +0929 : 1197; +092A : 1196; +092B : 1196; +092C : 1196; +092D : 1197; +092E : 1197; +092F : 1196; +0930 : 1195; +0931 : 1196; +0932 : 1197; +0933 : 1197; +0934 : 1196; +0935 : 1195; +0936 : 1194; +0937 : 1197; +0938 : 1196; +0939 : 1195; +093A : 1194; +093B : 1195; +093C : 1195; +093D : 1195; +093E : 1195; +093F : 1193; +0940 : 1194; +0941 : 1195; +0942 : 1196; +0943 : 1195; +0944 : 1195; +0945 : 1194; +0946 : 1194; +0947 : 1195; +0948 : 1194; +0949 : 1194; +094A : 1194; +094B : 1194; +094C : 1194; +094D : 1194; +094E : 1194; +094F : 1192; +0950 : 1193; +0951 : 1194; +0952 : 1194; +0953 : 1192; +0954 : 1193; +0955 : 1194; +0956 : 1193; +0957 : 1193; +0958 : 1192; +0959 : 1192; +095A : 1192; +095B : 1194; +095C : 1193; +095D : 1192; +095E : 1192; +095F : 1192; +0960 : 1192; +0961 : 1192; +0962 : 1192; +0963 : 1191; +0964 : 1192; +0965 : 1193; +0966 : 1192; +0967 : 1191; +0968 : 1190; +0969 : 1191; +096A : 1191; +096B : 1192; +096C : 1191; +096D : 1190; +096E : 1190; +096F : 1191; +0970 : 1191; +0971 : 1190; +0972 : 1189; +0973 : 1191; +0974 : 1191; +0975 : 1190; +0976 : 1190; +0977 : 1190; +0978 : 1189; +0979 : 1190; +097A : 1189; +097B : 1189; +097C : 1189; +097D : 1190; +097E : 1190; +097F : 1189; +0980 : 1189; +0981 : 1188; +0982 : 1189; +0983 : 1190; +0984 : 1189; +0985 : 1189; +0986 : 1188; +0987 : 1189; +0988 : 1189; +0989 : 1188; +098A : 1188; +098B : 1189; +098C : 1188; +098D : 1189; +098E : 1188; +098F : 1188; +0990 : 1187; +0991 : 1188; +0992 : 1188; +0993 : 1188; +0994 : 1188; +0995 : 1187; +0996 : 1188; +0997 : 1188; +0998 : 1188; +0999 : 1187; +099A : 1187; +099B : 1187; +099C : 1187; +099D : 1187; +099E : 1187; +099F : 1186; +09A0 : 1186; +09A1 : 1188; +09A2 : 1188; +09A3 : 1186; +09A4 : 1186; +09A5 : 1186; +09A6 : 1187; +09A7 : 1187; +09A8 : 1187; +09A9 : 1185; +09AA : 1185; +09AB : 1186; +09AC : 1186; +09AD : 1186; +09AE : 1185; +09AF : 1185; +09B0 : 1186; +09B1 : 1186; +09B2 : 1186; +09B3 : 1186; +09B4 : 1185; +09B5 : 1186; +09B6 : 1186; +09B7 : 1185; +09B8 : 1184; +09B9 : 1185; +09BA : 1185; +09BB : 1186; +09BC : 1185; +09BD : 1185; +09BE : 1185; +09BF : 1185; +09C0 : 1185; +09C1 : 1184; +09C2 : 1184; +09C3 : 1184; +09C4 : 1184; +09C5 : 1185; +09C6 : 1184; +09C7 : 1184; +09C8 : 1183; +09C9 : 1184; +09CA : 1185; +09CB : 1184; +09CC : 1183; +09CD : 1184; +09CE : 1183; +09CF : 1184; +09D0 : 1183; +09D1 : 1183; +09D2 : 1183; +09D3 : 1183; +09D4 : 1183; +09D5 : 1183; +09D6 : 1182; +09D7 : 1182; +09D8 : 1182; +09D9 : 1183; +09DA : 1183; +09DB : 1182; +09DC : 1182; +09DD : 1182; +09DE : 1183; +09DF : 1182; +09E0 : 1181; +09E1 : 1181; +09E2 : 1182; +09E3 : 1183; +09E4 : 1182; +09E5 : 1181; +09E6 : 1181; +09E7 : 1181; +09E8 : 1182; +09E9 : 1182; +09EA : 1180; +09EB : 1181; +09EC : 1182; +09ED : 1181; +09EE : 1181; +09EF : 1181; +09F0 : 1181; +09F1 : 1181; +09F2 : 1181; +09F3 : 1181; +09F4 : 1181; +09F5 : 1180; +09F6 : 1181; +09F7 : 1182; +09F8 : 1181; +09F9 : 1180; +09FA : 1180; +09FB : 1181; +09FC : 1181; +09FD : 1182; +09FE : 1179; +09FF : 1180; +END; Index: /sandbox/MultiChannelUSB/test.v =================================================================== --- /sandbox/MultiChannelUSB/test.v (revision 106) +++ /sandbox/MultiChannelUSB/test.v (revision 107) @@ -1,418 +1,61 @@ module test ( - input wire clk, + input wire clock, output wire [11:0] data ); - reg [11:0] int_data; - reg [15:0] counter; -// reg [5:0] counter; - reg [5:0] state; + reg [11:0] int_addr; - always @(posedge clk) + always @(posedge clock) begin - case (state) -/* - 0: - begin - int_data <= 12'd0; - state <= 6'd1; - end - - 1: - begin - int_data <= 12'd1024; - state <= 6'd2; - end + if (int_addr == 12'd2559) + begin + int_addr <= 12'd0; + end + else + begin + int_addr <= int_addr + 12'd1; + end - 2: - begin - int_data <= 12'd2048; - state <= 6'd3; - end - - 3: - begin - int_data <= 12'd3072; - state <= 6'd4; - end - - 4: - begin - int_data <= 12'd4095; - state <= 6'd5; - end - - 5: - begin - int_data <= 12'd3072; - state <= 6'd6; - end - - 6: - begin - int_data <= 12'd2048; - state <= 6'd7; - end - - 7: - begin - int_data <= 12'd1024; - state <= 6'd8; - end - - 8: - begin - int_data <= 12'd0; - counter <= counter + 6'd1; - if (&counter) - begin - state <= 6'd0; - end - end -*/ - - 6'd0: - begin - int_data <= 12'h030; - state <= 6'd1; - end - - 6'd1: - begin - int_data <= 12'h034; - state <= 6'd2; - end - - 6'd2: - begin - int_data <= 12'h081; - state <= 6'd3; - end - - 6'd3: - begin - int_data <= 12'h0f5; - state <= 6'd4; - end - - 6'd4: - begin - int_data <= 12'h10a; - state <= 6'd5; - end - - 6'd5: - begin - int_data <= 12'h11a; - state <= 6'd6; - end - - 6'd6: - begin - int_data <= 12'h124; - state <= 6'd7; - end - - 6'd7: - begin - int_data <= 12'h124; - state <= 6'd8; - end - - 6'd8: - begin - int_data <= 12'h12b; - state <= 6'd9; - end - - 6'd9: - begin - int_data <= 12'h12a; - state <= 6'd10; - end - - 6'd10: - begin - int_data <= 12'h12a; - state <= 6'd11; - end - - 6'd11: - begin - int_data <= 12'h12b; - state <= 6'd12; - end - - 6'd12: - begin - int_data <= 12'h12a; - state <= 6'd13; - end - - 6'd13: - begin - int_data <= 12'h12e; - state <= 6'd14; - end - - 6'd14: - begin - int_data <= 12'h12b; - state <= 6'd15; - end - - 6'd15: - begin - int_data <= 12'h12b; - state <= 6'd16; - end - - 6'd16: - begin - int_data <= 12'h12e; - state <= 6'd17; - end - - 6'd17: - begin - int_data <= 12'h12b; - state <= 6'd18; - end - - 6'd18: - begin - int_data <= 12'h12a; - state <= 6'd19; - end - - 6'd19: - begin - int_data <= 12'h12e; - state <= 6'd20; - end - - 6'd20: - begin - int_data <= 12'h12b; - state <= 6'd21; - end - - 6'd21: - begin - int_data <= 12'h12e; - state <= 6'd22; - end - - 6'd22: - begin - int_data <= 12'h12f; - state <= 6'd23; - end - - 6'd23: - begin - int_data <= 12'h12f; - state <= 6'd24; - end - - 6'd24: - begin - int_data <= 12'h12b; - state <= 6'd25; - end - - 6'd25: - begin - int_data <= 12'h12b; - state <= 6'd26; - end - - 6'd26: - begin - int_data <= 12'h12b; - state <= 6'd27; - end - - 6'd27: - begin - int_data <= 12'h12e; - state <= 6'd28; - end - - 6'd28: - begin - int_data <= 12'h12e; - state <= 6'd29; - end - - 6'd29: - begin - int_data <= 12'h12e; - state <= 6'd30; - end - - 6'd30: - begin - int_data <= 12'h12e; - state <= 6'd31; - end - - 6'd31: - begin - int_data <= 12'h12b; - state <= 6'd32; - end - - 6'd32: - begin - int_data <= 12'h12b; - state <= 6'd33; - end - - 6'd33: - begin - int_data <= 12'h12b; - state <= 6'd34; - end - - 6'd34: - begin - int_data <= 12'h12e; - state <= 6'd35; - end - - 6'd35: - begin - int_data <= 12'h12e; - state <= 6'd36; - end - - 6'd36: - begin - int_data <= 12'h12e; - state <= 6'd37; - end - - 6'd37: - begin - int_data <= 12'h12e; - state <= 6'd38; - end - - 6'd38: - begin - int_data <= 12'h12f; - state <= 6'd39; - end - - 6'd39: - begin - int_data <= 12'h12b; - state <= 6'd40; - end - - 6'd40: - begin - int_data <= 12'h12e; - state <= 6'd41; - end - - 6'd41: - begin - int_data <= 12'h12f; - state <= 6'd42; - end - - 6'd42: - begin - int_data <= 12'h0fb; - state <= 6'd43; - end - - 6'd43: - begin - int_data <= 12'h07e; - state <= 6'd44; - end - - 6'd44: - begin - int_data <= 12'h070; - state <= 6'd45; - end - - 6'd45: - begin - int_data <= 12'h05a; - state <= 6'd46; - end - - 6'd46: - begin - int_data <= 12'h045; - state <= 6'd47; - end - - 6'd47: - begin - int_data <= 12'h03f; - state <= 6'd48; - end - - 6'd48: - begin - int_data <= 12'h03b; - state <= 6'd49; - end - - 6'd49: - begin - int_data <= 12'h034; - state <= 6'd50; - end - - 6'd50: - begin - int_data <= 12'h035; - state <= 6'd51; - end - - 6'd51: - begin - int_data <= 12'h034; - state <= 6'd52; - end - - 6'd52: - begin - int_data <= 12'h034; - state <= 6'd53; - end - - 6'd53: - begin - int_data <= 12'h030; - state <= 6'd54; - end - - 6'd54: - begin - int_data <= 12'h030; - counter <= counter + 16'd1; - if (&counter) - begin - state <= 6'd0; - end - end - - default: - begin - state <= 6'd0; - end - endcase end - assign data = int_data; + altsyncram #( + .address_aclr_a("NONE"), + .clock_enable_input_a("BYPASS"), + .clock_enable_output_a("BYPASS"), + .init_file("test_mwd.mif"), + .intended_device_family("Cyclone III"), + .lpm_hint("ENABLE_RUNTIME_MOD=NO"), + .lpm_type("altsyncram"), + .numwords_a(2560), + .operation_mode("ROM"), + .outdata_aclr_a("NONE"), + .outdata_reg_a("CLOCK0"), + .widthad_a(12), + .width_a(12), + .width_byteena_a(1)) test_rom_unit ( + .clock0(clock), + .address_a(int_addr), + .q_a(data), + .aclr0(1'b0), + .aclr1(1'b0), + .address_b(1'b1), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clock1(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .data_a({12{1'b1}}), + .data_b(1'b1), + .eccstatus(), + .q_b(), + .rden_a(1'b1), + .rden_b(1'b1), + .wren_a(1'b0), + .wren_b(1'b0)); endmodule Index: ndbox/MultiChannelUSB/test_pll.v =================================================================== --- /sandbox/MultiChannelUSB/test_pll.v (revision 106) +++ (revision ) @@ -1,145 +1,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: test_pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 9.0 Build 132 02/25/2009 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2009 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module test_pll ( - inclk0, - c0); - - input inclk0; - output c0; - - wire [4:0] sub_wire0; - wire [0:0] sub_wire4 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire sub_wire2 = inclk0; - wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; - - altpll altpll_component ( - .inclk (sub_wire3), - .clk (sub_wire0), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .locked (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 5, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 2, - altpll_component.clk0_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 20000, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_UNUSED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_UNUSED", - altpll_component.port_clk2 = "PORT_UNUSED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.width_clock = 5; - -endmodule Index: ndbox/MultiChannelUSB/uwt_bior31.v =================================================================== --- /sandbox/MultiChannelUSB/uwt_bior31.v (revision 106) +++ (revision ) @@ -1,116 +1,0 @@ -module uwt_bior31 - #( - parameter L = 1 // transform level - ) - ( - input wire clock, frame, reset, - input wire [31:0] x, - output wire [31:0] d, - output wire [31:0] a, - output wire [31:0] peak, - output wire [1:0] flag - ); - - localparam index1 = 1 << (L - 1); - localparam index2 = 2 << (L - 1); - localparam index3 = 3 << (L - 1); - localparam index4 = index3 + 1; - localparam peak_index = ((index3 + 1) >> 1) + 2; - localparam peak_shift = ((L - 1) << 1) + (L - 1); - localparam zero = 32'h80000000; - - // Tapped delay line - reg [31:0] tap [index4:0]; - - reg [31:0] d_reg, d_next; - reg [31:0] a_reg, a_next; - reg [31:0] peak_reg, peak_next; - - reg [31:0] tmp1_reg, tmp1_next; - reg [31:0] tmp2_reg, tmp2_next; - - reg less_reg, less_next; - reg more_reg, more_next; - - reg [1:0] flag_reg; - - integer i; - - always @(posedge clock) - begin - if (reset) - begin - d_reg <= 0; - a_reg <= 0; - peak_reg <= 0; - flag_reg <= 0; - tmp1_reg <= 0; - tmp2_reg <= 0; - less_reg <= 1'b0; - more_reg <= 1'b0; - - for(i = 0; i <= index4; i = i + 1) - begin - tap[i] <= 0; - end - end - else if (frame) - begin - d_reg <= d_next; - a_reg <= a_next; - peak_reg <= peak_next; - - tmp1_reg <= tmp1_next; - tmp2_reg <= tmp2_next; - less_reg <= less_next; - more_reg <= more_next; - - flag_reg[0] <= (more_reg) & (~more_next); - flag_reg[1] <= (less_reg) & (~less_next); - - // Tapped delay line: shift one - for(i = 0; i < index4; i = i + 1) - begin - tap[i+1] <= tap[i]; - end - - // Input in register 0 - tap[0] <= x; - end - end - - always @* - begin - // Compute d and a with the filter coefficients. - // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1] - - tmp1_next = tap[index3] + {tap[index2][30:0], 1'b0} + tap[index2]; - tmp2_next = {tap[index1][30:0], 1'b0} + tap[index1] + tap[0]; - - d_next = zero - tmp1_reg + tmp2_reg; - a_next = tmp1_reg + tmp2_reg; - - more_next = (d_reg > zero); - less_next = (d_reg < zero); - -/* - d_next = zero - (tap[index3]) - - (tap[index2] << 1) - tap[index2] - + (tap[index1] << 1) + tap[index1] - + (tap[0]); - - a_next = (tap[index3]) - + {tap[index2] << 1} + tap[index2] - + (tap[index1] << 1) + tap[index1] - + (tap[0]); -*/ - peak_next = (tap[peak_index] >> peak_shift); - end - - // output logic - assign d = d_reg; - assign a = a_reg; - assign peak = peak_reg; - assign flag = flag_reg; - -endmodule