Index: sandbox/MultiChannelUSB/Paella.v
===================================================================
--- sandbox/MultiChannelUSB/Paella.v	(revision 106)
+++ sandbox/MultiChannelUSB/Paella.v	(revision 107)
@@ -83,5 +83,5 @@
 	usb_fifo usb_unit
 	(
-		.usb_clk(USB_IFCLK),
+		.usb_clock(USB_IFCLK),
 		.usb_data(USB_PB),
 		.usb_full(~USB_FLAGB),
@@ -93,5 +93,5 @@
 		.usb_addr(usb_addr),
 
-		.clk(sys_clock),
+		.clock(sys_clock),
 
 		.tx_full(usb_tx_full),
@@ -104,4 +104,14 @@
 	);
 		
+	wire	[11:0]	osc_mux_data [4:0];
+
+	wire	[11:0]	trg_mux_data;
+	wire			trg_flag;
+
+	wire	[2:0]	coi_data;
+	wire			coi_flag;
+
+	wire	[7*12-1:0]	int_mux_data [N-1:0];
+
 	wire			ana_dead [N-1:0];
 	wire			ana_good [N-1:0];
@@ -109,30 +119,25 @@
 	wire	[11:0]	ana_base [N-1:0];
 
+	wire			amp_good [N-1:0];
+	wire	[11:0]	amp_data [N-1:0];
+
 	wire			cnt_good [N-1:0];
-
-	wire	[11:0]	osc_mux_data [N-1:0];
-
-	wire	[11:0]	trg_mux_data;
-	wire			trg_flag;
-
-	wire	[83:0]	int_mux_data [N-1:0];
+	wire	[15:0]	cnt_bits_wire;
 
 	wire			sys_clock, sys_frame;
 
-	wire 	[11:0]	adc_data [N-1:0];
-    wire	[11:0]	int_data [N-1:0];
+    wire	[11:0]	adc_data [N-1:0];
     wire	[11:0]	sys_data [N-1:0];
+	wire	[11:0]	tst_data;
+
     wire	[11:0]	cmp_data;
-	wire	[11:0]	nowhere;
+    wire	[11:0]	del_data;
 
 	wire 	[31:0]	uwt_d1 [N-1:0];
 	wire 	[31:0]	uwt_a1 [N-1:0];
-	wire 	[31:0]	uwt_peak1 [N-1:0];
 	wire 	[31:0]	uwt_d2 [N-1:0];
 	wire 	[31:0]	uwt_a2 [N-1:0];
-	wire 	[31:0]	uwt_peak2 [N-1:0];
 	wire 	[31:0]	uwt_d3 [N-1:0];
 	wire 	[31:0]	uwt_a3 [N-1:0];
-	wire 	[31:0]	uwt_peak3 [N-1:0];
 
 	wire 	[1:0]	uwt_flag1 [N-1:0];
@@ -140,22 +145,11 @@
 	wire 	[1:0]	uwt_flag3 [N-1:0];
 	
+	wire	[11:0]	cic_mux_data;
+	wire	[13:0]	cic_lfsr;
+	wire	[24:0]	cic_data1 [N-1:0];
+	wire	[24:0]	cic_data2 [N-1:0];
+	wire	[24:0]	cic_data3 [N-1:0];
+
 	wire			i2c_reset;
-
-/*
-	adc_para adc_para_unit (
-		.lvds_dco(ADC_DCO),
-		.lvds_fco(ADC_FCO),
-		.para_good(CON_CCLK[0]),
- 		.para_data(CON_C[11:0]),
-		.adc_data(adc_data[2]));
-*/
- 
-	wire			adc_pll_clk;
-
-/*
-	adc_pll adc_pll_unit(
-		.inclk0(ADC_FCO),
-		.c0(adc_pll_clk));
-*/
 
 	sys_pll sys_pll_unit(
@@ -164,44 +158,37 @@
 
 	test test_unit(
-		.clk(ADC_FCO),
-		.data(adc_data[2]));
-//		.data(nowhere));
+		.clock(ADC_FCO),
+		.data(tst_data));
 
 	adc_lvds #(
 		.size(3),
 		.width(12)) adc_lvds_unit (
+		.clock(sys_clock),
 		.lvds_dco(ADC_DCO),
-//		.lvds_dco(adc_pll_clk),
 		.lvds_fco(ADC_FCO),
-		.lvds_d(ADC_D[2:0]),
-//		.adc_data({	adc_data[2],
-		.adc_data({	nowhere,
-					adc_data[1],
-					adc_data[0] }));
-
-/*					
-	assign			cmp_data = CON_B[11:0];
-	assign			sys_clock = ADC_DCO;
-	assign			sys_frame = ADC_FCO;
-*/
+		.lvds_d(ADC_D),
+		.test(tst_data),
+		.trig({CON_B[9:0], TRG[1:0]}),
+		.adc_frame(sys_frame),
+		.adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
 
 	wire	[15:0]	cfg_bits [31:0];
 	wire	[511:0]	int_cfg_bits;
 
-	wire	[31:0]	cfg_mux_selector;
+	wire	[39:0]	cfg_mux_selector;
 
 	wire 			cfg_reset;
 
-	wire 	[8:0]	bus_ssel;
+	wire 	[11:0]	bus_ssel;
 	wire			bus_wren;
 	wire	[31:0]	bus_addr;
 	wire	[15:0]	bus_mosi;
-	wire 	[15:0]	bus_miso [7:0];
-	wire 	[8:0]	bus_busy;
+	wire 	[15:0]	bus_miso [10:0];
+	wire 	[11:0]	bus_busy;
 
 	wire 	[15:0]	mrg_bus_miso;
 	wire 			mrg_bus_busy;
 
-	wire 	[127:0]	int_bus_miso;
+	wire 	[11*16-1:0]	int_bus_miso;
 
 	genvar j;
@@ -229,31 +216,35 @@
 		begin : MUX_DATA
 			assign int_mux_data[j] = {
-				{ana_good[j], 11'd0},
-				ana_data[j],
-				ana_base[j],
-				uwt_a3[j][20:9],
-				uwt_a2[j][17:6],
-				uwt_a1[j][14:3],
+				{4'd0, uwt_flag3[j][1], 7'd0},
+				{4'd0, uwt_flag3[j][0], 7'd0},
+				{12'd0},
+//				{4'd0, amp_good[j], 7'd0},
+				cic_data1[j][14:3],
+				cic_data2[j][18:7],
+				cic_data3[j][22:11],
+//				{8'd0, cic_lfsr[3:0]},
+//				{8'd0, cic_lfsr[5:2]},
+//				uwt_a3[j][20:9],
 				sys_data[j]};
 		end
 	endgenerate
 
-	assign cfg_mux_selector = {cfg_bits[3], cfg_bits[2]};
+	assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
 
 	lpm_mux #(
-		.lpm_size(21),
+		.lpm_size(7*3),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(12),
 		.lpm_widths(5)) trg_mux_unit (
-		.sel(cfg_mux_selector[28:24]),
+		.sel(cfg_bits[4][12:8]),
 		.data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
 		.result(trg_mux_data));
 
 	generate
-		for (j = 0; j < 3; j = j + 1)
+		for (j = 0; j < 5; j = j + 1)
 		begin : OSC_CHAIN
 		
 			lpm_mux #(
-				.lpm_size(21),
+				.lpm_size(7*3),
 				.lpm_type("LPM_MUX"),
 				.lpm_width(12),
@@ -278,7 +269,7 @@
 		.frame(sys_frame),
 		.reset(cfg_bits[0][1]),
-		.cfg_data(cfg_bits[4][0]),
+		.cfg_data(cfg_bits[5][12]),
 		.trg_flag(trg_flag),
-		.osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+		.osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
 		.ram_wren(RAM_WE),
 		.ram_addr(RAM_ADDR),
@@ -291,18 +282,18 @@
 		.bus_busy(bus_busy[1]));
 
-
-	adc_fifo #(.W(48)) adc_fifo_unit (
-		.adc_clock(ADC_FCO),
-		.adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
-		.sys_clock(sys_clock),
-		.sys_frame(sys_frame),
-		.sys_data({cmp_data, int_data[2], int_data[1], int_data[0]}));
-
-
+	cic1 #(.size(3), .width(12)) cic3_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(1'b0),
+		.inp_data({sys_data[2], sys_data[1], sys_data[0]}),
+		.out_data2({cic_data2[2], cic_data2[1], cic_data2[0]}),
+		.out_data3({cic_data3[2], cic_data3[1], cic_data3[0]}),
+		.out_data({cic_data1[2], cic_data1[1], cic_data1[0]}));
+	
 	generate
 		for (j = 0; j < 3; j = j + 1)
 		begin : MCA_CHAIN
 
-			assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]);
+			assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
 
 			uwt_bior31 #(.L(1)) uwt_1_unit (
@@ -313,5 +304,4 @@
 				.d(uwt_d1[j]),
 				.a(uwt_a1[j]),
-				.peak(uwt_peak1[j]),
 				.flag(uwt_flag1[j]));
 		
@@ -323,5 +313,4 @@
 				.d(uwt_d2[j]),
 				.a(uwt_a2[j]),
-				.peak(uwt_peak2[j]),
 				.flag(uwt_flag2[j]));
 		
@@ -333,5 +322,4 @@
 				.d(uwt_d3[j]),
 				.a(uwt_a3[j]),
-				.peak(uwt_peak3[j]),
 				.flag(uwt_flag3[j]));
 	
@@ -341,6 +329,6 @@
 				.reset(cfg_bits[0][2+j]),
 				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
-				.uwt_flag(uwt_flag3[j]),
-				.uwt_data(uwt_peak3[j]),
+				.uwt_flag(uwt_flag2[j]),
+				.uwt_data(uwt_a2[j][17:6]),
 				.ana_dead(ana_dead[j]),
 				.ana_good(ana_good[j]),
@@ -348,32 +336,49 @@
 				.ana_base(ana_base[j]));
 
-			histogram histogram_unit (
+			amplitude amplitude_unit (
 				.clock(sys_clock),
 				.frame(sys_frame),
-				.reset(cfg_bits[0][5+j]),
-				.hst_good((ana_good[j]) & (cnt_good[j])),
-				.hst_data(ana_data[j]),
-				.bus_ssel(bus_ssel[2+j]),
-				.bus_wren(bus_wren),
-				.bus_addr(bus_addr[12:0]),
-				.bus_mosi(bus_mosi),
-				.bus_miso(bus_miso[2+j]),
-				.bus_busy(bus_busy[2+j]));
-
-			counter counter_unit (
-				.clock(sys_clock),
-				.frame((sys_frame) & (~ana_dead[j])),
-				.reset(cfg_bits[0][8+j]),
-				.cfg_data(cfg_bits[12+j]),
-				.bus_ssel(bus_ssel[5+j]),
-				.bus_wren(bus_wren),
-				.bus_addr(bus_addr[1:0]),
-				.bus_mosi(bus_mosi),
-				.bus_miso(bus_miso[5+j]),
-				.bus_busy(bus_busy[5+j]),
-				.cnt_good(cnt_good[j]));
-
+				.reset(cfg_bits[0][2+j]),
+				.cfg_data(cfg_bits[12][11:0]),
+//				.cfg_data(10'd5),
+				.uwt_flag(uwt_flag3[j]),
+				.uwt_data(uwt_a3[j][20:9]),
+				.amp_good(amp_good[j]),
+				.amp_data(amp_data[j]));
 		end
 	endgenerate
+
+	histogram32 histogram32_unit (
+		.clock(sys_clock),
+		.frame(sys_frame),
+		.reset(cfg_bits[0][5]),
+		.hst_good((ana_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
+		.hst_data(ana_data[0]),
+/*
+		.hst_good((amp_good[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
+		.hst_data(amp_data[j]),
+*/
+		.bus_ssel(bus_ssel[2]),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr[12:0]),
+		.bus_mosi(bus_mosi),
+		.bus_miso(bus_miso[2]),
+		.bus_busy(bus_busy[2]));
+
+	counter hst_counter_unit (
+		.clock(sys_clock),
+		.frame((sys_frame) & (~ana_dead[0])),
+//		.frame(sys_frame),
+		.reset(cfg_bits[0][8]),
+		.setup(cfg_bits[13][0]),
+		.count(cfg_bits[13][1]),
+		.bus_ssel(bus_ssel[5]),
+		.bus_wren(bus_wren),
+		.bus_addr(bus_addr[1:0]),
+		.bus_mosi(bus_mosi),
+		.bus_miso(bus_miso[5]),
+		.bus_busy(bus_busy[5]),
+		.cnt_good(cnt_good[0]));
+
 
 	i2c_fifo i2c_unit(
@@ -390,11 +395,11 @@
 		.i2c_scl(I2C_SDA),
 		
-		.bus_ssel(bus_ssel[8]),
-		.bus_wren(bus_wren),
-		.bus_mosi(bus_mosi),
-		.bus_busy(bus_busy[8]));
+		.bus_ssel(bus_ssel[11]),
+		.bus_wren(bus_wren),
+		.bus_mosi(bus_mosi),
+		.bus_busy(bus_busy[11]));
 
 	generate
-		for (j = 0; j < 8; j = j + 1)
+		for (j = 0; j < 11; j = j + 1)
 		begin : BUS_OUTPUT
 			assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
@@ -403,14 +408,14 @@
 
 	lpm_mux #(
-		.lpm_size(8),
+		.lpm_size(11),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(16),
-		.lpm_widths(3)) bus_miso_mux_unit (
-		.sel(bus_addr[30:28]),
+		.lpm_widths(4)) bus_miso_mux_unit (
+		.sel(bus_addr[31:28]),
 		.data(int_bus_miso),
 		.result(mrg_bus_miso));
 
 	lpm_mux #(
-		.lpm_size(9),
+		.lpm_size(12),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(1),
@@ -420,23 +425,11 @@
 		.result(mrg_bus_busy));
 
-/*
-	lpm_or #(
-		.lpm_size(6),
-		.lpm_type("LPM_OR"),
-		.lpm_width(16)) bus_miso_or_unit (
-		.data(int_bus_miso),
-		.result(mrg_bus_miso));
-*/
-
 	lpm_decode #(
-		.lpm_decodes(9),
+		.lpm_decodes(12),
 		.lpm_type("LPM_DECODE"),
 		.lpm_width(4)) lpm_decode_unit (
 		.data(bus_addr[31:28]),
-		.eq(bus_ssel),
-		.aclr(),
-		.clken(),
-		.clock(),
-		.enable());
+		.eq(bus_ssel));
+
 
 	control control_unit (
