Index: sandbox/MultiChannelUSB/Paella.cof
===================================================================
--- sandbox/MultiChannelUSB/Paella.cof (revision 106)
+++ sandbox/MultiChannelUSB/Paella.cof (revision 106)
@@ -0,0 +1,18 @@
+
+
+ EPCS16
+ EP3C25
+ Paella.jic
+ 1
+ 1
+ 7
+
+ 1
+
+ Paella.sof
+
+
+ 4
+
+
+
Index: sandbox/MultiChannelUSB/Paella.dpf
===================================================================
--- sandbox/MultiChannelUSB/Paella.dpf (revision 106)
+++ sandbox/MultiChannelUSB/Paella.dpf (revision 106)
@@ -0,0 +1,34 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: sandbox/MultiChannelUSB/Paella.qpf
===================================================================
--- sandbox/MultiChannelUSB/Paella.qpf (revision 106)
+++ sandbox/MultiChannelUSB/Paella.qpf (revision 106)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "14:14:14 August 28, 2009"
+
+# Revisions
+
+PROJECT_REVISION = "Paella"
Index: sandbox/MultiChannelUSB/Paella.qsf
===================================================================
--- sandbox/MultiChannelUSB/Paella.qsf (revision 106)
+++ sandbox/MultiChannelUSB/Paella.qsf (revision 106)
@@ -0,0 +1,325 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# Paella_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY Paella
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 AUGUST 28, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 9.0
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name MISC_FILE Paella.dpf
+set_global_assignment -name VERILOG_FILE Paella.v
+set_global_assignment -name VERILOG_FILE adc_fifo.v
+set_global_assignment -name VERILOG_FILE adc_lvds.v
+set_global_assignment -name VERILOG_FILE adc_para.v
+set_global_assignment -name VERILOG_FILE adc_pll.v
+set_global_assignment -name VERILOG_FILE control.v
+set_global_assignment -name VERILOG_FILE analyser.v
+set_global_assignment -name VERILOG_FILE counter.v
+set_global_assignment -name VERILOG_FILE histogram.v
+set_global_assignment -name VERILOG_FILE trigger.v
+set_global_assignment -name VERILOG_FILE oscilloscope.v
+set_global_assignment -name VERILOG_FILE configuration.v
+set_global_assignment -name VERILOG_FILE usb_fifo.v
+set_global_assignment -name VERILOG_FILE i2c_fifo.v
+set_global_assignment -name VERILOG_FILE uwt_bior31.v
+set_global_assignment -name VERILOG_FILE test.v
+set_global_assignment -name VERILOG_FILE test_pll.v
+set_global_assignment -name VERILOG_FILE sys_pll.v
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 4
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 5
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
+set_location_assignment PIN_21 -to LED
+set_location_assignment PIN_33 -to CLK_50MHz
+set_location_assignment PIN_37 -to USB_PA7
+set_location_assignment PIN_38 -to USB_PA6
+set_location_assignment PIN_39 -to USB_PA5
+set_location_assignment PIN_41 -to USB_PA4
+set_location_assignment PIN_43 -to USB_PA3
+set_location_assignment PIN_44 -to USB_PA2
+set_location_assignment PIN_45 -to USB_PA1
+set_location_assignment PIN_46 -to USB_PA0
+set_location_assignment PIN_49 -to USB_FLAGC
+set_location_assignment PIN_50 -to USB_FLAGB
+set_location_assignment PIN_51 -to USB_FLAGA
+set_location_assignment PIN_52 -to USB_PB[7]
+set_location_assignment PIN_55 -to USB_PB[6]
+set_location_assignment PIN_56 -to USB_PB[5]
+set_location_assignment PIN_57 -to USB_PB[4]
+set_location_assignment PIN_63 -to USB_SLRD
+set_location_assignment PIN_64 -to USB_SLWR
+set_location_assignment PIN_65 -to USB_IFCLK
+set_location_assignment PIN_68 -to USB_PB[0]
+set_location_assignment PIN_69 -to USB_PB[1]
+set_location_assignment PIN_70 -to USB_PB[2]
+set_location_assignment PIN_71 -to USB_PB[3]
+set_location_assignment PIN_72 -to I2C_SDA
+set_location_assignment PIN_73 -to I2C_SCL
+set_location_assignment PIN_76 -to CON_A[0]
+set_location_assignment PIN_78 -to CON_A[1]
+set_location_assignment PIN_80 -to CON_A[2]
+set_location_assignment PIN_81 -to CON_A[3]
+set_location_assignment PIN_82 -to CON_A[4]
+set_location_assignment PIN_83 -to TRG[0]
+set_location_assignment PIN_84 -to TRG[1]
+set_location_assignment PIN_87 -to TRG[2]
+set_location_assignment PIN_88 -to TRG[3]
+set_location_assignment PIN_91 -to ADC_DCO
+set_location_assignment PIN_92 -to "ADC_DCO(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_DCO
+set_location_assignment PIN_93 -to ADC_FCO
+set_location_assignment PIN_94 -to "ADC_FCO(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
+set_location_assignment PIN_98 -to ADC_D[0]
+set_location_assignment PIN_99 -to "ADC_D[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0]
+set_location_assignment PIN_108 -to ADC_D[1]
+set_location_assignment PIN_109 -to "ADC_D[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1]
+set_location_assignment PIN_119 -to ADC_D[2]
+set_location_assignment PIN_120 -to "ADC_D[2](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2]
+set_location_assignment PIN_126 -to CON_B[0]
+set_location_assignment PIN_127 -to CON_B[1]
+set_location_assignment PIN_128 -to CON_B[2]
+set_location_assignment PIN_131 -to CON_B[3]
+set_location_assignment PIN_132 -to CON_B[4]
+set_location_assignment PIN_133 -to CON_B[5]
+set_location_assignment PIN_134 -to CON_B[6]
+set_location_assignment PIN_135 -to CON_B[7]
+set_location_assignment PIN_137 -to CON_B[8]
+set_location_assignment PIN_139 -to CON_B[9]
+set_location_assignment PIN_142 -to CON_B[10]
+set_location_assignment PIN_143 -to CON_B[11]
+set_location_assignment PIN_144 -to CON_B[12]
+set_location_assignment PIN_145 -to CON_B[13]
+set_location_assignment PIN_146 -to CON_B[14]
+set_location_assignment PIN_147 -to CON_B[15]
+set_location_assignment PIN_149 -to CON_BCLK[0]
+set_location_assignment PIN_150 -to CON_BCLK[1]
+set_location_assignment PIN_151 -to CON_CCLK[0]
+set_location_assignment PIN_152 -to CON_CCLK[1]
+set_location_assignment PIN_159 -to CON_C[0]
+set_location_assignment PIN_160 -to CON_C[1]
+set_location_assignment PIN_161 -to CON_C[2]
+set_location_assignment PIN_162 -to CON_C[3]
+set_location_assignment PIN_164 -to CON_C[4]
+set_location_assignment PIN_166 -to CON_C[5]
+set_location_assignment PIN_167 -to CON_C[6]
+set_location_assignment PIN_168 -to CON_C[7]
+set_location_assignment PIN_169 -to CON_C[8]
+set_location_assignment PIN_171 -to CON_C[9]
+set_location_assignment PIN_173 -to CON_C[10]
+set_location_assignment PIN_176 -to CON_C[11]
+set_location_assignment PIN_177 -to CON_C[12]
+set_location_assignment PIN_181 -to RAM_DQB[7]
+set_location_assignment PIN_182 -to RAM_ADDR[6]
+set_location_assignment PIN_183 -to RAM_ADDR[7]
+set_location_assignment PIN_184 -to RAM_CE1
+set_location_assignment PIN_186 -to RAM_CLK
+set_location_assignment PIN_187 -to RAM_WE
+set_location_assignment PIN_188 -to RAM_ADDR[8]
+set_location_assignment PIN_189 -to RAM_ADDR[9]
+set_location_assignment PIN_194 -to RAM_ADDR[10]
+set_location_assignment PIN_195 -to RAM_ADDR[11]
+set_location_assignment PIN_196 -to RAM_ADDR[12]
+set_location_assignment PIN_197 -to RAM_DQAP
+set_location_assignment PIN_200 -to RAM_DQA[0]
+set_location_assignment PIN_201 -to RAM_DQA[1]
+set_location_assignment PIN_202 -to RAM_DQA[2]
+set_location_assignment PIN_203 -to RAM_DQA[3]
+set_location_assignment PIN_207 -to RAM_DQA[4]
+set_location_assignment PIN_214 -to RAM_DQA[5]
+set_location_assignment PIN_216 -to RAM_DQA[6]
+set_location_assignment PIN_217 -to RAM_DQA[7]
+set_location_assignment PIN_218 -to RAM_ADDR[13]
+set_location_assignment PIN_219 -to RAM_ADDR[14]
+set_location_assignment PIN_221 -to RAM_ADDR[15]
+set_location_assignment PIN_223 -to RAM_ADDR[16]
+set_location_assignment PIN_224 -to RAM_ADDR[17]
+set_location_assignment PIN_226 -to RAM_ADDR[18]
+set_location_assignment PIN_230 -to RAM_ADDR[19]
+set_location_assignment PIN_231 -to RAM_ADDR[0]
+set_location_assignment PIN_232 -to RAM_ADDR[1]
+set_location_assignment PIN_233 -to RAM_ADDR[2]
+set_location_assignment PIN_234 -to RAM_ADDR[3]
+set_location_assignment PIN_235 -to RAM_ADDR[4]
+set_location_assignment PIN_236 -to RAM_ADDR[5]
+set_location_assignment PIN_237 -to RAM_DQBP
+set_location_assignment PIN_238 -to RAM_DQB[0]
+set_location_assignment PIN_239 -to RAM_DQB[1]
+set_location_assignment PIN_240 -to RAM_DQB[2]
+set_location_assignment PIN_4 -to RAM_DQB[3]
+set_location_assignment PIN_5 -to RAM_DQB[4]
+set_location_assignment PIN_6 -to RAM_DQB[5]
+set_location_assignment PIN_9 -to RAM_DQB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_50MHz
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TRG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_C[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_CCLK[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_CCLK[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CE1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7]
Index: sandbox/MultiChannelUSB/Paella.v
===================================================================
--- sandbox/MultiChannelUSB/Paella.v (revision 106)
+++ sandbox/MultiChannelUSB/Paella.v (revision 106)
@@ -0,0 +1,471 @@
+module Paella
+ (
+ input wire CLK_50MHz,
+ output wire LED,
+
+ inout wire [3:0] TRG,
+ inout wire I2C_SDA,
+ inout wire I2C_SCL,
+ inout wire [4:0] CON_A,
+ input wire [15:0] CON_B,
+ input wire [12:0] CON_C,
+ input wire [1:0] CON_BCLK,
+ input wire [1:0] CON_CCLK,
+
+ input wire ADC_DCO,
+ input wire ADC_FCO,
+ input wire [2:0] ADC_D,
+
+ output wire USB_SLRD,
+ output wire USB_SLWR,
+ input wire USB_IFCLK,
+ input wire USB_FLAGA, // EMPTY flag for EP6
+ input wire USB_FLAGB, // FULL flag for EP8
+ input wire USB_FLAGC,
+ inout wire USB_PA0,
+ inout wire USB_PA1,
+ output wire USB_PA2,
+ inout wire USB_PA3,
+ output wire USB_PA4,
+ output wire USB_PA5,
+ output wire USB_PA6,
+ inout wire USB_PA7,
+ inout wire [7:0] USB_PB,
+
+ output wire RAM_CLK,
+ output wire RAM_CE1,
+ output wire RAM_WE,
+ output wire [19:0] RAM_ADDR,
+ inout wire RAM_DQAP,
+ inout wire [7:0] RAM_DQA,
+ inout wire RAM_DQBP,
+ inout wire [7:0] RAM_DQB
+ );
+
+ localparam N = 3;
+
+ // Turn output ports off
+/*
+ assign RAM_CLK = 1'b0;
+ assign RAM_CE1 = 1'b0;
+ assign RAM_WE = 1'b0;
+ assign RAM_ADDR = 20'h00000;
+*/
+ assign RAM_CLK = sys_clock;
+ assign RAM_CE1 = 1'b0;
+
+ // Turn inout ports to tri-state
+ assign TRG = 4'bz;
+ assign CON_A = 5'bz;
+ assign USB_PA0 = 1'bz;
+ assign USB_PA1 = 1'bz;
+ assign USB_PA3 = 1'bz;
+ assign USB_PA7 = 1'bz;
+// assign RAM_DQAP = 1'bz;
+// assign RAM_DQA = 8'bz;
+// assign RAM_DQBP = 1'bz;
+// assign RAM_DQB = 8'bz;
+
+ assign USB_PA2 = ~usb_rden;
+ assign USB_PA4 = usb_addr[0];
+ assign USB_PA5 = usb_addr[1];
+ assign USB_PA6 = ~usb_pktend;
+
+ wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
+ wire usb_tx_wrreq, usb_rx_rdreq;
+ wire usb_tx_full, usb_rx_empty;
+ wire [7:0] usb_tx_data, usb_rx_data;
+ wire [1:0] usb_addr;
+
+ assign USB_SLRD = ~usb_rdreq;
+ assign USB_SLWR = ~usb_wrreq;
+
+ usb_fifo usb_unit
+ (
+ .usb_clk(USB_IFCLK),
+ .usb_data(USB_PB),
+ .usb_full(~USB_FLAGB),
+ .usb_empty(~USB_FLAGA),
+ .usb_wrreq(usb_wrreq),
+ .usb_rdreq(usb_rdreq),
+ .usb_rden(usb_rden),
+ .usb_pktend(usb_pktend),
+ .usb_addr(usb_addr),
+
+ .clk(sys_clock),
+
+ .tx_full(usb_tx_full),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+
+ .rx_empty(usb_rx_empty),
+ .rx_rdreq(usb_rx_rdreq),
+ .rx_q(usb_rx_data)
+ );
+
+ wire ana_dead [N-1:0];
+ wire ana_good [N-1:0];
+ wire [11:0] ana_data [N-1:0];
+ wire [11:0] ana_base [N-1:0];
+
+ wire cnt_good [N-1:0];
+
+ wire [11:0] osc_mux_data [N-1:0];
+
+ wire [11:0] trg_mux_data;
+ wire trg_flag;
+
+ wire [83:0] int_mux_data [N-1:0];
+
+ wire sys_clock, sys_frame;
+
+ wire [11:0] adc_data [N-1:0];
+ wire [11:0] int_data [N-1:0];
+ wire [11:0] sys_data [N-1:0];
+ wire [11:0] cmp_data;
+ wire [11:0] nowhere;
+
+ wire [31:0] uwt_d1 [N-1:0];
+ wire [31:0] uwt_a1 [N-1:0];
+ wire [31:0] uwt_peak1 [N-1:0];
+ wire [31:0] uwt_d2 [N-1:0];
+ wire [31:0] uwt_a2 [N-1:0];
+ wire [31:0] uwt_peak2 [N-1:0];
+ wire [31:0] uwt_d3 [N-1:0];
+ wire [31:0] uwt_a3 [N-1:0];
+ wire [31:0] uwt_peak3 [N-1:0];
+
+ wire [1:0] uwt_flag1 [N-1:0];
+ wire [1:0] uwt_flag2 [N-1:0];
+ wire [1:0] uwt_flag3 [N-1:0];
+
+ wire i2c_reset;
+
+/*
+ adc_para adc_para_unit (
+ .lvds_dco(ADC_DCO),
+ .lvds_fco(ADC_FCO),
+ .para_good(CON_CCLK[0]),
+ .para_data(CON_C[11:0]),
+ .adc_data(adc_data[2]));
+*/
+
+ wire adc_pll_clk;
+
+/*
+ adc_pll adc_pll_unit(
+ .inclk0(ADC_FCO),
+ .c0(adc_pll_clk));
+*/
+
+ sys_pll sys_pll_unit(
+ .inclk0(CLK_50MHz),
+ .c0(sys_clock));
+
+ test test_unit(
+ .clk(ADC_FCO),
+ .data(adc_data[2]));
+// .data(nowhere));
+
+ adc_lvds #(
+ .size(3),
+ .width(12)) adc_lvds_unit (
+ .lvds_dco(ADC_DCO),
+// .lvds_dco(adc_pll_clk),
+ .lvds_fco(ADC_FCO),
+ .lvds_d(ADC_D[2:0]),
+// .adc_data({ adc_data[2],
+ .adc_data({ nowhere,
+ adc_data[1],
+ adc_data[0] }));
+
+/*
+ assign cmp_data = CON_B[11:0];
+ assign sys_clock = ADC_DCO;
+ assign sys_frame = ADC_FCO;
+*/
+
+ wire [15:0] cfg_bits [31:0];
+ wire [511:0] int_cfg_bits;
+
+ wire [31:0] cfg_mux_selector;
+
+ wire cfg_reset;
+
+ wire [8:0] bus_ssel;
+ wire bus_wren;
+ wire [31:0] bus_addr;
+ wire [15:0] bus_mosi;
+ wire [15:0] bus_miso [7:0];
+ wire [8:0] bus_busy;
+
+ wire [15:0] mrg_bus_miso;
+ wire mrg_bus_busy;
+
+ wire [127:0] int_bus_miso;
+
+ genvar j;
+
+ generate
+ for (j = 0; j < 32; j = j + 1)
+ begin : CONFIGURATION_OUTPUT
+ assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
+ end
+ endgenerate
+
+ configuration configuration_unit (
+ .clock(sys_clock),
+ .reset(cfg_reset),
+ .bus_ssel(bus_ssel[0]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[4:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[0]),
+ .bus_busy(bus_busy[0]),
+ .cfg_bits(int_cfg_bits));
+
+ generate
+ for (j = 0; j < 3; j = j + 1)
+ begin : MUX_DATA
+ assign int_mux_data[j] = {
+ {ana_good[j], 11'd0},
+ ana_data[j],
+ ana_base[j],
+ uwt_a3[j][20:9],
+ uwt_a2[j][17:6],
+ uwt_a1[j][14:3],
+ sys_data[j]};
+ end
+ endgenerate
+
+ assign cfg_mux_selector = {cfg_bits[3], cfg_bits[2]};
+
+ lpm_mux #(
+ .lpm_size(21),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(5)) trg_mux_unit (
+ .sel(cfg_mux_selector[28:24]),
+ .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ .result(trg_mux_data));
+
+ generate
+ for (j = 0; j < 3; j = j + 1)
+ begin : OSC_CHAIN
+
+ lpm_mux #(
+ .lpm_size(21),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(5)) osc_mux_unit (
+ .sel(cfg_mux_selector[j*8+4:j*8]),
+ .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
+ .result(osc_mux_data[j]));
+
+ end
+ endgenerate
+
+ trigger trigger_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][0]),
+ .cfg_data(cfg_bits[5][11:0]),
+ .trg_data(trg_mux_data),
+ .trg_flag(trg_flag));
+
+ oscilloscope oscilloscope_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][1]),
+ .cfg_data(cfg_bits[4][0]),
+ .trg_flag(trg_flag),
+ .osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+ .ram_wren(RAM_WE),
+ .ram_addr(RAM_ADDR),
+ .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
+ .bus_ssel(bus_ssel[1]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[19:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[1]),
+ .bus_busy(bus_busy[1]));
+
+
+ adc_fifo #(.W(48)) adc_fifo_unit (
+ .adc_clock(ADC_FCO),
+ .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
+ .sys_clock(sys_clock),
+ .sys_frame(sys_frame),
+ .sys_data({cmp_data, int_data[2], int_data[1], int_data[0]}));
+
+
+ generate
+ for (j = 0; j < 3; j = j + 1)
+ begin : MCA_CHAIN
+
+ assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]);
+
+ uwt_bior31 #(.L(1)) uwt_1_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .x({20'h00000, sys_data[j]}),
+ .d(uwt_d1[j]),
+ .a(uwt_a1[j]),
+ .peak(uwt_peak1[j]),
+ .flag(uwt_flag1[j]));
+
+ uwt_bior31 #(.L(2)) uwt_2_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .x(uwt_a1[j]),
+ .d(uwt_d2[j]),
+ .a(uwt_a2[j]),
+ .peak(uwt_peak2[j]),
+ .flag(uwt_flag2[j]));
+
+ uwt_bior31 #(.L(3)) uwt_3_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .x(uwt_a2[j]),
+ .d(uwt_d3[j]),
+ .a(uwt_a3[j]),
+ .peak(uwt_peak3[j]),
+ .flag(uwt_flag3[j]));
+
+ analyser analyser_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][2+j]),
+ .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
+ .uwt_flag(uwt_flag3[j]),
+ .uwt_data(uwt_peak3[j]),
+ .ana_dead(ana_dead[j]),
+ .ana_good(ana_good[j]),
+ .ana_data(ana_data[j]),
+ .ana_base(ana_base[j]));
+
+ histogram histogram_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][5+j]),
+ .hst_good((ana_good[j]) & (cnt_good[j])),
+ .hst_data(ana_data[j]),
+ .bus_ssel(bus_ssel[2+j]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[12:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[2+j]),
+ .bus_busy(bus_busy[2+j]));
+
+ counter counter_unit (
+ .clock(sys_clock),
+ .frame((sys_frame) & (~ana_dead[j])),
+ .reset(cfg_bits[0][8+j]),
+ .cfg_data(cfg_bits[12+j]),
+ .bus_ssel(bus_ssel[5+j]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[1:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[5+j]),
+ .bus_busy(bus_busy[5+j]),
+ .cnt_good(cnt_good[j]));
+
+ end
+ endgenerate
+
+ i2c_fifo i2c_unit(
+ .clock(sys_clock),
+ .reset(i2c_reset),
+/*
+ normal connection
+ .i2c_sda(I2C_SDA),
+ .i2c_scl(I2C_SCL),
+
+ following is a cross wire connection for EPT
+*/
+ .i2c_sda(I2C_SCL),
+ .i2c_scl(I2C_SDA),
+
+ .bus_ssel(bus_ssel[8]),
+ .bus_wren(bus_wren),
+ .bus_mosi(bus_mosi),
+ .bus_busy(bus_busy[8]));
+
+ generate
+ for (j = 0; j < 8; j = j + 1)
+ begin : BUS_OUTPUT
+ assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(8),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(3)) bus_miso_mux_unit (
+ .sel(bus_addr[30:28]),
+ .data(int_bus_miso),
+ .result(mrg_bus_miso));
+
+ lpm_mux #(
+ .lpm_size(9),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(1),
+ .lpm_widths(4)) bus_busy_mux_unit (
+ .sel(bus_addr[31:28]),
+ .data(bus_busy),
+ .result(mrg_bus_busy));
+
+/*
+ lpm_or #(
+ .lpm_size(6),
+ .lpm_type("LPM_OR"),
+ .lpm_width(16)) bus_miso_or_unit (
+ .data(int_bus_miso),
+ .result(mrg_bus_miso));
+*/
+
+ lpm_decode #(
+ .lpm_decodes(9),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(4)) lpm_decode_unit (
+ .data(bus_addr[31:28]),
+ .eq(bus_ssel),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ control control_unit (
+ .clock(sys_clock),
+ .rx_empty(usb_rx_empty),
+ .tx_full(usb_tx_full),
+ .rx_data(usb_rx_data),
+ .rx_rdreq(usb_rx_rdreq),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr),
+ .bus_mosi(bus_mosi),
+ .bus_miso(mrg_bus_miso),
+ .bus_busy(mrg_bus_busy),
+ .led(LED));
+
+/*
+ altserial_flash_loader #(
+ .enable_shared_access("OFF"),
+ .enhanced_mode(1),
+ .intended_device_family("Cyclone III")) sfl_unit (
+ .noe(1'b0),
+ .asmi_access_granted(),
+ .asmi_access_request(),
+ .data0out(),
+ .dclkin(),
+ .scein(),
+ .sdoin());
+*/
+
+endmodule
Index: sandbox/MultiChannelUSB/UserInterface.tcl
===================================================================
--- sandbox/MultiChannelUSB/UserInterface.tcl (revision 106)
+++ sandbox/MultiChannelUSB/UserInterface.tcl (revision 106)
@@ -0,0 +1,1388 @@
+package require XOTcl
+
+package require BLT
+package require swt
+package require usb
+
+package require zlib
+
+wm minsize . 1000 700
+
+namespace eval ::mca {
+ namespace import ::xotcl::*
+
+ namespace import ::blt::vector
+ namespace import ::blt::graph
+ namespace import ::blt::tabnotebook
+
+ proc validate {max value} {
+ if {![regexp {^[0-9]*$} $value]} {
+ return 0
+ } elseif {$value > $max} {
+ return 0
+ } elseif {[string length $value] > 4} {
+ return 0
+ } else {
+ return 1
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ Class Display
+
+# -------------------------------------------------------------------------
+
+ Display instproc usbCmd {command} {
+ global usb_handle
+
+ if {[catch {$usb_handle writeRaw [usb::convert $command]} result]} {
+ puts {Error during write}
+ puts $result
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ Display instproc usbCmdRead {command width size} {
+ global usb_handle
+
+ my usbCmd $command
+
+ set usb_data {}
+ if {[catch {$usb_handle readHex $width $size} result]} {
+ puts {Error during read}
+ puts $result
+ set result {}
+ }
+
+ my set data $result
+ }
+
+# -------------------------------------------------------------------------
+
+ Display instproc usbCmdReadEpt {command size} {
+ global usb_handle
+
+ my usbCmd $command
+
+ set usb_data {}
+ if {[catch {$usb_handle readEpt $size} result]} {
+ puts {Error during read}
+ puts $result
+ set result {}
+ }
+
+ my set data $result
+ }
+
+# -------------------------------------------------------------------------
+
+ Class CfgDisplay -superclass Display -parameter {
+ {master}
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc init {} {
+
+ my reset
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc reset {} {
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc start {} {
+ my instvar config
+
+ trace add variable [myvar dac1] write [myproc dac1_update]
+ trace add variable [myvar dac2] write [myproc dac2_update]
+ trace add variable [myvar polar] write [myproc polar_update]
+
+ ${config(1)}.dac1 set 0
+ ${config(1)}.dac2 set 0
+
+ ${config(2)}.polar1 select
+ ${config(2)}.polar2 select
+ ${config(2)}.polar3 select
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc setup {} {
+ my instvar number master
+ my instvar config
+
+ set config(1) [labelframe ${master}.cfg1 -borderwidth 1 -relief sunken -text {DAC}]
+ set config(2) [labelframe ${master}.cfg2 -borderwidth 1 -relief sunken -text {polarity inversion}]
+
+ frame ${config(1)}.limits
+ label ${config(1)}.limits.min -text {0.0V}
+ label ${config(1)}.limits.max -text {-3.3V}
+
+ scale ${config(1)}.dac1 -orient vertical -from 0 -to 4095 -tickinterval 500 -variable [myvar dac1]
+ scale ${config(1)}.dac2 -orient vertical -from 0 -to 4095 -tickinterval 0 -variable [myvar dac2]
+
+ checkbutton ${config(2)}.polar1 -text {channel 1} -variable [myvar polar(1)]
+ checkbutton ${config(2)}.polar2 -text {channel 2} -variable [myvar polar(2)]
+ checkbutton ${config(2)}.polar3 -text {channel 3} -variable [myvar polar(3)]
+
+ grid ${config(1)} -sticky ns
+ grid ${config(2)} -sticky ew -pady 7
+
+ pack ${config(1)}.limits.min -anchor n -side top -pady 10
+ pack ${config(1)}.limits.max -anchor s -side bottom -pady 9
+
+ grid ${config(1)}.dac1 ${config(1)}.dac2 ${config(1)}.limits -sticky ns -pady 7
+
+ grid ${config(2)}.polar1
+ grid ${config(2)}.polar2
+ grid ${config(2)}.polar3
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid rowconfigure ${config(1)} 0 -weight 1
+ grid rowconfigure ${config(2)} 0 -weight 1
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc dac1_update args {
+ my instvar dac1
+
+ set value [format {%03x} $dac1]
+ set command 0005012000050030000500[string range $value 0 1]000502[string index $value 2]0
+
+ my usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc dac2_update args {
+ my instvar dac2
+
+ set value [format {%03x} $dac2]
+ set command 0005012400050030000500[string range $value 0 1]000502[string index $value 2]0
+
+ my usbCmd $command
+ }
+
+# -------------------------------------------------------------------------
+
+ CfgDisplay instproc polar_update args {
+ my instvar polar
+
+ set value [format {0%x%x%x} $polar(3) $polar(2) $polar(1)]
+
+ my usbCmd 000A${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ Class OscDisplay -superclass Display -parameter {
+ {number}
+ {master}
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc init {} {
+ my instvar data xvec yvec
+
+ set xvec [vector #auto]
+ set yvec [vector #auto]
+ # fill one vector for the x axis with 1025 points
+ $xvec seq 0 1024
+
+ my reset
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc reset {} {
+ my instvar data xvec yvec
+
+ set data {}
+
+ $yvec set {}
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc start {} {
+ my instvar config trig_mux disp_mux
+
+ set trig_mux 2
+ set disp_mux 2
+
+ trace add variable [myvar data] write [myproc data_update]
+ trace add variable [myvar auto] write [myproc auto_update]
+ trace add variable [myvar thrs] write [myproc thrs_update]
+ trace add variable [myvar thrs_val] write [myproc thrs_val_update]
+ trace add variable [myvar disp_val] write [myproc disp_val_update]
+ trace add variable [myvar trig_val] write [myproc trig_val_update]
+
+ ${config}.auto_check select
+ ${config}.thrs_check select
+ ${config}.thrs_field set 1278
+ ${config}.disp_uwt2 select
+ ${config}.trig_uwt2 select
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc setup {} {
+ my instvar number master
+ my instvar data xvec yvec
+ my instvar config auto thrs thrs_val disp_val trig_val
+
+ # create a graph widget and show a grid
+ set graph [graph ${master}.graph -height 250 -leftmargin 80]
+ $graph crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph grid configure -hide no
+ $graph legend configure -hide yes
+ $graph axis configure x -min 0 -max 1024
+ $graph axis configure y -min 0 -max 4100
+
+ set config [frame ${master}.config]
+
+ checkbutton ${config}.auto_check -text {auto update} -variable [myvar auto]
+
+ frame ${config}.spc1 -width 10 -height 10
+
+ checkbutton ${config}.thrs_check -text threshold -variable [myvar thrs]
+ spinbox ${config}.thrs_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar thrs_val] \
+ -validate all -vcmd {::mca::validate 4095 %P}
+
+ frame ${config}.spc2 -width 10 -height 10
+
+ label ${config}.disp -text {display input}
+ radiobutton ${config}.disp_data -text {raw data} -variable [myvar disp_val] -value data
+ radiobutton ${config}.disp_uwt1 -text {filter 1} -variable [myvar disp_val] -value uwt1
+ radiobutton ${config}.disp_uwt2 -text {filter 2} -variable [myvar disp_val] -value uwt2
+ radiobutton ${config}.disp_uwt3 -text {filter 3} -variable [myvar disp_val] -value uwt3
+ radiobutton ${config}.disp_base -text {baseline} -variable [myvar disp_val] -value base
+# radiobutton ${config}.disp_sum8 -text {sum of 8} -variable [myvar disp_val] -value sum8
+
+ frame ${config}.spc3 -width 10 -height 10
+
+ label ${config}.trig -text {trigger input}
+ radiobutton ${config}.trig_data -text {raw data} -variable [myvar trig_val] -value data
+ radiobutton ${config}.trig_uwt1 -text {filter 1} -variable [myvar trig_val] -value uwt1
+ radiobutton ${config}.trig_uwt2 -text {filter 2} -variable [myvar trig_val] -value uwt2
+ radiobutton ${config}.trig_uwt3 -text {filter 3} -variable [myvar trig_val] -value uwt3
+ radiobutton ${config}.trig_base -text {baseline} -variable [myvar trig_val] -value base
+# radiobutton ${config}.trig_sum8 -text {sum of 8} -variable [myvar trig_val] -value sum8
+
+ frame ${config}.spc4 -width 10 -height 10
+
+ button ${config}.acquire -text Acquire \
+ -bg green -activebackground green -command [myproc acquire]
+ button ${config}.restart -text Restart \
+ -bg yellow -activebackground yellow -command [myproc restart]
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+ grid ${config}.auto_check -sticky w
+ grid ${config}.spc1
+ grid ${config}.thrs_check -sticky w
+ grid ${config}.thrs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc2
+ grid ${config}.disp -sticky w -pady 1 -padx 3
+ grid ${config}.disp_data -sticky w
+ grid ${config}.disp_uwt1 -sticky w
+ grid ${config}.disp_uwt2 -sticky w
+ grid ${config}.disp_uwt3 -sticky w
+ grid ${config}.disp_base -sticky w
+# grid ${config}.disp_sum8 -sticky w
+ grid ${config}.spc3
+ grid ${config}.trig -sticky w -pady 1 -padx 3
+ grid ${config}.trig_data -sticky w
+ grid ${config}.trig_uwt1 -sticky w
+ grid ${config}.trig_uwt2 -sticky w
+ grid ${config}.trig_uwt3 -sticky w
+ grid ${config}.trig_base -sticky w
+# grid ${config}.disp_sum8 -sticky w
+ grid ${config}.spc4
+ grid ${config}.acquire -sticky ew -pady 3 -padx 5
+ grid ${config}.restart -sticky ew -pady 3 -padx 5
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+
+ grid ${graph} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 80
+
+ # enable zooming
+ Blt_ZoomStack $graph
+
+ #bind .graph {%W crosshairs configure -position @%x,%y}
+
+ # create one element with data for the x and y axis, no dots
+ $graph element create Spectrum1 -symbol none -xdata $xvec -ydata $yvec
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc data_update args {
+ my instvar data yvec
+ $yvec set $data
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc auto_update args {
+ my instvar config auto after_handle
+
+ if {$auto} {
+ ${config}.acquire configure -state disabled
+ ${config}.restart configure -state disabled
+ ${config}.register configure -state disabled
+
+ my acquire_restart_loop
+ } else {
+ if {[my exists after_handle]} {
+ after cancel $after_handle
+ }
+ ${config}.acquire configure -state active
+ ${config}.restart configure -state active
+ ${config}.register configure -state active
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc thrs_update args {
+ my instvar config number thrs thrs_val
+
+ set val_addr [format %04x [expr {17 + ${number}}]]
+
+ if {$thrs} {
+ ${config}.thrs_field configure -state normal
+ my thrs_val_update
+ } else {
+ ${config}.thrs_field configure -state disabled
+ my usbCmd ${val_addr}0000
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc thrs_val_update args {
+ my instvar config number thrs_val
+
+ if {[string equal $thrs_val {}]} {
+ set thrs_val 0
+ }
+
+ set val_addr [format %04x [expr {17 + ${number}}]]
+ set value [format %04x $thrs_val]
+
+ my usbCmd ${val_addr}${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc mux {} {
+ my instvar trig_mux disp_mux
+
+ format {00%x%x} $trig_mux $disp_mux
+ }
+
+# ------------------------------------------------------------------------
+
+ OscDisplay instproc disp_val_update args {
+ my instvar number disp_val disp_mux
+
+ set mux_addr [format %04x [expr {20 + ${number}}]]
+
+ switch -- $disp_val {
+ data {
+ set disp_mux 0
+ my usbCmd ${mux_addr}[my mux]
+ }
+ uwt1 {
+ set disp_mux 1
+ my usbCmd ${mux_addr}[my mux]
+ }
+ uwt2 {
+ set disp_mux 2
+ my usbCmd ${mux_addr}[my mux]
+ }
+ uwt3 {
+ set disp_mux 3
+ my usbCmd ${mux_addr}[my mux]
+ }
+ base {
+ set disp_mux 4
+ my usbCmd ${mux_addr}[my mux]
+ }
+ }
+ }
+
+# ------------------------------------------------------------------------
+
+ OscDisplay instproc trig_val_update args {
+ my instvar number trig_val trig_mux
+
+ set mux_addr [format %04x [expr {20 + ${number}}]]
+
+ switch -- $trig_val {
+ data {
+ set trig_mux 0
+ my usbCmd ${mux_addr}[my mux]
+ }
+ uwt1 {
+ set trig_mux 1
+ my usbCmd ${mux_addr}[my mux]
+ }
+ uwt2 {
+ set trig_mux 2
+ my usbCmd ${mux_addr}[my mux]
+ }
+ uwt3 {
+ set trig_mux 3
+ my usbCmd ${mux_addr}[my mux]
+ }
+ base {
+ set trig_mux 4
+ my usbCmd ${mux_addr}[my mux]
+ }
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc save_data {data} {
+ set file [tk_getSaveFile]
+ if {[string equal $file {}]} {
+ return
+ }
+
+ set x [catch {set fid [open $file w+]}]
+ set y [catch {puts $fid $data}]
+ set z [catch {close $fid}]
+
+ if { $x || $y || $z || ![file exists $file] || ![file isfile $file] || ![file readable $file] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$file\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$file\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc acquire {} {
+ my instvar number
+ my usbCmdRead 0002000${number} 2 1024
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc restart {} {
+ my instvar number
+ my usbCmd 0001000${number}
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc register {} {
+ my save_data [my set data]
+ }
+
+# -------------------------------------------------------------------------
+
+ OscDisplay instproc acquire_restart_loop {} {
+ my instvar number after_handle
+
+ my acquire
+ my restart
+
+ set after_handle [after 1000 [myproc acquire_restart_loop]]
+ }
+
+# -------------------------------------------------------------------------
+
+ Class HstDisplay -superclass Display -parameter {
+ {number}
+ {master}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc init {} {
+ my instvar data xvec yvec
+
+ set xvec [vector #auto]
+ set yvec [vector #auto]
+ # fill one vector for the x axis with 4097 points
+ $xvec seq 0 4096
+
+ my reset
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc reset {} {
+ my instvar data xvec yvec
+
+ set data {}
+
+ $yvec set {}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc start {} {
+ my instvar config base_mux peak_mux
+
+ set base_mux 0
+ set peak_mux 1
+
+ trace add variable [myvar axis] write [myproc axis_update]
+ trace add variable [myvar data] write [myproc data_update]
+ trace add variable [myvar auto] write [myproc auto_update]
+ trace add variable [myvar peak] write [myproc peak_update]
+ trace add variable [myvar thrs] write [myproc thrs_update]
+ trace add variable [myvar thrs_val] write [myproc thrs_val_update]
+ trace add variable [myvar base] write [myproc base_update]
+ trace add variable [myvar base_typ] write [myproc base_typ_update]
+ trace add variable [myvar base_val] write [myproc base_val_update]
+
+ ${config}.axis_check deselect
+ ${config}.auto_check select
+ ${config}.peak_check select
+
+ ${config}.thrs_check select
+ ${config}.thrs_field set 1278
+
+ ${config}.base_const select
+ ${config}.base_field set 35
+ ${config}.base_check deselect
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc setup {} {
+ my instvar number master
+ my instvar data xvec yvec graph
+ my instvar config auto thrs thrs_val base base_typ base_val
+
+ # create a graph widget and show a grid
+ set graph [graph ${master}.graph -height 250 -leftmargin 80]
+ $graph crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph grid configure -hide no
+ $graph legend configure -hide yes
+ $graph axis configure x -min 0 -max 4096
+
+ set config [frame ${master}.config]
+
+ checkbutton ${config}.axis_check -text {log scale} -variable [myvar axis]
+
+ frame ${config}.spc1 -width 10 -height 10
+
+ checkbutton ${config}.auto_check -text {auto update} -variable [myvar auto]
+
+ frame ${config}.spc2 -width 10 -height 10
+
+ checkbutton ${config}.peak_check -text {peak detect} -variable [myvar peak]
+
+ frame ${config}.spc3 -width 10 -height 10
+
+ checkbutton ${config}.thrs_check -text threshold -variable [myvar thrs]
+ spinbox ${config}.thrs_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar thrs_val] \
+ -validate all -vcmd {::mca::validate 4095 %P}
+
+ frame ${config}.spc4 -width 10 -height 10
+
+ checkbutton ${config}.base_check -text baseline -variable [myvar base]
+ radiobutton ${config}.base_auto -text automatic -variable [myvar base_typ] -value auto
+ radiobutton ${config}.base_const -text constant -variable [myvar base_typ] -value const
+ spinbox ${config}.base_field -from 1 -to 4095 \
+ -increment 5 -width 10 -textvariable [myvar base_val] \
+ -validate all -vcmd {::mca::validate 4095 %P}
+
+ frame ${config}.spc5 -width 10 -height 10
+
+ button ${config}.acquire -text Acquire \
+ -bg green -activebackground green -command [myproc acquire]
+ button ${config}.restart -text Restart \
+ -bg yellow -activebackground yellow -command [myproc restart]
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+ grid ${config}.axis_check -sticky w
+ grid ${config}.spc1
+ grid ${config}.auto_check -sticky w
+ grid ${config}.spc2
+ grid ${config}.peak_check -sticky w
+ grid ${config}.spc3
+ grid ${config}.thrs_check -sticky w
+ grid ${config}.thrs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc4
+ grid ${config}.base_check -sticky w
+ grid ${config}.base_auto -sticky w
+ grid ${config}.base_const -sticky w
+ grid ${config}.base_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc5
+ grid ${config}.acquire -sticky ew -pady 3 -padx 5
+ grid ${config}.restart -sticky ew -pady 3 -padx 5
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+
+ grid ${graph} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 80
+
+ # enable zooming
+ Blt_ZoomStack $graph
+
+ #bind .graph {%W crosshairs configure -position @%x,%y}
+
+ # create one element with data for the x and y axis, no dots
+ $graph element create Spectrum1 -symbol none -smooth step -xdata $xvec -ydata $yvec
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc axis_update args {
+ my instvar axis graph
+ if {$axis} {
+ $graph axis configure y -min 1 -max 1E10 -logscale yes
+ } else {
+ $graph axis configure y -min {} -max {} -logscale no
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc data_update args {
+ my instvar data yvec
+ $yvec set $data
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc auto_update args {
+ my instvar auto after_handle
+ my instvar config
+ if {$auto} {
+ ${config}.acquire configure -state disabled
+ ${config}.register configure -state disabled
+
+ my acquire_loop
+ } else {
+ if {[my exists after_handle]} {
+ after cancel $after_handle
+ }
+ ${config}.acquire configure -state active
+ ${config}.register configure -state active
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc mux {} {
+ my instvar base_mux peak_mux
+
+ format {00%x%x} $base_mux $peak_mux
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc peak_update args {
+ my instvar number peak peak_mux
+
+ set mux_addr [format %04x [expr {23 + ${number}}]]
+
+ if {$peak} {
+ set peak_mux 1
+ my usbCmd ${mux_addr}[my mux]
+ } else {
+ set peak_mux 0
+ my usbCmd ${mux_addr}[my mux]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc thrs_update args {
+ my instvar config number thrs thrs_val
+
+ set val_addr [format %04x [expr {14 + ${number}}]]
+
+ if {$thrs} {
+ ${config}.thrs_field configure -state normal
+ my thrs_val_update
+ } else {
+ ${config}.thrs_field configure -state disabled
+ my usbCmd ${val_addr}0000
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc thrs_val_update args {
+ my instvar config number thrs_val
+
+ if {[string equal $thrs_val {}]} {
+ set thrs_val 0
+ }
+
+ set val_addr [format %04x [expr {14 + ${number}}]]
+ set value [format %04x $thrs_val]
+
+ my usbCmd ${val_addr}${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc base_update args {
+ my instvar config number base base_val base_mux
+
+ set mux_addr [format %04x [expr {23 + ${number}}]]
+ set val_addr [format %04x [expr {11 + ${number}}]]
+
+ if {$base} {
+ ${config}.base_auto configure -state normal
+ ${config}.base_const configure -state normal
+ my base_typ_update
+ } else {
+ ${config}.base_auto configure -state disabled
+ ${config}.base_const configure -state disabled
+ ${config}.base_field configure -state disabled
+ set base_mux 0
+ my usbCmd ${mux_addr}[my mux]${val_addr}0000
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc base_typ_update args {
+ my instvar config number base_typ base_val base_mux
+
+ set mux_addr [format %04x [expr {23 + ${number}}]]
+ set val_addr [format %04x [expr {11 + ${number}}]]
+ set value [format %04x $base_val]
+
+ switch -- $base_typ {
+ auto {
+ ${config}.base_field configure -state disabled
+ set base_mux 1
+ my usbCmd ${mux_addr}[my mux]
+ }
+ const {
+ ${config}.base_field configure -state normal
+ set base_mux 0
+ my usbCmd ${mux_addr}[my mux]${val_addr}${value}
+ }
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc base_val_update args {
+ my instvar number base_val
+
+ if {[string equal $base_val {}]} {
+ set base_val 0
+ }
+
+ set val_addr [format %04x [expr {11 + ${number}}]]
+ set value [format %04x $base_val]
+
+ my usbCmd ${val_addr}${value}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc acquire {} {
+ my instvar number
+ my usbCmdRead 0002001${number} 4 4096
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc restart {} {
+ my instvar number
+ my usbCmd 0001001${number}
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc save_data {data} {
+ set file [tk_getSaveFile]
+ if {[string equal $file {}]} {
+ return
+ }
+
+ set x [catch {set fid [open $file w+]}]
+ set y [catch {puts $fid $data}]
+ set z [catch {close $fid}]
+
+ if { $x || $y || $z || ![file exists $file] || ![file isfile $file] || ![file readable $file] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$file\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$file\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc register {} {
+ my save_data [my set data]
+ }
+
+# -------------------------------------------------------------------------
+
+ HstDisplay instproc acquire_loop {} {
+ my instvar number after_handle
+
+ my acquire
+
+ set after_handle [after 1000 [myproc acquire_loop]]
+ }
+
+# -------------------------------------------------------------------------
+
+ Class EptDisplay -superclass Display -parameter {
+ {number}
+ {master}
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc init {} {
+ my instvar data xvec yvec
+
+ set xvec [vector #auto]
+
+ for {set i 0} {$i < 11} {incr i} {
+ set yvec($i) [vector #auto]
+ }
+
+ # fill one vector for the x axis
+ $xvec seq 0 10000
+
+ my reset
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc reset {} {
+ my instvar data xvec yvec
+ my instvar number_val directory
+
+ set data {}
+
+ set directory $::env(HOMEPATH)
+ set number_val 10
+
+ for {set i 0} {$i < 11} {incr i} {
+ $yvec($i) set {}
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc start {} {
+ my instvar config
+
+ trace add variable [myvar recs_val] write [myproc recs_val_update]
+ trace add variable [myvar data] write [myproc data_update]
+ trace add variable [myvar last] write [myproc data_update]
+
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc setup {} {
+ my instvar master
+ my instvar data xvec yvec graph
+ my instvar config number_val
+
+ # create a graph widget and show a grid
+ set display [frame ${master}.display]
+
+ set graph(0) [graph ${display}.graph0 -height 200 -leftmargin 80]
+ $graph(0) crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph(0) grid configure -hide no
+ $graph(0) legend configure -hide yes
+ $graph(0) axis configure x -min 0 -max 10000
+ $graph(0) axis configure y -min 0 -max 4100
+
+ set graph(1) [graph ${display}.graph1 -height 200 -leftmargin 80]
+ $graph(1) crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph(1) grid configure -hide no
+ $graph(1) legend configure -hide yes
+ $graph(1) axis configure x -min 0 -max 10000 -hide yes
+ $graph(1) axis configure y -min 0 -max 4100
+
+ set graph(2) [graph ${display}.graph2 -height 200 -leftmargin 80]
+ $graph(2) crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph(2) grid configure -hide no
+ $graph(2) legend configure -hide yes
+ $graph(2) axis configure x -min 0 -max 10000 -hide yes
+ $graph(2) axis configure y -min 0 -max 4100
+
+ set graph(3) [graph ${display}.graph3 -height 100 -leftmargin 80]
+ $graph(3) crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph(3) grid configure -hide no
+ $graph(3) legend configure -hide yes
+ $graph(3) axis configure x -min 0 -max 10000 -hide yes
+ $graph(3) axis configure y -min 0 -max 25
+
+ scale ${master}.last -orient horizontal -from 1 -to 35 -tickinterval 0 -showvalue no -variable [myvar last]
+
+ set config [frame ${master}.config -width 120]
+
+ label ${config}.recs -text {number of records}
+ spinbox ${config}.recs_field -from 5 -to 100 \
+ -increment 5 -width 10 -textvariable [myvar recs_val] \
+ -validate all -vcmd {::mca::validate 100 %P}
+
+ frame ${config}.spc1 -width 10 -height 10
+
+ button ${config}.sequence -text {Start Recording} \
+ -bg red -activebackground red -command [myproc sequence]
+
+ frame ${config}.spc2 -width 10 -height 10
+
+ label ${config}.stat -text {}
+
+ frame ${config}.spc3 -width 10 -height 20
+
+ button ${config}.acquire -text Acquire \
+ -bg green -activebackground green -command [myproc acquire]
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+
+ grid ${config}.recs -sticky w -pady 1 -padx 3
+ grid ${config}.recs_field -sticky ew -pady 1 -padx 5
+ grid ${config}.spc1
+ grid ${config}.sequence -sticky ew -pady 3 -padx 5
+ grid ${config}.spc2
+ grid ${config}.stat -sticky w -pady 1 -padx 3
+ grid ${config}.spc3
+ grid ${config}.acquire -sticky ew -pady 3 -padx 5
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+
+ grid ${graph(3)} -row 0 -column 0 -sticky news
+ grid ${graph(2)} -row 1 -column 0 -sticky news
+ grid ${graph(1)} -row 2 -column 0 -sticky news
+ grid ${graph(0)} -row 3 -column 0 -sticky news
+
+ grid ${display} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+ grid ${master}.last -row 1 -column 0 -columnspan 2 -sticky ew
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 120
+
+ grid columnconfigure ${display} 0 -weight 1
+ grid rowconfigure ${display} 0 -weight 1
+ grid rowconfigure ${display} 1 -weight 1
+ grid rowconfigure ${display} 2 -weight 1
+ grid rowconfigure ${display} 3 -weight 1
+
+ # enable zooming
+ Blt_ZoomStack $graph(0)
+ Blt_ZoomStack $graph(1)
+ Blt_ZoomStack $graph(2)
+ Blt_ZoomStack $graph(3)
+
+ #bind .graph {%W crosshairs configure -position @%x,%y}
+
+ # create one element with data for the x and y axis, no dots
+ $graph(0) element create Spectrum0 -symbol none -xdata $xvec -ydata $yvec(0)
+ $graph(1) element create Spectrum1 -symbol none -xdata $xvec -ydata $yvec(1)
+ $graph(2) element create Spectrum2 -symbol none -xdata $xvec -ydata $yvec(2)
+ for {set i 3} {$i < 11} {incr i} {
+ $graph(3) element create Spectrum$i -symbol none -xdata $xvec -ydata $yvec($i)
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc recs_val_update args {
+ my instvar recs_val
+ if {[string equal $recs_val {}]} {
+ set number_val 0
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc data_update args {
+ my instvar data xvec yvec graph last
+
+ set first [expr {$last - 1}]
+
+ $xvec seq ${first}0000 ${last}0000
+ for {set i 0} {$i < 4} {incr i} {
+ $graph($i) axis configure x -min ${first}0000 -max ${last}0000
+ }
+
+ for {set i 0} {$i < 11} {incr i} {
+ $yvec($i) set [lrange [lindex $data $i] ${first}0000 ${last}0000]
+ }
+ }
+
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc save_data {data} {
+ set file [tk_getSaveFile]
+ if {[string equal $file {}]} {
+ return
+ }
+
+ set x [catch {set fid [open $file w+]}]
+ set y [catch {puts $fid $data}]
+ set z [catch {close $fid}]
+
+ if { $x || $y || $z || ![file exists $file] || ![file isfile $file] || ![file readable $file] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$file\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$file\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc acquire {} {
+ my usbCmdReadEpt 00060000 2097152
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc register {} {
+ my save_data [my set data]
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc sequence {} {
+ my instvar config recs_val directory counter
+
+ set directory [tk_chooseDirectory -initialdir $directory -title {Choose a directory}]
+
+ if {[string equal $directory {}]} {
+ return
+ }
+
+ ${config}.recs_field configure -state disabled
+ ${config}.sequence configure -state disabled
+ ${config}.acquire configure -state disabled
+ ${config}.register configure -state disabled
+
+ set counter 1
+
+ if {$counter <= $recs_val} {
+ ${config}.stat configure -text "record $counter of $recs_val"
+ set after_handle [after 100 [myproc acquire_register_loop]]
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ EptDisplay instproc acquire_register_loop {} {
+ my instvar after_handle
+ my instvar config data recs_val directory counter
+
+ my acquire
+
+ set file [file join $directory ept_$counter.dat.gz]
+
+ set x [catch {set fid [open $file w+]}]
+ fconfigure $fid -translation binary -encoding binary
+
+ set y [catch {
+ puts -nonewline $fid [binary format "H*iH*" "1f8b0800" [clock seconds] "0003"]
+ puts -nonewline $fid [zlib deflate $data]
+ puts -nonewline $fid [binary format i [zlib crc32 $data]]
+ puts -nonewline $fid [binary format i [string length $data]]
+ }]
+
+ set z [catch {close $fid}]
+
+ my incr counter
+
+ if { $x || $y || $z || ![file exists $file] || ![file isfile $file] || ![file readable $file] } {
+ tk_messageBox -icon error -message "An error occurred while writing to \"$file\""
+ } elseif {$counter <= $recs_val} {
+ ${config}.stat configure -text "record $counter of $recs_val"
+ set after_handle [after 100 [myproc acquire_register_loop]]
+ return
+ }
+
+ ${config}.stat configure -text {}
+ ${config}.recs_field configure -state normal
+ ${config}.sequence configure -state active
+ ${config}.acquire configure -state active
+ ${config}.register configure -state active
+
+ }
+
+# -------------------------------------------------------------------------
+
+ Class MemDisplay -superclass Display -parameter {
+ {number}
+ {master}
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc init {} {
+ my instvar data xvec yvec
+
+ set xvec [vector #auto]
+ set yvec [vector #auto]
+
+ # fill one vector for the x axis
+ $xvec seq 0 10000
+
+ my reset
+
+ my setup
+
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc destroy {} {
+ next
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc reset {} {
+ my instvar data xvec yvec
+
+ set data {}
+
+ $yvec set {}
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc start {} {
+ my instvar config
+
+ trace add variable [myvar data] write [myproc data_update]
+ trace add variable [myvar last] write [myproc data_update]
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc setup {} {
+ my instvar master
+ my instvar data xvec yvec
+ my instvar config auto thrs thrs_val disp_val trig_val
+
+ # create a graph widget and show a grid
+ set graph [graph ${master}.graph -height 250 -leftmargin 80]
+ $graph crosshairs configure -hide no -linewidth 2 -dashes { 1 1 }
+ $graph grid configure -hide no
+ $graph legend configure -hide yes
+ $graph axis configure x -min 0 -max 10000
+# $graph axis configure y -min 0 -max 4100
+
+ scale ${master}.last -orient horizontal -from 1 -to 105 -tickinterval 0 -variable [myvar last]
+
+ set config [frame ${master}.config]
+
+ button ${config}.acquire -text Acquire \
+ -bg green -activebackground green -command [myproc acquire]
+ button ${config}.register -text Register \
+ -bg lightblue -activebackground lightblue -command [myproc register]
+
+ grid ${config}.acquire -sticky ew -pady 3 -padx 5
+ grid ${config}.register -sticky ew -pady 3 -padx 5
+
+ grid ${graph} -row 0 -column 0 -sticky news
+ grid ${config} -row 0 -column 1
+
+ grid ${master}.last -row 1 -column 0 -columnspan 2 -sticky ew
+
+ grid rowconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 0 -weight 1
+ grid columnconfigure ${master} 1 -weight 0 -minsize 80
+
+ # enable zooming
+ Blt_ZoomStack $graph
+
+ #bind .graph {%W crosshairs configure -position @%x,%y}
+
+ # create one element with data for the x and y axis, no dots
+ $graph element create Spectrum -symbol none -xdata $xvec -ydata $yvec
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc data_update args {
+ my instvar data yvec last
+
+ set first [expr {$last - 1}]
+ $yvec set [lrange $data ${first}0000 ${last}0000]
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc save_data {data} {
+ set file [tk_getSaveFile]
+ if {[string equal $file {}]} {
+ return
+ }
+
+ set x [catch {set fid [open $file w+]}]
+ set y [catch {puts $fid $data}]
+ set z [catch {close $fid}]
+
+ if { $x || $y || $z || ![file exists $file] || ![file isfile $file] || ![file readable $file] } {
+ tk_messageBox -icon error \
+ -message "An error occurred while writing to \"$file\""
+ } else {
+ tk_messageBox -icon info \
+ -message "File \"$file\" written successfully"
+ }
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc acquire {} {
+ my usbCmdRead 00040000 1 524288
+# my usbCmdRead 00060000 1 1048576
+ }
+
+# -------------------------------------------------------------------------
+
+ MemDisplay instproc register {} {
+ my save_data [my set data]
+ }
+
+# -------------------------------------------------------------------------
+
+ namespace export MemDisplay
+ namespace export EptDisplay
+ namespace export HstDisplay
+ namespace export OscDisplay
+ namespace export CfgDisplay
+}
+
+set config [frame .config]
+set notebook [::blt::tabnotebook .notebook -borderwidth 1 -selectforeground black -side bottom]
+
+grid ${config} -row 0 -column 0 -sticky ns -padx 3
+grid ${notebook} -row 0 -column 1 -sticky news -pady 5
+
+grid rowconfigure . 0 -weight 1
+grid columnconfigure . 0 -weight 0 -minsize 50
+grid columnconfigure . 1 -weight 1
+
+foreach i {0 1 2} {
+ set channel [expr $i + 1]
+
+ set window [frame ${notebook}.hst_$i]
+ $notebook insert end -text "Histogram $channel" -window $window -fill both
+ ::mca::HstDisplay hst_$i -number $i -master $window
+
+ set window [frame ${notebook}.osc_$i]
+ $notebook insert end -text "Pulse shape $channel" -window $window -fill both
+ ::mca::OscDisplay osc_$i -number $i -master $window
+}
+
+#set window [frame ${notebook}.cfg]
+#$notebook insert end -text "Configuration" -window $window -fill both
+::mca::CfgDisplay cfg -master $config
+
+set window [frame ${notebook}.ept]
+$notebook insert end -text "EPT" -window $window -fill both
+::mca::EptDisplay ept -master $window
+
+#set window [frame ${notebook}.mem]
+#$notebook insert end -text "Memory test" -window $window -fill both
+#::mca::MemDisplay mem -master $window
+
+set usb_handle {}
+
+while {[catch {usb::connect 0x09FB 0x6001 1 1 0} usb_handle]} {
+ set answer [tk_messageBox -icon error -type retrycancel \
+ -message {Cannot access USB device} -detail $usb_handle]
+ if {[string equal $answer cancel]} break
+}
+
+# cfg reset
+cfg reset
+
+cfg start
+
+foreach i {0 1 2} {
+ hst_$i start
+ osc_$i start
+
+ hst_$i restart
+ osc_$i restart
+}
+
+ept start
+#mem start
Index: sandbox/MultiChannelUSB/adc_fifo.v
===================================================================
--- sandbox/MultiChannelUSB/adc_fifo.v (revision 106)
+++ sandbox/MultiChannelUSB/adc_fifo.v (revision 106)
@@ -0,0 +1,73 @@
+module adc_fifo
+ #(
+ parameter W = 48 // fifo width
+ )
+ (
+ input wire adc_clock,
+ input wire [W-1:0] adc_data,
+
+ input wire sys_clock,
+ output wire sys_frame,
+ output wire [W-1:0] sys_data
+ );
+
+ wire [W-1:0] int_q;
+ reg [W-1:0] int_data;
+
+ reg state, int_rdreq, int_frame;
+ wire int_wrfull, int_rdempty;
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(W),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("ON"),
+ .write_aclr_synch("OFF")) fifo_unit (
+ .aclr(1'b0),
+ .data(adc_data),
+ .rdclk(sys_clock),
+ .rdreq((~int_rdempty) & int_rdreq),
+ .wrclk(adc_clock),
+ .wrreq(~int_wrfull),
+ .q(int_q),
+ .rdempty(int_rdempty),
+ .wrfull(int_wrfull),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ always @(posedge sys_clock)
+ begin
+ case (state)
+ 1'b0:
+ begin
+ int_rdreq <= 1'b1;
+ int_frame <= 1'b0;
+ state <= 1'b1;
+ end
+
+ 1'b1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_rdreq <= 1'b0;
+ int_frame <= 1'b1;
+ state <= 1'b0;
+ end
+ end
+ endcase
+ end
+
+ assign sys_frame = int_frame;
+ assign sys_data = int_data;
+
+endmodule
Index: sandbox/MultiChannelUSB/adc_lvds.v
===================================================================
--- sandbox/MultiChannelUSB/adc_lvds.v (revision 106)
+++ sandbox/MultiChannelUSB/adc_lvds.v (revision 106)
@@ -0,0 +1,74 @@
+module adc_lvds
+ #(
+ parameter size = 3, // number of channels
+ parameter width = 12 // channel resolution
+ )
+ (
+ input wire lvds_dco,
+ input wire lvds_fco,
+ input wire [size-1:0] lvds_d,
+
+ output wire [size*width-1:0] adc_data
+ );
+
+ wire [size-1:0] int_data_h, int_data_l;
+ reg [width-1:0] int_data_next [size-1:0];
+// reg [2*width:0] int_data_next [size-1:0];
+ reg [width-1:0] int_data_reg [size-1:0];
+// reg [2*width:0] int_data_reg [size-1:0];
+
+ reg [width-1:0] int_adc_data [size-1:0];
+
+ integer i;
+ genvar j;
+
+ altddio_in #(
+ .intended_device_family("Cyclone III"),
+ .invert_input_clocks("ON"),
+// .invert_input_clocks("OFF"),
+ .lpm_type("altddio_in"),
+ .width(size)) altddio_in_unit (
+ .datain(lvds_d),
+ .inclock(lvds_dco),
+ .aclr(1'b0),
+ .dataout_h(int_data_h),
+ .dataout_l(int_data_l),
+ .aset(1'b0),
+ .inclocken(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0));
+
+ always @ (posedge lvds_dco)
+ begin
+ for (i = 0; i < size; i = i + 1)
+ begin
+ int_data_reg[i] <= int_data_next[i];
+ end
+ end
+
+ always @ (posedge lvds_fco)
+ begin
+ for (i = 0; i < size; i = i + 1)
+ begin
+ int_adc_data[i] <= int_data_next[i];
+// int_data_next[i] = {int_data_reg[i][2*width-2:0], int_data_l[i], int_data_h[i]};
+ end
+ end
+
+ always @*
+ begin
+ for (i = 0; i < size; i = i + 1)
+ begin
+ int_data_next[i] = {int_data_reg[i][width-3:0], int_data_l[i], int_data_h[i]};
+// int_data_next[i] = {int_data_reg[i][2*width-2:0], int_data_l[i], int_data_h[i]};
+ end
+ end
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : ADC_LVDS_OUTPUT
+ assign adc_data[j*width+width-1:j*width] = int_adc_data[j];
+ end
+ endgenerate
+
+endmodule
Index: sandbox/MultiChannelUSB/adc_para.v
===================================================================
--- sandbox/MultiChannelUSB/adc_para.v (revision 106)
+++ sandbox/MultiChannelUSB/adc_para.v (revision 106)
@@ -0,0 +1,31 @@
+module adc_para
+ (
+ input wire lvds_dco,
+ input wire lvds_fco,
+ input wire para_data_ready,
+ input wire [11:0] para_data,
+
+ output wire [11:0] adc_data
+ );
+
+ reg [1:0] int_data_ready;
+ reg [11:0] int_data, int_adc_data;
+
+ always @ (posedge lvds_dco)
+ begin
+ int_data_ready[1] <= int_data_ready[0];
+ int_data_ready[0] <= para_data_ready;
+ if ((int_data_ready[0]) & (~int_data_ready[1]))
+ begin
+ int_data <= para_data;
+ end
+ end
+
+ always @ (posedge lvds_fco)
+ begin
+ int_adc_data <= int_data;
+ end
+
+ assign adc_data = int_adc_data;
+
+endmodule
Index: sandbox/MultiChannelUSB/adc_pll.v
===================================================================
--- sandbox/MultiChannelUSB/adc_pll.v (revision 106)
+++ sandbox/MultiChannelUSB/adc_pll.v (revision 106)
@@ -0,0 +1,146 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: adc_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module adc_pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 6,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 50000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=adc_pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+
+endmodule
Index: sandbox/MultiChannelUSB/analyser.v
===================================================================
--- sandbox/MultiChannelUSB/analyser.v (revision 106)
+++ sandbox/MultiChannelUSB/analyser.v (revision 106)
@@ -0,0 +1,187 @@
+module analyser
+ (
+ input wire clock, frame, reset,
+ input wire [24:0] cfg_data,
+ input wire [1:0] uwt_flag,
+ input wire [11:0] uwt_data,
+ output wire ana_dead,
+ output wire ana_good,
+ output wire [11:0] ana_data,
+ output wire [11:0] ana_base
+ );
+
+ reg [2:0] state_reg, state_next;
+ reg [4:0] counter_reg, counter_next;
+ reg dead_reg, dead_next;
+ reg good_reg, good_next;
+ reg [11:0] data_reg, data_next;
+
+ reg [19:0] sample_reg, sample_next;
+
+ reg [19:0] buffer_reg [31:0];
+ reg [19:0] buffer_next [31:0];
+
+ wire [11:0] baseline = buffer_reg[31][16:5];
+ wire counter_max = (&counter_reg);
+
+ integer i;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ state_reg <= 3'd0;
+ counter_reg <= 5'd0;
+ sample_reg = 20'd0;
+ dead_reg <= 1'b0;
+ good_reg <= 1'b0;
+ data_reg <= 12'd0;
+
+ for (i = 0; i <= 31; i = i + 1)
+ begin
+ buffer_reg[i] <= 20'hfffff;
+ end
+ end
+ else
+ begin
+ state_reg <= state_next;
+ counter_reg <= counter_next;
+ sample_reg <= sample_next;
+ dead_reg <= dead_next;
+ good_reg <= good_next;
+ data_reg <= data_next;
+
+ for (i = 0; i <= 31; i = i + 1)
+ begin
+ buffer_reg[i] <= buffer_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ state_next = state_reg;
+ counter_next = counter_reg;
+ sample_next = sample_reg;
+ dead_next = dead_reg;
+ good_next = good_reg;
+ data_next = data_reg;
+
+ for (i = 0; i <= 31; i = i + 1)
+ begin
+ buffer_next[i] = buffer_reg[i];
+ end
+
+ case (state_reg)
+ 0: // skip first 32 samples
+ begin
+ if (frame)
+ begin
+ counter_next = counter_reg + 5'd1;
+ if (counter_max)
+ begin
+ state_next = 3'd1;
+ end
+ end
+ end
+
+ 1: // skip first 32 baseline samples
+ begin
+ if (frame)
+ begin
+ for (i = 0; i < 31; i = i + 1)
+ begin
+ buffer_next[i+1] = buffer_reg[i] + {8'd0, uwt_data};
+ end
+ buffer_next[0] = {8'd0, uwt_data};
+
+ counter_next = counter_reg + 5'd1;
+ if (counter_max)
+ begin
+ state_next = 3'd2;
+ end
+ end
+ end
+
+ 2:
+ begin
+ if (frame)
+ begin
+
+ if (cfg_data[24])
+ begin
+ if (uwt_data > baseline)
+ begin
+ data_next = uwt_data - baseline;
+ end
+ else
+ begin
+ data_next = 12'd0;
+ end
+ end
+ else
+ begin
+ if (uwt_data > cfg_data[23:12])
+ begin
+ data_next = uwt_data - cfg_data[23:12];
+ end
+ else
+ begin
+ data_next = 12'd0;
+ end
+ end
+
+ sample_next = {8'd0, uwt_data};
+
+ dead_next = 1'b1;
+ good_next = 1'b0;
+
+ state_next = 3'd3;
+ end
+ end
+
+ 3:
+ begin
+
+ // if (sample - baseline < threshold)
+ if (data_reg < cfg_data[11:0])
+ begin
+ for (i = 0; i < 31; i = i + 1)
+ begin
+ buffer_next[i+1] = buffer_reg[i] + sample_reg;
+ end
+ buffer_next[0] = sample_reg;
+ dead_next = 1'b0;
+ end
+
+ state_next = 3'd2;
+
+ // skip 32 samples after peak
+ if (counter_max)
+ begin
+ if (uwt_flag[0])
+ begin
+ counter_next = 5'd0;
+ state_next = 3'd4;
+ end
+ end
+ else
+ begin
+ counter_next = counter_reg + 5'd1;
+ end
+ end
+
+ 4:
+ begin
+ good_next = dead_reg;
+ state_next = 2'd2;
+ end
+ endcase
+ end
+
+ assign ana_dead = dead_reg;
+ assign ana_good = good_reg;
+ assign ana_data = data_reg;
+ assign ana_base = baseline;
+
+endmodule
Index: sandbox/MultiChannelUSB/configuration.v
===================================================================
--- sandbox/MultiChannelUSB/configuration.v (revision 106)
+++ sandbox/MultiChannelUSB/configuration.v (revision 106)
@@ -0,0 +1,82 @@
+module configuration
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [4:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire [511:0] cfg_bits
+ );
+
+ wire [31:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+ reg [15:0] int_miso_reg;
+
+ wire [511:0] int_bits_wire;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 32; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(int_bits_wire[j*16+15:j*16]),
+ .aclr(),
+ .aload(),
+ .aset(),
+ .sload(),
+ .sset());
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(32),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(5)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(int_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(32),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(5)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cfg_bits = int_bits_wire;
+
+endmodule
Index: sandbox/MultiChannelUSB/control.v
===================================================================
--- sandbox/MultiChannelUSB/control.v (revision 106)
+++ sandbox/MultiChannelUSB/control.v (revision 106)
@@ -0,0 +1,260 @@
+module control
+ (
+ input wire clock, reset,
+
+ input wire rx_empty, tx_full,
+ input wire [7:0] rx_data,
+
+ output wire rx_rdreq, tx_wrreq,
+ output wire [7:0] tx_data,
+
+ output wire bus_wren,
+ output wire [31:0] bus_addr,
+ output wire [15:0] bus_mosi,
+
+ input wire [15:0] bus_miso,
+ input wire bus_busy,
+
+ output wire led
+ );
+
+ reg [23:0] led_counter;
+
+ reg int_bus_wren;
+ reg [31:0] int_bus_addr;
+ reg [31:0] int_bus_cntr;
+ reg [15:0] int_bus_mosi;
+
+ reg int_rdreq, int_wrreq;
+ reg [7:0] int_data;
+ reg int_led;
+
+ reg [1:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ reg [4:0] state;
+
+ reg [31:0] address, counter;
+
+ reg [15:0] prefix;
+
+ wire [15:0] dest, data;
+
+ reg [7:0] buffer [3:0];
+
+ assign dest = {buffer[0], buffer[1]};
+ assign data = {buffer[2], buffer[3]};
+
+ always @(posedge clock)
+ begin
+ if (~rx_empty)
+ begin
+ int_led <= 1'b0;
+ led_counter <= 24'd0;
+ end
+ else
+ begin
+ if (&led_counter)
+ begin
+ int_led <= 1'b1;
+ end
+ else
+ begin
+ led_counter <= led_counter + 24'd1;
+ end
+ end
+
+ case(state)
+ 0:
+ begin
+ int_rdreq <= 1'b1;
+ int_wrreq <= 1'b0;
+ idle_counter <= 5'd0;
+ byte_counter <= 2'd0;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ // read 4 bytes
+ if (~rx_empty)
+ begin
+ idle_counter <= 5'd0;
+ byte_counter <= byte_counter + 2'd1;
+ buffer[byte_counter] <= rx_data;
+ if (&byte_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+ else if(|byte_counter)
+ begin
+ idle_counter <= idle_counter + 5'd1;
+ if (&idle_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+ end
+
+ 2:
+ begin
+ case (dest)
+ 16'h0000:
+ begin
+ // reset
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+
+ 16'h0001:
+ begin
+ // prefix register
+ prefix <= data;
+ state <= 5'd0;
+ end
+
+
+ 16'h0002:
+ begin
+ // address register
+ address <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0003:
+ begin
+ // counter register
+ counter <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0004:
+ begin
+ // single write
+ int_bus_addr <= address;
+ int_bus_mosi <= data;
+ int_bus_wren <= 1'b1;
+ prefix <= 16'd0;
+ state <= 5'd3;
+ end
+
+ 16'h0005:
+ begin
+ // multi read
+ int_bus_addr <= address;
+ int_bus_cntr <= counter;
+ int_bus_wren <= 1'b0;
+ prefix <= 16'd0;
+ state <= 5'd4;
+ end
+
+ default:
+ begin
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ // single write
+ 3:
+ begin
+ if (~bus_busy)
+ begin
+ int_bus_addr <= 32'd0;
+ int_bus_mosi <= 16'd0;
+ int_bus_wren <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+
+ // multi read
+ 4:
+ begin
+ if (bus_busy)
+ begin
+ buffer[0] <= 8'd1;
+ buffer[1] <= 8'd0;
+ int_bus_cntr <= 32'd0;
+ end
+ else
+ begin
+ buffer[0] <= 8'd0;
+ buffer[1] <= 8'd0;
+ end
+ state <= 5'd7;
+ end
+
+ 5:
+ begin
+ buffer[0] <= bus_miso[7:0];
+ buffer[1] <= bus_miso[15:8];
+ int_bus_addr <= int_bus_addr + 32'd1;
+ int_bus_cntr <= int_bus_cntr - 32'd1;
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_data <= buffer[0];
+ int_wrreq <= 1'b1;
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ if (~tx_full)
+ begin
+ int_data <= buffer[1];
+ state <= 5'd9;
+ end
+ end
+
+ 9:
+ begin
+ if (~tx_full)
+ begin
+ int_wrreq <= 1'b0;
+ state <= 5'd10;
+ end
+ end
+
+ 10:
+ begin
+ if (|int_bus_cntr)
+ begin
+ state <= 5'd5;
+ end
+ else
+ begin
+ state <= 5'd0;
+ end
+ end
+
+ default:
+ begin
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ assign bus_wren = int_bus_wren;
+ assign bus_addr = int_bus_addr;
+ assign bus_mosi = int_bus_mosi;
+ assign rx_rdreq = int_rdreq & (~rx_empty);
+ assign tx_wrreq = int_wrreq & (~tx_full);
+ assign tx_data = int_data;
+ assign led = int_led;
+
+endmodule
Index: sandbox/MultiChannelUSB/counter.v
===================================================================
--- sandbox/MultiChannelUSB/counter.v (revision 106)
+++ sandbox/MultiChannelUSB/counter.v (revision 106)
@@ -0,0 +1,111 @@
+module counter
+ (
+ input wire clock, frame, reset,
+
+ input wire [15:0] cfg_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [1:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire cnt_good
+ );
+
+ wire [3:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+
+ reg cnt_good_reg;
+ reg [15:0] int_miso_reg;
+
+ wire [63:0] reg_bits_wire;
+ wire [63:0] cnt_bits_wire;
+
+ integer i;
+ genvar j;
+
+ lpm_counter #(
+ .lpm_direction("DOWN"),
+ .lpm_port_updown("PORT_UNUSED"),
+ .lpm_type("LPM_COUNTER"),
+ .lpm_width(64)) lpm_counter_component (
+ .sload(cfg_data[0]),
+ .sclr(reset),
+ .clock(clock),
+ .data(reg_bits_wire),
+// .cnt_en(frame & cfg_data[1]),
+ .cnt_en((frame) & (|cnt_bits_wire) & (cfg_data[1])),
+ .q(cnt_bits_wire),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .cout(),
+ .eq(),
+ .sset(1'b0),
+ .updown(1'b1));
+
+ generate
+ for (j = 0; j < 4; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(reg_bits_wire[j*16+15:j*16]),
+ .aclr(),
+ .aload(),
+ .aset(),
+ .sload(),
+ .sset());
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(2)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(cnt_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(4),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(2)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ cnt_good_reg <= 1'b0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ cnt_good_reg <= (|cnt_bits_wire) & (cfg_data[1]);
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cnt_good = cnt_good_reg;
+
+endmodule
Index: sandbox/MultiChannelUSB/histogram.v
===================================================================
--- sandbox/MultiChannelUSB/histogram.v (revision 106)
+++ sandbox/MultiChannelUSB/histogram.v (revision 106)
@@ -0,0 +1,199 @@
+module histogram
+ (
+ input wire clock, frame, reset,
+
+ input wire hst_good,
+ input wire [11:0] hst_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [12:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+ // signal declaration
+ reg [3:0] int_case_reg, int_case_next;
+ reg int_wren_reg, int_wren_next;
+ reg [11:0] int_addr_reg, int_addr_next;
+ reg [31:0] int_data_reg, int_data_next;
+
+ reg [12:0] bus_addr_reg, bus_addr_next;
+ reg [15:0] bus_miso_reg, bus_miso_next;
+
+ reg bus_wren_reg, bus_wren_next;
+ reg [15:0] bus_mosi_reg, bus_mosi_next;
+
+ wire [31:0] q_a_wire;
+ wire [15:0] q_b_wire;
+
+ altsyncram #(
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_a("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .indata_reg_b("CLOCK0"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(4096),
+ .numwords_b(8192),
+ .operation_mode("BIDIR_DUAL_PORT"),
+ .outdata_aclr_a("NONE"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_a("CLOCK0"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("OLD_DATA"),
+ .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
+ .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
+ .widthad_a(12),
+ .widthad_b(13),
+ .width_a(32),
+ .width_b(16),
+ .width_byteena_a(1),
+ .width_byteena_b(1),
+ .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .wren_b(bus_wren_reg),
+ .address_a(int_addr_reg),
+ .address_b(bus_addr_reg),
+ .data_a(int_data_reg),
+ .data_b(bus_mosi_reg),
+ .q_a(q_a_wire),
+ .q_b(q_b_wire),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .eccstatus(),
+ .rden_a(1'b1),
+ .rden_b(1'b1));
+
+ // body
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_addr_reg <= 12'd0;
+ int_data_reg <= 32'd0;
+ int_case_reg <= 4'b0;
+ bus_addr_reg <= 13'd0;
+ bus_miso_reg <= 16'd0;
+ bus_wren_reg <= 1'b0;
+ bus_mosi_reg <= 16'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_addr_reg <= int_addr_next;
+ int_data_reg <= int_data_next;
+ int_case_reg <= int_case_next;
+ bus_addr_reg <= bus_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_wren_reg <= bus_wren_next;
+ bus_mosi_reg <= bus_mosi_next;
+ end
+ end
+
+ always @*
+ begin
+ bus_addr_next = bus_addr_reg;
+ bus_miso_next = bus_miso_reg;
+
+ bus_wren_next = 1'b0;
+ bus_mosi_next = bus_mosi_reg;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = q_b_wire;
+ bus_addr_next = bus_addr;
+ bus_wren_next = bus_wren;
+ if (bus_wren)
+ begin
+ bus_mosi_next = bus_mosi;
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_addr_next = int_addr_reg;
+ int_data_next = int_data_reg;
+ int_case_next = int_case_reg;
+
+ case (int_case_reg)
+
+ 0:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 12'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_case_next = 4'd1;
+ end
+ end
+
+ 1:
+ begin
+ int_wren_next = 1'b0;
+/*
+ if (&int_data_reg)
+ begin
+ int_case_next = 4'd0;
+ end
+ else if (frame & hst_good)
+*/
+ if (frame & hst_good)
+ begin
+ int_addr_next = hst_data;
+ int_case_next = 4'd2;
+ end
+ end
+
+ 2:
+ begin
+ int_case_next = 4'd3;
+ end
+
+ 3:
+ begin
+ int_case_next = 4'd4;
+ end
+
+ 4:
+ begin
+ int_case_next = 4'd1;
+ if (~&q_a_wire)
+ begin
+ int_wren_next = 1'b1;
+ int_data_next = q_a_wire + 32'd1;
+ end
+ end
+
+ default:
+ begin
+ int_wren_next = 1'b0;
+ int_addr_next = 12'd0;
+ int_data_next = 32'd0;
+ int_case_next = 4'd0;
+ end
+ endcase
+ end
+
+ // output logic
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = 1'b0;
+endmodule
Index: sandbox/MultiChannelUSB/i2c_fifo.v
===================================================================
--- sandbox/MultiChannelUSB/i2c_fifo.v (revision 106)
+++ sandbox/MultiChannelUSB/i2c_fifo.v (revision 106)
@@ -0,0 +1,219 @@
+module i2c_fifo
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [15:0] bus_mosi,
+
+ output wire bus_busy,
+
+ inout wire i2c_sda,
+ inout wire i2c_scl
+ );
+
+ wire int_rdempty, int_wrfull, i2c_clk, start, stop;
+ wire [15:0] int_q;
+
+ reg int_bus_busy;
+ reg int_rdreq, int_wrreq, int_clken, int_sdo, int_scl, int_ack;
+ reg [15:0] int_bus_mosi;
+ reg [15:0] int_data;
+ reg [9:0] counter;
+ reg [4:0] state;
+
+ assign i2c_sda = int_sdo ? 1'bz : 1'b0;
+ assign i2c_scl = int_scl | (int_clken ? counter[9] : 1'b0);
+
+ assign start = int_data[8];
+ assign stop = int_data[9];
+
+ scfifo #(
+ .add_ram_output_register("OFF"),
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("scfifo"),
+ .lpm_width(16),
+ .lpm_widthu(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF")) fifo_tx (
+ .rdreq((~int_rdempty) & (int_rdreq) & (&counter)),
+ .aclr(1'b0),
+ .clock(clock),
+ .wrreq(int_wrreq),
+ .data(int_bus_mosi),
+ .empty(int_rdempty),
+ .q(int_q),
+ .full(int_wrfull),
+ .almost_empty(),
+ .almost_full(),
+ .sclr(),
+ .usedw());
+
+ always @ (posedge clock)
+ begin
+ int_bus_busy <= int_wrfull;
+
+ if (bus_ssel)
+ begin
+ if (~int_wrfull & bus_wren)
+ begin
+ int_bus_mosi <= bus_mosi;
+ int_wrreq <= 1'b1;
+ end
+ end
+
+ if (~int_wrfull & int_wrreq)
+ begin
+ int_wrreq <= 1'b0;
+ end
+
+ end
+
+ always @ (posedge clock)
+ begin
+ counter <= counter + 10'd1;
+ if (&counter)
+ begin
+ case (state)
+ 0:
+ begin
+ int_ack <= 1'b0;
+ int_sdo <= 1'b1;
+ int_scl <= 1'b1;
+ int_rdreq <= 1'b1;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+
+ 2:
+ begin
+ if (start)
+ begin
+ int_sdo <= 1'b1;
+ int_scl <= 1'b1;
+ state <= 5'd3;
+ end
+ else
+ begin
+ state <= 5'd5;
+ end
+ end
+
+ 3:
+ begin // start
+ int_sdo <= 1'b0;
+ state <= 5'd4;
+ end
+
+ 4:
+ begin
+ int_scl <= 1'b0;
+ state <= 5'd5;
+ end
+
+ 5:
+ begin // data
+ int_clken <= 1'b1;
+ int_sdo <= int_data[7];
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ int_sdo <= int_data[6];
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_sdo <= int_data[5];
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ int_sdo <= int_data[4];
+ state <= 5'd9;
+ end
+
+ 9:
+ begin
+ int_sdo <= int_data[3];
+ state <= 5'd10;
+ end
+
+ 10:
+ begin
+ int_sdo <= int_data[2];
+ state <= 5'd11;
+ end
+
+ 11:
+ begin
+ int_sdo <= int_data[1];
+ state <= 5'd12;
+ end
+
+ 12:
+ begin
+ int_sdo <= int_data[0];
+ state <= 5'd13;
+ end
+
+ 13:
+ begin // ack
+ int_sdo <= 1'b1;
+ int_rdreq <= 1'b1;
+ state <= 5'd14;
+ end
+
+ 14:
+ begin
+ int_ack <= i2c_sda;
+ int_rdreq <= 1'b0;
+ if (stop | int_rdempty)
+ begin
+ int_clken <= 1'b0;
+ int_sdo <= 1'b0;
+ int_scl <= 1'b0;
+ state <= 5'd15;
+ end
+ else if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_sdo <= int_q[7];
+ state <= 5'd6;
+ end
+ end
+
+ 15:
+ begin // stop
+ int_scl <= 1'b1;
+ state <= 5'd16;
+ end
+
+ 16:
+ begin
+ int_sdo <= 1'b1;
+ state <= 5'd0;
+ end
+
+ endcase
+ end
+ end
+
+ // output logic
+ assign bus_busy = int_bus_busy;
+
+endmodule
Index: sandbox/MultiChannelUSB/oscilloscope.v
===================================================================
--- sandbox/MultiChannelUSB/oscilloscope.v (revision 106)
+++ sandbox/MultiChannelUSB/oscilloscope.v (revision 106)
@@ -0,0 +1,246 @@
+module oscilloscope
+ (
+ input wire clock, frame, reset,
+
+ input wire cfg_data,
+
+ input wire trg_flag,
+
+ input wire [63:0] osc_data,
+
+ output wire ram_wren,
+ output wire [19:0] ram_addr,
+ inout wire [17:0] ram_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [19:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+
+ reg [63:0] osc_data_reg, osc_data_next;
+
+ reg [2:0] int_case_reg, int_case_next;
+
+ reg int_trig_reg, int_trig_next;
+ reg [19:0] int_trig_addr_reg, int_trig_addr_next;
+
+ reg [19:0] int_cntr_reg [1:0];
+ reg [19:0] int_cntr_next [1:0];
+
+ reg [15:0] bus_miso_reg, bus_miso_next;
+ reg bus_busy_reg, bus_busy_next;
+
+ reg ram_wren_reg [2:0];
+ reg ram_wren_next [2:0];
+
+ reg [17:0] ram_data_reg [2:0];
+ reg [17:0] ram_data_next [2:0];
+
+ reg [19:0] ram_addr_reg, ram_addr_next;
+
+ wire [17:0] ram_wren_wire;
+
+ assign ram_wren = ~ram_wren_reg[0];
+ assign ram_addr = ram_addr_reg;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 18; j = j + 1)
+ begin : SRAM_WREN
+ assign ram_wren_wire[j] = ram_wren_reg[2];
+ assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz;
+ end
+ endgenerate
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ osc_data_reg <= 64'd0;
+ ram_addr_reg <= 20'd0;
+ bus_miso_reg <= 16'd0;
+ bus_busy_reg <= 1'b0;
+ int_case_reg <= 5'd0;
+ int_cntr_reg[0] <= 20'd0;
+ int_cntr_reg[1] <= 20'd0;
+ int_trig_reg <= 1'b0;
+ int_trig_addr_reg <= 20'd0;
+
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ ram_wren_reg[i] <= 1'b0;
+ ram_data_reg[i] <= 16'd0;
+ end
+ end
+ else
+ begin
+ osc_data_reg <= osc_data_next;
+ ram_addr_reg <= ram_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_busy_reg <= bus_busy_next;
+ int_case_reg <= int_case_next;
+ int_cntr_reg[0] <= int_cntr_next[0];
+ int_cntr_reg[1] <= int_cntr_next[1];
+ int_trig_reg <= int_trig_next;
+ int_trig_addr_reg <= int_trig_addr_next;
+
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ ram_wren_reg[i] <= ram_wren_next[i];
+ ram_data_reg[i] <= ram_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+
+ osc_data_next = osc_data_reg;
+ ram_addr_next = ram_addr_reg;
+ bus_miso_next = bus_miso_reg;
+ bus_busy_next = bus_busy_reg;
+ int_case_next = int_case_reg;
+ int_cntr_next[0] = int_cntr_reg[0];
+ int_cntr_next[1] = int_cntr_reg[1];
+ int_trig_next = int_trig_reg;
+ int_trig_addr_next = int_trig_addr_reg;
+
+ for(i = 0; i < 2; i = i + 1)
+ begin
+ ram_wren_next[i+1] = ram_wren_reg[i];
+ ram_data_next[i+1] = ram_data_reg[i];
+ end
+ ram_wren_next[0] = 1'b0;
+ ram_data_next[0] = 18'd0;
+
+ case (int_case_reg)
+ 0:
+ begin
+ bus_busy_next = 1'b0;
+ int_cntr_next[0] = 20'd0;
+ int_cntr_next[1] = 20'd0;
+ int_trig_next = 1'b0;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = {ram_data[17:10], ram_data[8:1]};
+ ram_wren_next[0] = bus_wren;
+ if (bus_wren)
+ begin
+ ram_addr_next = bus_addr;
+ ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0};
+ end
+ else
+ begin
+ ram_addr_next = int_trig_addr_reg + bus_addr;
+// ram_addr_next = bus_addr;
+ end
+ end
+ else if (cfg_data)
+ begin
+ // start recording
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = 18'd0;
+ ram_addr_next = 20'd0;
+ bus_busy_next = 1'b1;
+ int_case_next = 3'd1;
+ int_trig_addr_next = 20'd0;
+// int_cntr_next[0] = {cfg_data[7:0], 10'd0};
+ int_cntr_next[0] = 20'd262143;
+// int_cntr_next[1] = {cfg_data[15:8], 10'd0};
+ int_cntr_next[1] = 20'd5000;
+ end
+
+ end
+
+ // write zeros
+ 1:
+ begin
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = 18'd2;
+ if(&ram_addr_reg)
+ begin
+ int_case_next = 3'd2;
+ end
+ else
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ end
+ end
+
+ // sample recording
+ 2:
+ begin
+ if (frame)
+ begin
+ osc_data_next = osc_data;
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data[15:8], 1'b0, osc_data[7:0], 1'b0};
+
+ int_case_next = 3'd3;
+
+ if (|int_cntr_reg[1])
+ begin
+ int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+ int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
+ end
+ else if (int_trig_reg)
+ begin
+ if (|int_cntr_reg[0])
+ begin
+ int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+ end
+ end
+ else if (trg_flag)
+ begin
+ int_trig_next = 1'b1;
+ int_trig_addr_next = ram_addr_reg - 20'd19999;
+ end
+ end
+ end
+
+ 3:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
+ int_case_next = 3'd4;
+ end
+
+ 4:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
+ int_case_next = 3'd5;
+ end
+
+ 5:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data_reg[63:56], 1'b0, osc_data_reg[55:48], 1'b0};
+ if (|int_cntr_reg[0])
+ begin
+ int_case_next = 3'd2;
+ end
+ else
+ begin
+ int_case_next = 3'd0;
+ end
+ end
+
+ endcase
+ end
+
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = bus_busy_reg;
+
+endmodule
Index: sandbox/MultiChannelUSB/sys_pll.v
===================================================================
--- sandbox/MultiChannelUSB/sys_pll.v (revision 106)
+++ sandbox/MultiChannelUSB/sys_pll.v (revision 106)
@@ -0,0 +1,145 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: sys_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sys_pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 10,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 17,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+endmodule
Index: sandbox/MultiChannelUSB/test.v
===================================================================
--- sandbox/MultiChannelUSB/test.v (revision 106)
+++ sandbox/MultiChannelUSB/test.v (revision 106)
@@ -0,0 +1,418 @@
+module test
+ (
+ input wire clk,
+ output wire [11:0] data
+ );
+
+ reg [11:0] int_data;
+ reg [15:0] counter;
+// reg [5:0] counter;
+ reg [5:0] state;
+
+ always @(posedge clk)
+ begin
+ case (state)
+/*
+ 0:
+ begin
+ int_data <= 12'd0;
+ state <= 6'd1;
+ end
+
+ 1:
+ begin
+ int_data <= 12'd1024;
+ state <= 6'd2;
+ end
+
+ 2:
+ begin
+ int_data <= 12'd2048;
+ state <= 6'd3;
+ end
+
+ 3:
+ begin
+ int_data <= 12'd3072;
+ state <= 6'd4;
+ end
+
+ 4:
+ begin
+ int_data <= 12'd4095;
+ state <= 6'd5;
+ end
+
+ 5:
+ begin
+ int_data <= 12'd3072;
+ state <= 6'd6;
+ end
+
+ 6:
+ begin
+ int_data <= 12'd2048;
+ state <= 6'd7;
+ end
+
+ 7:
+ begin
+ int_data <= 12'd1024;
+ state <= 6'd8;
+ end
+
+ 8:
+ begin
+ int_data <= 12'd0;
+ counter <= counter + 6'd1;
+ if (&counter)
+ begin
+ state <= 6'd0;
+ end
+ end
+*/
+
+ 6'd0:
+ begin
+ int_data <= 12'h030;
+ state <= 6'd1;
+ end
+
+ 6'd1:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd2;
+ end
+
+ 6'd2:
+ begin
+ int_data <= 12'h081;
+ state <= 6'd3;
+ end
+
+ 6'd3:
+ begin
+ int_data <= 12'h0f5;
+ state <= 6'd4;
+ end
+
+ 6'd4:
+ begin
+ int_data <= 12'h10a;
+ state <= 6'd5;
+ end
+
+ 6'd5:
+ begin
+ int_data <= 12'h11a;
+ state <= 6'd6;
+ end
+
+ 6'd6:
+ begin
+ int_data <= 12'h124;
+ state <= 6'd7;
+ end
+
+ 6'd7:
+ begin
+ int_data <= 12'h124;
+ state <= 6'd8;
+ end
+
+ 6'd8:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd9;
+ end
+
+ 6'd9:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd10;
+ end
+
+ 6'd10:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd11;
+ end
+
+ 6'd11:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd12;
+ end
+
+ 6'd12:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd13;
+ end
+
+ 6'd13:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd14;
+ end
+
+ 6'd14:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd15;
+ end
+
+ 6'd15:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd16;
+ end
+
+ 6'd16:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd17;
+ end
+
+ 6'd17:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd18;
+ end
+
+ 6'd18:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd19;
+ end
+
+ 6'd19:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd20;
+ end
+
+ 6'd20:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd21;
+ end
+
+ 6'd21:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd22;
+ end
+
+ 6'd22:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd23;
+ end
+
+ 6'd23:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd24;
+ end
+
+ 6'd24:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd25;
+ end
+
+ 6'd25:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd26;
+ end
+
+ 6'd26:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd27;
+ end
+
+ 6'd27:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd28;
+ end
+
+ 6'd28:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd29;
+ end
+
+ 6'd29:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd30;
+ end
+
+ 6'd30:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd31;
+ end
+
+ 6'd31:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd32;
+ end
+
+ 6'd32:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd33;
+ end
+
+ 6'd33:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd34;
+ end
+
+ 6'd34:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd35;
+ end
+
+ 6'd35:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd36;
+ end
+
+ 6'd36:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd37;
+ end
+
+ 6'd37:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd38;
+ end
+
+ 6'd38:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd39;
+ end
+
+ 6'd39:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd40;
+ end
+
+ 6'd40:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd41;
+ end
+
+ 6'd41:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd42;
+ end
+
+ 6'd42:
+ begin
+ int_data <= 12'h0fb;
+ state <= 6'd43;
+ end
+
+ 6'd43:
+ begin
+ int_data <= 12'h07e;
+ state <= 6'd44;
+ end
+
+ 6'd44:
+ begin
+ int_data <= 12'h070;
+ state <= 6'd45;
+ end
+
+ 6'd45:
+ begin
+ int_data <= 12'h05a;
+ state <= 6'd46;
+ end
+
+ 6'd46:
+ begin
+ int_data <= 12'h045;
+ state <= 6'd47;
+ end
+
+ 6'd47:
+ begin
+ int_data <= 12'h03f;
+ state <= 6'd48;
+ end
+
+ 6'd48:
+ begin
+ int_data <= 12'h03b;
+ state <= 6'd49;
+ end
+
+ 6'd49:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd50;
+ end
+
+ 6'd50:
+ begin
+ int_data <= 12'h035;
+ state <= 6'd51;
+ end
+
+ 6'd51:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd52;
+ end
+
+ 6'd52:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd53;
+ end
+
+ 6'd53:
+ begin
+ int_data <= 12'h030;
+ state <= 6'd54;
+ end
+
+ 6'd54:
+ begin
+ int_data <= 12'h030;
+ counter <= counter + 16'd1;
+ if (&counter)
+ begin
+ state <= 6'd0;
+ end
+ end
+
+ default:
+ begin
+ state <= 6'd0;
+ end
+ endcase
+ end
+
+ assign data = int_data;
+
+endmodule
Index: sandbox/MultiChannelUSB/test_pll.v
===================================================================
--- sandbox/MultiChannelUSB/test_pll.v (revision 106)
+++ sandbox/MultiChannelUSB/test_pll.v (revision 106)
@@ -0,0 +1,145 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: test_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module test_pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 5,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+endmodule
Index: sandbox/MultiChannelUSB/trigger.v
===================================================================
--- sandbox/MultiChannelUSB/trigger.v (revision 106)
+++ sandbox/MultiChannelUSB/trigger.v (revision 106)
@@ -0,0 +1,32 @@
+module trigger
+ (
+ input wire clock, frame, reset,
+ input wire [11:0] cfg_data,
+ input wire [11:0] trg_data,
+ output wire trg_flag
+ );
+
+ reg trg_flag_reg;
+ reg [11:0] cfg_data_reg;
+ reg [11:0] trg_data_reg;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ trg_flag_reg <= 1'b0;
+ end
+ else
+ begin
+ if (frame)
+ begin
+ cfg_data_reg <= cfg_data;
+ trg_data_reg <= trg_data;
+ end
+ trg_flag_reg <= (trg_data_reg >= cfg_data_reg);
+ end
+ end
+
+ assign trg_flag = trg_flag_reg;
+
+endmodule
Index: sandbox/MultiChannelUSB/usb_fifo.v
===================================================================
--- sandbox/MultiChannelUSB/usb_fifo.v (revision 106)
+++ sandbox/MultiChannelUSB/usb_fifo.v (revision 106)
@@ -0,0 +1,121 @@
+module usb_fifo
+ (
+ input wire usb_clock,
+ inout wire [7:0] usb_data,
+ input wire usb_full, usb_empty,
+ output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
+ output wire [1:0] usb_addr,
+
+ input wire clock,
+ input wire tx_wrreq, rx_rdreq,
+ input wire [7:0] tx_data,
+ output wire tx_full, rx_empty,
+ output wire [7:0] rx_q
+ );
+
+ wire int_rx_full, int_tx_empty;
+ wire rx_ready, tx_ready;
+ wire int_rdreq, int_wrreq, int_pktend;
+ reg is_rx_addr_ok;
+ reg [8:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ wire [7:0] int_rx_data = usb_data;
+ wire [7:0] int_tx_q;
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF"),
+ .write_aclr_synch("OFF")) fifo_tx (
+ .aclr(1'b0),
+ .data(tx_data),
+ .rdclk(usb_clock),
+ .rdreq(int_wrreq),
+ .wrclk(clock),
+ .wrreq(tx_wrreq),
+ .q(int_tx_q),
+ .rdempty(int_tx_empty),
+ .wrfull(tx_full),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF"),
+ .write_aclr_synch("OFF")) fifo_rx (
+ .aclr(1'b0),
+ .data(int_rx_data),
+ .rdclk(clock),
+ .rdreq(rx_rdreq),
+ .wrclk(usb_clock),
+ .wrreq(int_rdreq),
+ .q(rx_q),
+ .rdempty(rx_empty),
+ .wrfull(int_rx_full),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ assign rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);
+ assign tx_ready = (~rx_ready) & (~usb_full) & (~int_tx_empty) & (~int_pktend);
+
+ assign int_rdreq = (rx_ready) & (is_rx_addr_ok);
+ assign int_wrreq = (tx_ready) & (~is_rx_addr_ok);
+
+ assign int_pktend = (&idle_counter);
+
+ always @ (posedge usb_clock)
+ begin
+ // respect 1 clock delay between fifo selection
+ // and data transfer operations
+ is_rx_addr_ok <= rx_ready;
+
+ // assert pktend if buffer contains unsent data
+ // and fifo_tx_unit stays empty for more than 30 clocks
+ if (int_pktend)
+ begin
+ byte_counter <= 9'd0;
+ idle_counter <= 5'd0;
+ end
+ else if (int_wrreq)
+ begin
+ byte_counter <= byte_counter + 9'd1;
+ idle_counter <= 5'd0;
+ end
+ else if ((|byte_counter) & (int_tx_empty) & (~rx_ready))
+ begin
+ byte_counter <= byte_counter;
+ idle_counter <= idle_counter + 5'd1;
+ end
+
+ end
+
+ assign usb_pktend = int_pktend;
+ assign usb_rdreq = int_rdreq;
+ assign usb_wrreq = int_wrreq;
+ assign usb_rden = int_rdreq;
+ assign usb_addr = {1'b1, ~rx_ready};
+ assign usb_data = int_wrreq ? int_tx_q : 8'bz;
+
+endmodule
Index: sandbox/MultiChannelUSB/uwt_bior31.v
===================================================================
--- sandbox/MultiChannelUSB/uwt_bior31.v (revision 106)
+++ sandbox/MultiChannelUSB/uwt_bior31.v (revision 106)
@@ -0,0 +1,116 @@
+module uwt_bior31
+ #(
+ parameter L = 1 // transform level
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [31:0] x,
+ output wire [31:0] d,
+ output wire [31:0] a,
+ output wire [31:0] peak,
+ output wire [1:0] flag
+ );
+
+ localparam index1 = 1 << (L - 1);
+ localparam index2 = 2 << (L - 1);
+ localparam index3 = 3 << (L - 1);
+ localparam index4 = index3 + 1;
+ localparam peak_index = ((index3 + 1) >> 1) + 2;
+ localparam peak_shift = ((L - 1) << 1) + (L - 1);
+ localparam zero = 32'h80000000;
+
+ // Tapped delay line
+ reg [31:0] tap [index4:0];
+
+ reg [31:0] d_reg, d_next;
+ reg [31:0] a_reg, a_next;
+ reg [31:0] peak_reg, peak_next;
+
+ reg [31:0] tmp1_reg, tmp1_next;
+ reg [31:0] tmp2_reg, tmp2_next;
+
+ reg less_reg, less_next;
+ reg more_reg, more_next;
+
+ reg [1:0] flag_reg;
+
+ integer i;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ d_reg <= 0;
+ a_reg <= 0;
+ peak_reg <= 0;
+ flag_reg <= 0;
+ tmp1_reg <= 0;
+ tmp2_reg <= 0;
+ less_reg <= 1'b0;
+ more_reg <= 1'b0;
+
+ for(i = 0; i <= index4; i = i + 1)
+ begin
+ tap[i] <= 0;
+ end
+ end
+ else if (frame)
+ begin
+ d_reg <= d_next;
+ a_reg <= a_next;
+ peak_reg <= peak_next;
+
+ tmp1_reg <= tmp1_next;
+ tmp2_reg <= tmp2_next;
+ less_reg <= less_next;
+ more_reg <= more_next;
+
+ flag_reg[0] <= (more_reg) & (~more_next);
+ flag_reg[1] <= (less_reg) & (~less_next);
+
+ // Tapped delay line: shift one
+ for(i = 0; i < index4; i = i + 1)
+ begin
+ tap[i+1] <= tap[i];
+ end
+
+ // Input in register 0
+ tap[0] <= x;
+ end
+ end
+
+ always @*
+ begin
+ // Compute d and a with the filter coefficients.
+ // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1]
+
+ tmp1_next = tap[index3] + {tap[index2][30:0], 1'b0} + tap[index2];
+ tmp2_next = {tap[index1][30:0], 1'b0} + tap[index1] + tap[0];
+
+ d_next = zero - tmp1_reg + tmp2_reg;
+ a_next = tmp1_reg + tmp2_reg;
+
+ more_next = (d_reg > zero);
+ less_next = (d_reg < zero);
+
+/*
+ d_next = zero - (tap[index3])
+ - (tap[index2] << 1) - tap[index2]
+ + (tap[index1] << 1) + tap[index1]
+ + (tap[0]);
+
+ a_next = (tap[index3])
+ + {tap[index2] << 1} + tap[index2]
+ + (tap[index1] << 1) + tap[index1]
+ + (tap[0]);
+*/
+ peak_next = (tap[peak_index] >> peak_shift);
+ end
+
+ // output logic
+ assign d = d_reg;
+ assign a = a_reg;
+ assign peak = peak_reg;
+ assign flag = flag_reg;
+
+endmodule