Index: trunk/Octopus/Octopus.cof
===================================================================
--- trunk/Octopus/Octopus.cof (revision 102)
+++ trunk/Octopus/Octopus.cof (revision 102)
@@ -0,0 +1,18 @@
+
+
+ EPCS16
+ EP3C25
+ Octopus.jic
+ 1
+ 1
+ 7
+
+ 1
+
+ Octopus.sof
+
+
+ 4
+
+
+
Index: trunk/Octopus/Octopus.dpf
===================================================================
--- trunk/Octopus/Octopus.dpf (revision 102)
+++ trunk/Octopus/Octopus.dpf (revision 102)
@@ -0,0 +1,50 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: trunk/Octopus/Octopus.qpf
===================================================================
--- trunk/Octopus/Octopus.qpf (revision 102)
+++ trunk/Octopus/Octopus.qpf (revision 102)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "10:10:10 March 22, 2010"
+
+# Revisions
+
+PROJECT_REVISION = "Octopus"
Index: trunk/Octopus/Octopus.qsf
===================================================================
--- trunk/Octopus/Octopus.qsf (revision 102)
+++ trunk/Octopus/Octopus.qsf (revision 102)
@@ -0,0 +1,302 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 14:14:14 August 28, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# Octopus_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY Octopus
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:14 MARCH 17, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION 9.0
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name MISC_FILE Octopus.dpf
+set_global_assignment -name VERILOG_FILE Octopus.v
+set_global_assignment -name VERILOG_FILE adc_lvds.v
+set_global_assignment -name VERILOG_FILE adc_pll.v
+set_global_assignment -name VERILOG_FILE sys_pll.v
+set_global_assignment -name VERILOG_FILE control.v
+set_global_assignment -name VERILOG_FILE uwt_bior31.v
+set_global_assignment -name VERILOG_FILE analyser.v
+set_global_assignment -name VERILOG_FILE counter.v
+set_global_assignment -name VERILOG_FILE histogram.v
+set_global_assignment -name VERILOG_FILE trigger.v
+set_global_assignment -name VERILOG_FILE oscilloscope.v
+set_global_assignment -name VERILOG_FILE configuration.v
+set_global_assignment -name VERILOG_FILE usb_fifo.v
+set_global_assignment -name VERILOG_FILE i2c_fifo.v
+set_global_assignment -name VERILOG_FILE test.v
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 3
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 4
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 5
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
+set_location_assignment PIN_13 -to USB_IFCLK
+set_location_assignment PIN_18 -to USB_SLWR
+set_location_assignment PIN_21 -to USB_SLRD
+set_location_assignment PIN_37 -to USB_PA6
+set_location_assignment PIN_38 -to USB_PA5
+set_location_assignment PIN_39 -to USB_PA4
+set_location_assignment PIN_41 -to USB_PA2
+set_location_assignment PIN_43 -to USB_FLAGB
+set_location_assignment PIN_44 -to USB_FLAGA
+set_location_assignment PIN_45 -to USB_PB[7]
+set_location_assignment PIN_46 -to USB_PB[6]
+set_location_assignment PIN_49 -to USB_PB[5]
+set_location_assignment PIN_50 -to USB_PB[4]
+set_location_assignment PIN_51 -to USB_PB[0]
+set_location_assignment PIN_52 -to USB_PB[1]
+set_location_assignment PIN_55 -to USB_PB[2]
+set_location_assignment PIN_56 -to USB_PB[3]
+set_location_assignment PIN_57 -to LED
+set_location_assignment PIN_63 -to ADC_D[0]
+set_location_assignment PIN_64 -to "ADC_D[0](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[0]
+set_location_assignment PIN_71 -to ADC_D[1]
+set_location_assignment PIN_72 -to "ADC_D[1](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[1]
+set_location_assignment PIN_81 -to ADC_D[2]
+set_location_assignment PIN_82 -to "ADC_D[2](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[2]
+set_location_assignment PIN_89 -to ADC_D[3]
+set_location_assignment PIN_90 -to "ADC_D[3](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[3]
+set_location_assignment PIN_91 -to ADC_FCO
+set_location_assignment PIN_92 -to "ADC_FCO(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
+set_location_assignment PIN_93 -to ADC_D[4]
+set_location_assignment PIN_94 -to "ADC_D[4](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[4]
+set_location_assignment PIN_98 -to ADC_D[5]
+set_location_assignment PIN_99 -to "ADC_D[5](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[5]
+set_location_assignment PIN_108 -to ADC_D[6]
+set_location_assignment PIN_109 -to "ADC_D[6](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[6]
+set_location_assignment PIN_119 -to ADC_D[7]
+set_location_assignment PIN_120 -to "ADC_D[7](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to ADC_D[7]
+set_location_assignment PIN_126 -to CON_A[0]
+set_location_assignment PIN_127 -to CON_A[1]
+set_location_assignment PIN_128 -to CON_A[2]
+set_location_assignment PIN_131 -to CON_A[3]
+set_location_assignment PIN_132 -to CON_A[4]
+set_location_assignment PIN_133 -to CON_A[5]
+set_location_assignment PIN_134 -to CON_A[6]
+set_location_assignment PIN_135 -to CON_A[7]
+set_location_assignment PIN_137 -to CON_A[8]
+set_location_assignment PIN_139 -to CON_A[9]
+set_location_assignment PIN_142 -to CON_A[10]
+set_location_assignment PIN_143 -to CON_A[11]
+set_location_assignment PIN_144 -to CON_A[12]
+set_location_assignment PIN_145 -to CON_A[13]
+set_location_assignment PIN_146 -to CON_A[14]
+set_location_assignment PIN_147 -to CON_A[15]
+set_location_assignment PIN_148 -to CON_A[16]
+set_location_assignment PIN_150 -to CLK_50MHz
+set_location_assignment PIN_151 -to CON_BCLK[0]
+set_location_assignment PIN_152 -to CON_BCLK[1]
+set_location_assignment PIN_159 -to CON_B[0]
+set_location_assignment PIN_160 -to CON_B[1]
+set_location_assignment PIN_161 -to CON_B[2]
+set_location_assignment PIN_162 -to CON_B[3]
+set_location_assignment PIN_164 -to CON_B[4]
+set_location_assignment PIN_166 -to CON_B[5]
+set_location_assignment PIN_167 -to CON_B[6]
+set_location_assignment PIN_168 -to CON_B[7]
+set_location_assignment PIN_169 -to CON_B[8]
+set_location_assignment PIN_171 -to CON_B[9]
+set_location_assignment PIN_173 -to CON_B[10]
+set_location_assignment PIN_176 -to I2C_SCL
+set_location_assignment PIN_177 -to I2C_SDA
+set_location_assignment PIN_181 -to RAM_DQB[7]
+set_location_assignment PIN_182 -to RAM_ADDR[6]
+set_location_assignment PIN_183 -to RAM_ADDR[7]
+set_location_assignment PIN_184 -to RAM_CE1
+set_location_assignment PIN_186 -to RAM_CLK
+set_location_assignment PIN_187 -to RAM_WE
+set_location_assignment PIN_188 -to RAM_ADDR[8]
+set_location_assignment PIN_189 -to RAM_ADDR[9]
+set_location_assignment PIN_194 -to RAM_ADDR[10]
+set_location_assignment PIN_195 -to RAM_ADDR[11]
+set_location_assignment PIN_196 -to RAM_ADDR[12]
+set_location_assignment PIN_197 -to RAM_DQAP
+set_location_assignment PIN_200 -to RAM_DQA[0]
+set_location_assignment PIN_201 -to RAM_DQA[1]
+set_location_assignment PIN_202 -to RAM_DQA[2]
+set_location_assignment PIN_203 -to RAM_DQA[3]
+set_location_assignment PIN_207 -to RAM_DQA[4]
+set_location_assignment PIN_214 -to RAM_DQA[5]
+set_location_assignment PIN_216 -to RAM_DQA[6]
+set_location_assignment PIN_217 -to RAM_DQA[7]
+set_location_assignment PIN_218 -to RAM_ADDR[13]
+set_location_assignment PIN_219 -to RAM_ADDR[14]
+set_location_assignment PIN_221 -to RAM_ADDR[15]
+set_location_assignment PIN_223 -to RAM_ADDR[16]
+set_location_assignment PIN_224 -to RAM_ADDR[17]
+set_location_assignment PIN_226 -to RAM_ADDR[18]
+set_location_assignment PIN_230 -to RAM_ADDR[19]
+set_location_assignment PIN_231 -to RAM_ADDR[0]
+set_location_assignment PIN_232 -to RAM_ADDR[1]
+set_location_assignment PIN_233 -to RAM_ADDR[2]
+set_location_assignment PIN_234 -to RAM_ADDR[3]
+set_location_assignment PIN_235 -to RAM_ADDR[4]
+set_location_assignment PIN_236 -to RAM_ADDR[5]
+set_location_assignment PIN_237 -to RAM_DQBP
+set_location_assignment PIN_238 -to RAM_DQB[0]
+set_location_assignment PIN_239 -to RAM_DQB[1]
+set_location_assignment PIN_240 -to RAM_DQB[2]
+set_location_assignment PIN_4 -to RAM_DQB[3]
+set_location_assignment PIN_5 -to RAM_DQB[4]
+set_location_assignment PIN_6 -to RAM_DQB[5]
+set_location_assignment PIN_9 -to RAM_DQB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_IFCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLWR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SLRD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FLAGB
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PA2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_PB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_A[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_50MHz
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_BCLK[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CON_B[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_CE1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_WE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQAP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQBP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAM_DQB[7]
Index: trunk/Octopus/Octopus.v
===================================================================
--- trunk/Octopus/Octopus.v (revision 102)
+++ trunk/Octopus/Octopus.v (revision 102)
@@ -0,0 +1,380 @@
+module Octopus
+ (
+ input wire CLK_50MHz,
+ output wire LED,
+
+ input wire [16:0] CON_A,
+
+ input wire [1:0] CON_BCLK,
+ input wire [10:0] CON_B,
+ inout wire I2C_SDA,
+ inout wire I2C_SCL,
+
+// input wire ADC_DCO,
+ input wire ADC_FCO,
+ input wire [7:0] ADC_D,
+
+ output wire USB_SLRD,
+ output wire USB_SLWR,
+ input wire USB_IFCLK,
+ input wire USB_FLAGA, // EMPTY flag for EP6
+ input wire USB_FLAGB, // FULL flag for EP8
+ output wire USB_PA2,
+ output wire USB_PA4,
+ output wire USB_PA5,
+ output wire USB_PA6,
+ inout wire [7:0] USB_PB,
+
+ output wire RAM_CLK,
+ output wire RAM_CE1,
+ output wire RAM_WE,
+ output wire [19:0] RAM_ADDR,
+ inout wire RAM_DQAP,
+ inout wire [7:0] RAM_DQA,
+ inout wire RAM_DQBP,
+ inout wire [7:0] RAM_DQB
+ );
+
+ localparam N = 16;
+ localparam M = 4;
+
+ assign RAM_CLK = sys_clock;
+ assign RAM_CE1 = 1'b0;
+
+ assign USB_PA2 = ~usb_rden;
+ assign USB_PA4 = usb_addr[0];
+ assign USB_PA5 = usb_addr[1];
+ assign USB_PA6 = ~usb_pktend;
+
+ wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
+ wire usb_tx_wrreq, usb_rx_rdreq;
+ wire usb_tx_full, usb_rx_empty;
+ wire [7:0] usb_tx_data, usb_rx_data;
+ wire [1:0] usb_addr;
+
+ assign USB_SLRD = ~usb_rdreq;
+ assign USB_SLWR = ~usb_wrreq;
+
+ usb_fifo usb_unit
+ (
+ .usb_clock(USB_IFCLK),
+ .usb_data(USB_PB),
+ .usb_full(~USB_FLAGB),
+ .usb_empty(~USB_FLAGA),
+ .usb_wrreq(usb_wrreq),
+ .usb_rdreq(usb_rdreq),
+ .usb_rden(usb_rden),
+ .usb_pktend(usb_pktend),
+ .usb_addr(usb_addr),
+
+ .clock(sys_clock),
+
+ .tx_full(usb_tx_full),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+
+ .rx_empty(usb_rx_empty),
+ .rx_rdreq(usb_rx_rdreq),
+ .rx_q(usb_rx_data)
+ );
+
+ wire [N*M*12-1:0] int_mux_data;
+
+ wire [11:0] osc_mux_data [M-1:0];
+ wire [11:0] trg_mux_data;
+ wire trg_flag;
+
+ wire ana_good [N-1:0];
+ wire [11:0] ana_data [N-1:0];
+
+ wire sys_clock, sys_frame;
+
+ wire adc_fast_clock, adc_slow_clock;
+
+ wire [N*12-1:0] int_data;
+
+ wire [11:0] sys_data [N-1:0];
+ wire [11:0] nowhere;
+
+ wire [23:0] uwt_d1 [N-1:0];
+ wire [23:0] uwt_a1 [N-1:0];
+ wire [23:0] uwt_peak1 [N-1:0];
+ wire [23:0] uwt_d2 [N-1:0];
+ wire [23:0] uwt_a2 [N-1:0];
+ wire [23:0] uwt_peak2 [N-1:0];
+ wire [23:0] uwt_d3 [N-1:0];
+ wire [23:0] uwt_a3 [N-1:0];
+ wire [23:0] uwt_peak3 [N-1:0];
+
+ wire [1:0] uwt_flag1 [N-1:0];
+ wire [1:0] uwt_flag2 [N-1:0];
+ wire [1:0] uwt_flag3 [N-1:0];
+
+ wire i2c_reset;
+
+
+ sys_pll sys_pll_unit (
+ .inclk0(CLK_50MHz),
+ .c0(sys_clock));
+
+ test test_unit (
+ .clk(ADC_FCO),
+ .data(nowhere));
+
+ adc_pll adc_pll_unit (
+ .inclk0(ADC_FCO),
+ .c0(adc_fast_clock),
+ .c1(adc_slow_clock));
+
+ adc_lvds #(
+ .size(N/2),
+ .width(24)) adc_lvds_unit (
+ .clock(sys_clock),
+ .lvds_dco(adc_fast_clock),
+ .lvds_fco(adc_slow_clock),
+ .lvds_d(ADC_D),
+ .adc_frame(sys_frame),
+ .adc_data(int_data));
+
+ wire [15:0] cfg_bits [31:0];
+ wire [511:0] int_cfg_bits;
+
+ wire [31:0] cfg_mux_selector;
+
+ wire cfg_reset;
+
+ wire [19-1:0] bus_ssel;
+ wire bus_wren;
+ wire [31:0] bus_addr;
+ wire [15:0] bus_mosi;
+ wire [15:0] bus_miso [19-2:0];
+ wire [19-1:0] bus_busy;
+
+ wire [15:0] mrg_bus_miso;
+ wire mrg_bus_busy;
+
+ wire [(19-1)*16-1:0] int_bus_miso;
+
+ genvar j;
+
+ generate
+ for (j = 0; j < 32; j = j + 1)
+ begin : CONFIGURATION_OUTPUT
+ assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
+ end
+ endgenerate
+
+ configuration configuration_unit (
+ .clock(sys_clock),
+ .reset(cfg_reset),
+ .bus_ssel(bus_ssel[0]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[4:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[0]),
+ .bus_busy(bus_busy[0]),
+ .cfg_bits(int_cfg_bits));
+
+ generate
+ for (j = 0; j < N; j = j + 1)
+ begin : MUX_DATA
+ assign int_mux_data[j*4*12+4*12-1:j*4*12] = {
+ {ana_good[j], 11'd0},
+ ana_data[j],
+ uwt_a2[j][17:6],
+ sys_data[j]};
+ end
+ endgenerate
+
+ assign cfg_mux_selector = {cfg_bits[5], cfg_bits[4]};
+
+ lpm_mux #(
+ .lpm_size(N*4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(6)) trg_mux_unit (
+ .sel(cfg_bits[6][5:0]),
+ .data(int_mux_data),
+ .result(trg_mux_data));
+
+ generate
+ for (j = 0; j < M; j = j + 1)
+ begin : OSC_CHAIN
+
+ lpm_mux #(
+ .lpm_size(N*4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(12),
+ .lpm_widths(6)) osc_mux_unit (
+ .sel(cfg_mux_selector[j*8+5:j*8]),
+ .data(int_mux_data),
+ .result(osc_mux_data[j]));
+
+ end
+ endgenerate
+
+ trigger trigger_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][0]),
+ .cfg_data(cfg_bits[7][11:0]),
+ .trg_data(trg_mux_data),
+ .trg_flag(trg_flag));
+
+ oscilloscope oscilloscope_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[0][1]),
+ .cfg_data(cfg_bits[7][12]),
+ .trg_flag(trg_flag),
+ .osc_data({16'd0, osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
+ .ram_wren(RAM_WE),
+ .ram_addr(RAM_ADDR),
+ .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
+ .bus_ssel(bus_ssel[1]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[19:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[1]),
+ .bus_busy(bus_busy[1]));
+
+ generate
+ for (j = 0; j < N; j = j + 1)
+ begin : MCA_CHAIN
+
+ assign sys_data[j] = (cfg_bits[3][j]) ? (int_data[j*12+11:j*12] ^ 12'hfff) : (int_data[j*12+11:j*12]);
+
+ uwt_bior31 #(.L(1)) uwt_1_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .x({20'h00000, sys_data[j]}),
+ .d(uwt_d1[j]),
+ .a(uwt_a1[j]),
+ .peak(uwt_peak1[j]),
+ .flag(uwt_flag1[j]));
+
+ uwt_bior31 #(.L(2)) uwt_2_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .x(uwt_a1[j]),
+ .d(uwt_d2[j]),
+ .a(uwt_a2[j]),
+ .peak(uwt_peak2[j]),
+ .flag(uwt_flag2[j]));
+
+ uwt_bior31 #(.L(3)) uwt_3_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(1'b0),
+ .x(uwt_a2[j]),
+ .d(uwt_d3[j]),
+ .a(uwt_a3[j]),
+ .peak(uwt_peak3[j]),
+ .flag(uwt_flag3[j]));
+
+ analyser analyser_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[1][j]),
+ .cfg_data(cfg_bits[8+j]),
+ .uwt_flag(uwt_flag3[j]),
+ .uwt_data(uwt_peak3[j][11:0]),
+ .ana_good(ana_good[j]),
+ .ana_data(ana_data[j]));
+
+ histogram histogram_unit (
+ .clock(sys_clock),
+ .frame(sys_frame),
+ .reset(cfg_bits[2][j]),
+ .hst_good(ana_good[j]),
+ .hst_data(ana_data[j][11:3]),
+ .bus_ssel(bus_ssel[2+j]),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr[9:0]),
+ .bus_mosi(bus_mosi),
+ .bus_miso(bus_miso[2+j]),
+ .bus_busy(bus_busy[2+j]));
+
+ end
+ endgenerate
+
+ i2c_fifo i2c_unit(
+ .clock(sys_clock),
+ .reset(i2c_reset),
+
+ .i2c_sda(I2C_SDA),
+ .i2c_scl(I2C_SCL),
+
+ .bus_ssel(bus_ssel[18]),
+ .bus_wren(bus_wren),
+ .bus_mosi(bus_mosi),
+ .bus_busy(bus_busy[18]));
+
+ generate
+ for (j = 0; j < 18; j = j + 1)
+ begin : BUS_OUTPUT
+ assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(18),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(5)) bus_miso_mux_unit (
+ .sel(bus_addr[28:24]),
+ .data(int_bus_miso),
+ .result(mrg_bus_miso));
+
+ lpm_mux #(
+ .lpm_size(19),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(1),
+ .lpm_widths(5)) bus_busy_mux_unit (
+ .sel(bus_addr[28:24]),
+ .data(bus_busy),
+ .result(mrg_bus_busy));
+
+ lpm_decode #(
+ .lpm_decodes(19),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(5)) lpm_decode_unit (
+ .data(bus_addr[28:24]),
+ .eq(bus_ssel),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ control control_unit (
+ .clock(sys_clock),
+ .rx_empty(usb_rx_empty),
+ .tx_full(usb_tx_full),
+ .rx_data(usb_rx_data),
+ .rx_rdreq(usb_rx_rdreq),
+ .tx_wrreq(usb_tx_wrreq),
+ .tx_data(usb_tx_data),
+ .bus_wren(bus_wren),
+ .bus_addr(bus_addr),
+ .bus_mosi(bus_mosi),
+ .bus_miso(mrg_bus_miso),
+ .bus_busy(mrg_bus_busy),
+ .led(LED));
+
+/*
+ altserial_flash_loader #(
+ .enable_shared_access("OFF"),
+ .enhanced_mode(1),
+ .intended_device_family("Cyclone III")) sfl_unit (
+ .noe(1'b0),
+ .asmi_access_granted(),
+ .asmi_access_request(),
+ .data0out(),
+ .dclkin(),
+ .scein(),
+ .sdoin());
+*/
+
+endmodule
Index: trunk/Octopus/adc_lvds.v
===================================================================
--- trunk/Octopus/adc_lvds.v (revision 102)
+++ trunk/Octopus/adc_lvds.v (revision 102)
@@ -0,0 +1,102 @@
+module adc_lvds
+ #(
+ parameter size = 8, // number of channels
+ parameter width = 24 // channel resolution
+ )
+ (
+ input wire clock,
+
+ input wire lvds_dco,
+ input wire lvds_fco,
+ input wire [size-1:0] lvds_d,
+
+ output wire adc_frame,
+ output wire [size*width-1:0] adc_data
+
+ );
+
+ reg state, int_rdreq, adc_frame_reg;
+ wire int_wrfull, int_rdempty;
+
+ reg [size-1:0] int_data_h, int_data_l;
+
+ reg [size*width-1:0] int_data_reg;
+ wire [size*width-1:0] int_data_wire;
+
+ wire [size*width-1:0] int_q_wire;
+ reg [size*width-1:0] adc_data_reg;
+
+
+ genvar j;
+
+ generate
+ for (j = 0; j < size; j = j + 1)
+ begin : INT_DATA
+ assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_h[j], int_data_l[j]};
+ end
+ endgenerate
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(size*width),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("ON")) fifo_unit (
+ .data(int_data_wire),
+ .rdclk(clock),
+ .rdreq((~int_rdempty) & int_rdreq),
+ .wrclk(lvds_fco),
+ .wrreq(~int_wrfull),
+ .q(int_q_wire),
+ .rdempty(int_rdempty),
+ .wrfull(int_wrfull),
+ .aclr(),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ always @ (posedge clock)
+ begin
+ case (state)
+ 1'b0:
+ begin
+ int_rdreq <= 1'b1;
+ adc_frame_reg <= 1'b0;
+ state <= 1'b1;
+ end
+
+ 1'b1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_rdreq <= 1'b0;
+ adc_data_reg <= int_q_wire;
+ adc_frame_reg <= 1'b1;
+ state <= 1'b0;
+ end
+ end
+ endcase
+ end
+
+ always @ (negedge lvds_dco)
+ begin
+ int_data_l <= lvds_d;
+ end
+
+ always @ (posedge lvds_dco)
+ begin
+ int_data_h <= lvds_d;
+ int_data_reg <= int_data_wire;
+ end
+
+ assign adc_frame = adc_frame_reg;
+ assign adc_data = adc_data_reg;
+
+endmodule
Index: trunk/Octopus/adc_pll.v
===================================================================
--- trunk/Octopus/adc_pll.v (revision 102)
+++ trunk/Octopus/adc_pll.v (revision 102)
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: adc_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module adc_pll (
+ inclk0,
+ c0,
+ c1);
+
+ input inclk0;
+ output c0;
+ output c1;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire sub_wire3 = inclk0;
+ wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+ altpll altpll_component (
+ .inclk (sub_wire4),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 12,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 50000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=adc_pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "240.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "20.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "12"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "adc_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "50000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
Index: trunk/Octopus/analyser.v
===================================================================
--- trunk/Octopus/analyser.v (revision 102)
+++ trunk/Octopus/analyser.v (revision 102)
@@ -0,0 +1,82 @@
+module analyser
+ (
+ input wire clock, frame, reset,
+ input wire [15:0] cfg_data,
+ input wire [1:0] uwt_flag,
+ input wire [11:0] uwt_data,
+ output wire ana_good,
+ output wire [11:0] ana_data
+ );
+
+ reg state_reg, state_next;
+ reg [3:0] counter_reg, counter_next;
+ reg [11:0] minimum_reg, minimum_next;
+ reg good_reg, good_next;
+ reg [11:0] data_reg, data_next;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ state_reg <= 1'b0;
+ counter_reg <= 4'd0;
+ minimum_reg <= 12'd0;
+ good_reg <= 1'b0;
+ data_reg <= 12'd0;
+ end
+ else
+ begin
+ state_reg <= state_next;
+ counter_reg <= counter_next;
+ minimum_reg <= minimum_next;
+ good_reg <= good_next;
+ data_reg <= data_next;
+ end
+ end
+
+ always @*
+ begin
+ state_next = state_reg;
+ counter_next = counter_reg;
+ minimum_next = minimum_reg;
+ good_next = good_reg;
+ data_next = data_reg;
+
+ case (state_reg)
+ 0:
+ begin
+ if (frame)
+ begin
+ // minimum
+ if (uwt_flag[0])
+ begin
+ counter_next = cfg_data[3:0];
+ minimum_next = uwt_data;
+ end
+ // counter is not zero
+ else if (|counter_reg)
+ begin
+ counter_next = counter_reg - 4'd1;
+ end
+ // maximum
+ else if ((uwt_flag[1]) & (uwt_data > minimum_reg))
+ begin
+ data_next = uwt_data - minimum_reg;
+ state_next = 1'b1;
+ end
+ end
+ end
+
+ 1:
+ begin
+ good_next = (data_reg >= cfg_data[15:4]);
+ state_next = 1'b0;
+ end
+
+ endcase
+ end
+
+ assign ana_good = good_reg;
+ assign ana_data = data_reg;
+
+endmodule
Index: trunk/Octopus/configuration.v
===================================================================
--- trunk/Octopus/configuration.v (revision 102)
+++ trunk/Octopus/configuration.v (revision 102)
@@ -0,0 +1,82 @@
+module configuration
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [4:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire [511:0] cfg_bits
+ );
+
+ wire [31:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+ reg [15:0] int_miso_reg;
+
+ wire [511:0] int_bits_wire;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 32; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(int_bits_wire[j*16+15:j*16]),
+ .aclr(),
+ .aload(),
+ .aset(),
+ .sload(),
+ .sset());
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(32),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(5)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(int_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(32),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(5)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cfg_bits = int_bits_wire;
+
+endmodule
Index: trunk/Octopus/control.v
===================================================================
--- trunk/Octopus/control.v (revision 102)
+++ trunk/Octopus/control.v (revision 102)
@@ -0,0 +1,260 @@
+module control
+ (
+ input wire clock, reset,
+
+ input wire rx_empty, tx_full,
+ input wire [7:0] rx_data,
+
+ output wire rx_rdreq, tx_wrreq,
+ output wire [7:0] tx_data,
+
+ output wire bus_wren,
+ output wire [31:0] bus_addr,
+ output wire [15:0] bus_mosi,
+
+ input wire [15:0] bus_miso,
+ input wire bus_busy,
+
+ output wire led
+ );
+
+ reg [23:0] led_counter;
+
+ reg int_bus_wren;
+ reg [31:0] int_bus_addr;
+ reg [31:0] int_bus_cntr;
+ reg [15:0] int_bus_mosi;
+
+ reg int_rdreq, int_wrreq;
+ reg [7:0] int_data;
+ reg int_led;
+
+ reg [1:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ reg [4:0] state;
+
+ reg [31:0] address, counter;
+
+ reg [15:0] prefix;
+
+ wire [15:0] dest, data;
+
+ reg [7:0] buffer [3:0];
+
+ assign dest = {buffer[0], buffer[1]};
+ assign data = {buffer[2], buffer[3]};
+
+ always @(posedge clock)
+ begin
+ if (~rx_empty)
+ begin
+ int_led <= 1'b0;
+ led_counter <= 24'd0;
+ end
+ else
+ begin
+ if (&led_counter)
+ begin
+ int_led <= 1'b1;
+ end
+ else
+ begin
+ led_counter <= led_counter + 24'd1;
+ end
+ end
+
+ case(state)
+ 0:
+ begin
+ int_rdreq <= 1'b1;
+ int_wrreq <= 1'b0;
+ idle_counter <= 5'd0;
+ byte_counter <= 2'd0;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ // read 4 bytes
+ if (~rx_empty)
+ begin
+ idle_counter <= 5'd0;
+ byte_counter <= byte_counter + 2'd1;
+ buffer[byte_counter] <= rx_data;
+ if (&byte_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+ else if(|byte_counter)
+ begin
+ idle_counter <= idle_counter + 5'd1;
+ if (&idle_counter)
+ begin
+ int_rdreq <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+ end
+
+ 2:
+ begin
+ case (dest)
+ 16'h0000:
+ begin
+ // reset
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+
+ 16'h0001:
+ begin
+ // prefix register
+ prefix <= data;
+ state <= 5'd0;
+ end
+
+
+ 16'h0002:
+ begin
+ // address register
+ address <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0003:
+ begin
+ // counter register
+ counter <= {prefix, data};
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+
+ 16'h0004:
+ begin
+ // single write
+ int_bus_addr <= address;
+ int_bus_mosi <= data;
+ int_bus_wren <= 1'b1;
+ prefix <= 16'd0;
+ state <= 5'd3;
+ end
+
+ 16'h0005:
+ begin
+ // multi read
+ int_bus_addr <= address;
+ int_bus_cntr <= counter;
+ int_bus_wren <= 1'b0;
+ prefix <= 16'd0;
+ state <= 5'd4;
+ end
+
+ default:
+ begin
+ prefix <= 16'd0;
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ // single write
+ 3:
+ begin
+ if (~bus_busy)
+ begin
+ int_bus_addr <= 32'd0;
+ int_bus_mosi <= 16'd0;
+ int_bus_wren <= 1'b0;
+ state <= 5'd0;
+ end
+ end
+
+ // multi read
+ 4:
+ begin
+ if (bus_busy)
+ begin
+ buffer[0] <= 8'd1;
+ buffer[1] <= 8'd0;
+ int_bus_cntr <= 32'd0;
+ end
+ else
+ begin
+ buffer[0] <= 8'd0;
+ buffer[1] <= 8'd0;
+ end
+ state <= 5'd7;
+ end
+
+ 5:
+ begin
+ buffer[0] <= bus_miso[7:0];
+ buffer[1] <= bus_miso[15:8];
+ int_bus_addr <= int_bus_addr + 32'd1;
+ int_bus_cntr <= int_bus_cntr - 32'd1;
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_data <= buffer[0];
+ int_wrreq <= 1'b1;
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ if (~tx_full)
+ begin
+ int_data <= buffer[1];
+ state <= 5'd9;
+ end
+ end
+
+ 9:
+ begin
+ if (~tx_full)
+ begin
+ int_wrreq <= 1'b0;
+ state <= 5'd10;
+ end
+ end
+
+ 10:
+ begin
+ if (|int_bus_cntr)
+ begin
+ state <= 5'd5;
+ end
+ else
+ begin
+ state <= 5'd0;
+ end
+ end
+
+ default:
+ begin
+ state <= 5'd0;
+ end
+ endcase
+ end
+
+ assign bus_wren = int_bus_wren;
+ assign bus_addr = int_bus_addr;
+ assign bus_mosi = int_bus_mosi;
+ assign rx_rdreq = int_rdreq & (~rx_empty);
+ assign tx_wrreq = int_wrreq & (~tx_full);
+ assign tx_data = int_data;
+ assign led = int_led;
+
+endmodule
Index: trunk/Octopus/counter.v
===================================================================
--- trunk/Octopus/counter.v (revision 102)
+++ trunk/Octopus/counter.v (revision 102)
@@ -0,0 +1,111 @@
+module counter
+ (
+ input wire clock, frame, reset,
+
+ input wire [15:0] cfg_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [1:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy,
+
+ output wire cnt_good
+ );
+
+ wire [3:0] int_ssel_wire;
+ wire [15:0] int_miso_wire;
+
+ reg cnt_good_reg;
+ reg [15:0] int_miso_reg;
+
+ wire [63:0] reg_bits_wire;
+ wire [63:0] cnt_bits_wire;
+
+ integer i;
+ genvar j;
+
+ lpm_counter #(
+ .lpm_direction("DOWN"),
+ .lpm_port_updown("PORT_UNUSED"),
+ .lpm_type("LPM_COUNTER"),
+ .lpm_width(64)) lpm_counter_component (
+ .sload(cfg_data[0]),
+ .sclr(reset),
+ .clock(clock),
+ .data(reg_bits_wire),
+// .cnt_en(frame & cfg_data[1]),
+ .cnt_en((frame) & (|cnt_bits_wire) & (cfg_data[1])),
+ .q(cnt_bits_wire),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .cout(),
+ .eq(),
+ .sset(1'b0),
+ .updown(1'b1));
+
+ generate
+ for (j = 0; j < 4; j = j + 1)
+ begin : BUS_OUTPUT
+ lpm_ff #(
+ .lpm_fftype("DFF"),
+ .lpm_type("LPM_FF"),
+ .lpm_width(16)) cfg_reg_unit (
+ .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
+ .sclr(reset),
+ .clock(clock),
+ .data(bus_mosi),
+ .q(reg_bits_wire[j*16+15:j*16]),
+ .aclr(),
+ .aload(),
+ .aset(),
+ .sload(),
+ .sset());
+ end
+ endgenerate
+
+ lpm_mux #(
+ .lpm_size(4),
+ .lpm_type("LPM_MUX"),
+ .lpm_width(16),
+ .lpm_widths(2)) bus_miso_mux_unit (
+ .sel(bus_addr),
+ .data(cnt_bits_wire),
+ .result(int_miso_wire));
+
+
+ lpm_decode #(
+ .lpm_decodes(4),
+ .lpm_type("LPM_DECODE"),
+ .lpm_width(2)) lpm_decode_unit (
+ .data(bus_addr),
+ .eq(int_ssel_wire),
+ .aclr(),
+ .clken(),
+ .clock(),
+ .enable());
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_miso_reg <= 16'd0;
+ cnt_good_reg <= 1'b0;
+ end
+ else
+ begin
+ int_miso_reg <= int_miso_wire;
+ cnt_good_reg <= (|cnt_bits_wire) & (cfg_data[1]);
+ end
+ end
+
+ // output logic
+ assign bus_miso = int_miso_reg;
+ assign bus_busy = 1'b0;
+ assign cnt_good = cnt_good_reg;
+
+endmodule
Index: trunk/Octopus/histogram.v
===================================================================
--- trunk/Octopus/histogram.v (revision 102)
+++ trunk/Octopus/histogram.v (revision 102)
@@ -0,0 +1,199 @@
+module histogram
+ (
+ input wire clock, frame, reset,
+
+ input wire hst_good,
+ input wire [8:0] hst_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [9:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+ // signal declaration
+ reg [3:0] int_case_reg, int_case_next;
+ reg int_wren_reg, int_wren_next;
+ reg [8:0] int_addr_reg, int_addr_next;
+ reg [31:0] int_data_reg, int_data_next;
+
+ reg [9:0] bus_addr_reg, bus_addr_next;
+ reg [15:0] bus_miso_reg, bus_miso_next;
+
+ reg bus_wren_reg, bus_wren_next;
+ reg [15:0] bus_mosi_reg, bus_mosi_next;
+
+ wire [31:0] q_a_wire;
+ wire [15:0] q_b_wire;
+
+ altsyncram #(
+ .address_reg_b("CLOCK0"),
+ .clock_enable_input_a("BYPASS"),
+ .clock_enable_input_b("BYPASS"),
+ .clock_enable_output_a("BYPASS"),
+ .clock_enable_output_b("BYPASS"),
+ .indata_reg_b("CLOCK0"),
+ .intended_device_family("Cyclone III"),
+ .lpm_type("altsyncram"),
+ .numwords_a(512),
+ .numwords_b(1024),
+ .operation_mode("BIDIR_DUAL_PORT"),
+ .outdata_aclr_a("NONE"),
+ .outdata_aclr_b("NONE"),
+ .outdata_reg_a("CLOCK0"),
+ .outdata_reg_b("CLOCK0"),
+ .power_up_uninitialized("FALSE"),
+ .read_during_write_mode_mixed_ports("OLD_DATA"),
+ .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
+ .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
+ .widthad_a(9),
+ .widthad_b(10),
+ .width_a(32),
+ .width_b(16),
+ .width_byteena_a(1),
+ .width_byteena_b(1),
+ .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
+ .wren_a(int_wren_reg),
+ .clock0(clock),
+ .wren_b(bus_wren_reg),
+ .address_a(int_addr_reg),
+ .address_b(bus_addr_reg),
+ .data_a(int_data_reg),
+ .data_b(bus_mosi_reg),
+ .q_a(q_a_wire),
+ .q_b(q_b_wire),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a(1'b1),
+ .byteena_b(1'b1),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .eccstatus(),
+ .rden_a(1'b1),
+ .rden_b(1'b1));
+
+ // body
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ int_wren_reg <= 1'b1;
+ int_addr_reg <= 9'd0;
+ int_data_reg <= 32'd0;
+ int_case_reg <= 4'b0;
+ bus_addr_reg <= 10'd0;
+ bus_miso_reg <= 16'd0;
+ bus_wren_reg <= 1'b0;
+ bus_mosi_reg <= 16'd0;
+ end
+ else
+ begin
+ int_wren_reg <= int_wren_next;
+ int_addr_reg <= int_addr_next;
+ int_data_reg <= int_data_next;
+ int_case_reg <= int_case_next;
+ bus_addr_reg <= bus_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_wren_reg <= bus_wren_next;
+ bus_mosi_reg <= bus_mosi_next;
+ end
+ end
+
+ always @*
+ begin
+ bus_addr_next = bus_addr_reg;
+ bus_miso_next = bus_miso_reg;
+
+ bus_wren_next = 1'b0;
+ bus_mosi_next = bus_mosi_reg;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = q_b_wire;
+ bus_addr_next = bus_addr;
+ bus_wren_next = bus_wren;
+ if (bus_wren)
+ begin
+ bus_mosi_next = bus_mosi;
+ end
+ end
+ end
+
+ always @*
+ begin
+ int_wren_next = int_wren_reg;
+ int_addr_next = int_addr_reg;
+ int_data_next = int_data_reg;
+ int_case_next = int_case_reg;
+
+ case (int_case_reg)
+
+ 0:
+ begin
+ // write zeros
+ int_addr_next = int_addr_reg + 9'd1;
+ if (&int_addr_reg)
+ begin
+ int_wren_next = 1'b0;
+ int_case_next = 4'd1;
+ end
+ end
+
+ 1:
+ begin
+ int_wren_next = 1'b0;
+/*
+ if (&int_data_reg)
+ begin
+ int_case_next = 4'd0;
+ end
+ else if (frame & hst_good)
+*/
+ if (frame & hst_good)
+ begin
+ int_addr_next = hst_data;
+ int_case_next = 4'd2;
+ end
+ end
+
+ 2:
+ begin
+ int_case_next = 4'd3;
+ end
+
+ 3:
+ begin
+ int_case_next = 4'd4;
+ end
+
+ 4:
+ begin
+ int_case_next = 4'd1;
+ if (~&q_a_wire)
+ begin
+ int_wren_next = 1'b1;
+ int_data_next = q_a_wire + 32'd1;
+ end
+ end
+
+ default:
+ begin
+ int_wren_next = 1'b0;
+ int_addr_next = 9'd0;
+ int_data_next = 32'd0;
+ int_case_next = 4'd0;
+ end
+ endcase
+ end
+
+ // output logic
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = 1'b0;
+endmodule
Index: trunk/Octopus/i2c_fifo.v
===================================================================
--- trunk/Octopus/i2c_fifo.v (revision 102)
+++ trunk/Octopus/i2c_fifo.v (revision 102)
@@ -0,0 +1,219 @@
+module i2c_fifo
+ (
+ input wire clock, reset,
+
+ input wire bus_ssel, bus_wren,
+ input wire [15:0] bus_mosi,
+
+ output wire bus_busy,
+
+ inout wire i2c_sda,
+ inout wire i2c_scl
+ );
+
+ wire int_rdempty, int_wrfull, i2c_clk, start, stop;
+ wire [15:0] int_q;
+
+ reg int_bus_busy;
+ reg int_rdreq, int_wrreq, int_clken, int_sdo, int_scl, int_ack;
+ reg [15:0] int_bus_mosi;
+ reg [15:0] int_data;
+ reg [9:0] counter;
+ reg [4:0] state;
+
+ assign i2c_sda = int_sdo ? 1'bz : 1'b0;
+ assign i2c_scl = int_scl | (int_clken ? counter[9] : 1'b0);
+
+ assign start = int_data[8];
+ assign stop = int_data[9];
+
+ scfifo #(
+ .add_ram_output_register("OFF"),
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("scfifo"),
+ .lpm_width(16),
+ .lpm_widthu(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF")) fifo_tx (
+ .rdreq((~int_rdempty) & (int_rdreq) & (&counter)),
+ .aclr(1'b0),
+ .clock(clock),
+ .wrreq(int_wrreq),
+ .data(int_bus_mosi),
+ .empty(int_rdempty),
+ .q(int_q),
+ .full(int_wrfull),
+ .almost_empty(),
+ .almost_full(),
+ .sclr(),
+ .usedw());
+
+ always @ (posedge clock)
+ begin
+ int_bus_busy <= int_wrfull;
+
+ if (bus_ssel)
+ begin
+ if (~int_wrfull & bus_wren)
+ begin
+ int_bus_mosi <= bus_mosi;
+ int_wrreq <= 1'b1;
+ end
+ end
+
+ if (~int_wrfull & int_wrreq)
+ begin
+ int_wrreq <= 1'b0;
+ end
+
+ end
+
+ always @ (posedge clock)
+ begin
+ counter <= counter + 10'd1;
+ if (&counter)
+ begin
+ case (state)
+ 0:
+ begin
+ int_ack <= 1'b0;
+ int_sdo <= 1'b1;
+ int_scl <= 1'b1;
+ int_rdreq <= 1'b1;
+ state <= 5'd1;
+ end
+
+ 1:
+ begin
+ if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_rdreq <= 1'b0;
+ state <= 5'd2;
+ end
+ end
+
+ 2:
+ begin
+ if (start)
+ begin
+ int_sdo <= 1'b1;
+ int_scl <= 1'b1;
+ state <= 5'd3;
+ end
+ else
+ begin
+ state <= 5'd5;
+ end
+ end
+
+ 3:
+ begin // start
+ int_sdo <= 1'b0;
+ state <= 5'd4;
+ end
+
+ 4:
+ begin
+ int_scl <= 1'b0;
+ state <= 5'd5;
+ end
+
+ 5:
+ begin // data
+ int_clken <= 1'b1;
+ int_sdo <= int_data[7];
+ state <= 5'd6;
+ end
+
+ 6:
+ begin
+ int_sdo <= int_data[6];
+ state <= 5'd7;
+ end
+
+ 7:
+ begin
+ int_sdo <= int_data[5];
+ state <= 5'd8;
+ end
+
+ 8:
+ begin
+ int_sdo <= int_data[4];
+ state <= 5'd9;
+ end
+
+ 9:
+ begin
+ int_sdo <= int_data[3];
+ state <= 5'd10;
+ end
+
+ 10:
+ begin
+ int_sdo <= int_data[2];
+ state <= 5'd11;
+ end
+
+ 11:
+ begin
+ int_sdo <= int_data[1];
+ state <= 5'd12;
+ end
+
+ 12:
+ begin
+ int_sdo <= int_data[0];
+ state <= 5'd13;
+ end
+
+ 13:
+ begin // ack
+ int_sdo <= 1'b1;
+ int_rdreq <= 1'b1;
+ state <= 5'd14;
+ end
+
+ 14:
+ begin
+ int_ack <= i2c_sda;
+ int_rdreq <= 1'b0;
+ if (stop | int_rdempty)
+ begin
+ int_clken <= 1'b0;
+ int_sdo <= 1'b0;
+ int_scl <= 1'b0;
+ state <= 5'd15;
+ end
+ else if (~int_rdempty)
+ begin
+ int_data <= int_q;
+ int_sdo <= int_q[7];
+ state <= 5'd6;
+ end
+ end
+
+ 15:
+ begin // stop
+ int_scl <= 1'b1;
+ state <= 5'd16;
+ end
+
+ 16:
+ begin
+ int_sdo <= 1'b1;
+ state <= 5'd0;
+ end
+
+ endcase
+ end
+ end
+
+ // output logic
+ assign bus_busy = int_bus_busy;
+
+endmodule
Index: trunk/Octopus/oscilloscope.v
===================================================================
--- trunk/Octopus/oscilloscope.v (revision 102)
+++ trunk/Octopus/oscilloscope.v (revision 102)
@@ -0,0 +1,246 @@
+module oscilloscope
+ (
+ input wire clock, frame, reset,
+
+ input wire cfg_data,
+
+ input wire trg_flag,
+
+ input wire [63:0] osc_data,
+
+ output wire ram_wren,
+ output wire [19:0] ram_addr,
+ inout wire [17:0] ram_data,
+
+ input wire bus_ssel, bus_wren,
+ input wire [19:0] bus_addr,
+ input wire [15:0] bus_mosi,
+
+ output wire [15:0] bus_miso,
+ output wire bus_busy
+ );
+
+
+ reg [63:0] osc_data_reg, osc_data_next;
+
+ reg [2:0] int_case_reg, int_case_next;
+
+ reg int_trig_reg, int_trig_next;
+ reg [19:0] int_trig_addr_reg, int_trig_addr_next;
+
+ reg [19:0] int_cntr_reg [1:0];
+ reg [19:0] int_cntr_next [1:0];
+
+ reg [15:0] bus_miso_reg, bus_miso_next;
+ reg bus_busy_reg, bus_busy_next;
+
+ reg ram_wren_reg [2:0];
+ reg ram_wren_next [2:0];
+
+ reg [17:0] ram_data_reg [2:0];
+ reg [17:0] ram_data_next [2:0];
+
+ reg [19:0] ram_addr_reg, ram_addr_next;
+
+ wire [17:0] ram_wren_wire;
+
+ assign ram_wren = ~ram_wren_reg[0];
+ assign ram_addr = ram_addr_reg;
+
+ integer i;
+ genvar j;
+
+ generate
+ for (j = 0; j < 18; j = j + 1)
+ begin : SRAM_WREN
+ assign ram_wren_wire[j] = ram_wren_reg[2];
+ assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz;
+ end
+ endgenerate
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ osc_data_reg <= 64'd0;
+ ram_addr_reg <= 20'd0;
+ bus_miso_reg <= 16'd0;
+ bus_busy_reg <= 1'b0;
+ int_case_reg <= 5'd0;
+ int_cntr_reg[0] <= 20'd0;
+ int_cntr_reg[1] <= 20'd0;
+ int_trig_reg <= 1'b0;
+ int_trig_addr_reg <= 20'd0;
+
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ ram_wren_reg[i] <= 1'b0;
+ ram_data_reg[i] <= 16'd0;
+ end
+ end
+ else
+ begin
+ osc_data_reg <= osc_data_next;
+ ram_addr_reg <= ram_addr_next;
+ bus_miso_reg <= bus_miso_next;
+ bus_busy_reg <= bus_busy_next;
+ int_case_reg <= int_case_next;
+ int_cntr_reg[0] <= int_cntr_next[0];
+ int_cntr_reg[1] <= int_cntr_next[1];
+ int_trig_reg <= int_trig_next;
+ int_trig_addr_reg <= int_trig_addr_next;
+
+ for(i = 0; i <= 2; i = i + 1)
+ begin
+ ram_wren_reg[i] <= ram_wren_next[i];
+ ram_data_reg[i] <= ram_data_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+
+ osc_data_next = osc_data_reg;
+ ram_addr_next = ram_addr_reg;
+ bus_miso_next = bus_miso_reg;
+ bus_busy_next = bus_busy_reg;
+ int_case_next = int_case_reg;
+ int_cntr_next[0] = int_cntr_reg[0];
+ int_cntr_next[1] = int_cntr_reg[1];
+ int_trig_next = int_trig_reg;
+ int_trig_addr_next = int_trig_addr_reg;
+
+ for(i = 0; i < 2; i = i + 1)
+ begin
+ ram_wren_next[i+1] = ram_wren_reg[i];
+ ram_data_next[i+1] = ram_data_reg[i];
+ end
+ ram_wren_next[0] = 1'b0;
+ ram_data_next[0] = 18'd0;
+
+ case (int_case_reg)
+ 0:
+ begin
+ bus_busy_next = 1'b0;
+ int_cntr_next[0] = 20'd0;
+ int_cntr_next[1] = 20'd0;
+ int_trig_next = 1'b0;
+
+ if (bus_ssel)
+ begin
+ bus_miso_next = {ram_data[17:10], ram_data[8:1]};
+ ram_wren_next[0] = bus_wren;
+ if (bus_wren)
+ begin
+ ram_addr_next = bus_addr;
+ ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0};
+ end
+ else
+ begin
+ ram_addr_next = int_trig_addr_reg + bus_addr;
+// ram_addr_next = bus_addr;
+ end
+ end
+ else if (cfg_data)
+ begin
+ // start recording
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = 18'd0;
+ ram_addr_next = 20'd0;
+ bus_busy_next = 1'b1;
+ int_case_next = 3'd1;
+ int_trig_addr_next = 20'd0;
+// int_cntr_next[0] = {cfg_data[7:0], 10'd0};
+ int_cntr_next[0] = 20'd262143;
+// int_cntr_next[1] = {cfg_data[15:8], 10'd0};
+ int_cntr_next[1] = 20'd5000;
+ end
+
+ end
+
+ // write zeros
+ 1:
+ begin
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = 18'd2;
+ if(&ram_addr_reg)
+ begin
+ int_case_next = 3'd2;
+ end
+ else
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ end
+ end
+
+ // sample recording
+ 2:
+ begin
+ if (frame)
+ begin
+ osc_data_next = osc_data;
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data[15:8], 1'b0, osc_data[7:0], 1'b0};
+
+ int_case_next = 3'd3;
+
+ if (|int_cntr_reg[1])
+ begin
+ int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+ int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
+ end
+ else if (int_trig_reg)
+ begin
+ if (|int_cntr_reg[0])
+ begin
+ int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+ end
+ end
+ else if (trg_flag)
+ begin
+ int_trig_next = 1'b1;
+ int_trig_addr_next = ram_addr_reg - 20'd19999;
+ end
+ end
+ end
+
+ 3:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
+ int_case_next = 3'd4;
+ end
+
+ 4:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
+ int_case_next = 3'd5;
+ end
+
+ 5:
+ begin
+ ram_addr_next = ram_addr_reg + 20'd1;
+ ram_wren_next[0] = 1'b1;
+ ram_data_next[0] = {osc_data_reg[63:56], 1'b0, osc_data_reg[55:48], 1'b0};
+ if (|int_cntr_reg[0])
+ begin
+ int_case_next = 3'd2;
+ end
+ else
+ begin
+ int_case_next = 3'd0;
+ end
+ end
+
+ endcase
+ end
+
+ assign bus_miso = bus_miso_reg;
+ assign bus_busy = bus_busy_reg;
+
+endmodule
Index: trunk/Octopus/sys_pll.v
===================================================================
--- trunk/Octopus/sys_pll.v (revision 102)
+++ trunk/Octopus/sys_pll.v (revision 102)
@@ -0,0 +1,145 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: sys_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sys_pll (
+ inclk0,
+ c0);
+
+ input inclk0;
+ output c0;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 10,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 17,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+endmodule
Index: trunk/Octopus/test.v
===================================================================
--- trunk/Octopus/test.v (revision 102)
+++ trunk/Octopus/test.v (revision 102)
@@ -0,0 +1,418 @@
+module test
+ (
+ input wire clk,
+ output wire [11:0] data
+ );
+
+ reg [11:0] int_data;
+ reg [15:0] counter;
+// reg [5:0] counter;
+ reg [5:0] state;
+
+ always @(posedge clk)
+ begin
+ case (state)
+/*
+ 0:
+ begin
+ int_data <= 12'd0;
+ state <= 6'd1;
+ end
+
+ 1:
+ begin
+ int_data <= 12'd1024;
+ state <= 6'd2;
+ end
+
+ 2:
+ begin
+ int_data <= 12'd2048;
+ state <= 6'd3;
+ end
+
+ 3:
+ begin
+ int_data <= 12'd3072;
+ state <= 6'd4;
+ end
+
+ 4:
+ begin
+ int_data <= 12'd4095;
+ state <= 6'd5;
+ end
+
+ 5:
+ begin
+ int_data <= 12'd3072;
+ state <= 6'd6;
+ end
+
+ 6:
+ begin
+ int_data <= 12'd2048;
+ state <= 6'd7;
+ end
+
+ 7:
+ begin
+ int_data <= 12'd1024;
+ state <= 6'd8;
+ end
+
+ 8:
+ begin
+ int_data <= 12'd0;
+ counter <= counter + 6'd1;
+ if (&counter)
+ begin
+ state <= 6'd0;
+ end
+ end
+*/
+
+ 6'd0:
+ begin
+ int_data <= 12'h030;
+ state <= 6'd1;
+ end
+
+ 6'd1:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd2;
+ end
+
+ 6'd2:
+ begin
+ int_data <= 12'h081;
+ state <= 6'd3;
+ end
+
+ 6'd3:
+ begin
+ int_data <= 12'h0f5;
+ state <= 6'd4;
+ end
+
+ 6'd4:
+ begin
+ int_data <= 12'h10a;
+ state <= 6'd5;
+ end
+
+ 6'd5:
+ begin
+ int_data <= 12'h11a;
+ state <= 6'd6;
+ end
+
+ 6'd6:
+ begin
+ int_data <= 12'h124;
+ state <= 6'd7;
+ end
+
+ 6'd7:
+ begin
+ int_data <= 12'h124;
+ state <= 6'd8;
+ end
+
+ 6'd8:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd9;
+ end
+
+ 6'd9:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd10;
+ end
+
+ 6'd10:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd11;
+ end
+
+ 6'd11:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd12;
+ end
+
+ 6'd12:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd13;
+ end
+
+ 6'd13:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd14;
+ end
+
+ 6'd14:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd15;
+ end
+
+ 6'd15:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd16;
+ end
+
+ 6'd16:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd17;
+ end
+
+ 6'd17:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd18;
+ end
+
+ 6'd18:
+ begin
+ int_data <= 12'h12a;
+ state <= 6'd19;
+ end
+
+ 6'd19:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd20;
+ end
+
+ 6'd20:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd21;
+ end
+
+ 6'd21:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd22;
+ end
+
+ 6'd22:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd23;
+ end
+
+ 6'd23:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd24;
+ end
+
+ 6'd24:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd25;
+ end
+
+ 6'd25:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd26;
+ end
+
+ 6'd26:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd27;
+ end
+
+ 6'd27:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd28;
+ end
+
+ 6'd28:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd29;
+ end
+
+ 6'd29:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd30;
+ end
+
+ 6'd30:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd31;
+ end
+
+ 6'd31:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd32;
+ end
+
+ 6'd32:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd33;
+ end
+
+ 6'd33:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd34;
+ end
+
+ 6'd34:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd35;
+ end
+
+ 6'd35:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd36;
+ end
+
+ 6'd36:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd37;
+ end
+
+ 6'd37:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd38;
+ end
+
+ 6'd38:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd39;
+ end
+
+ 6'd39:
+ begin
+ int_data <= 12'h12b;
+ state <= 6'd40;
+ end
+
+ 6'd40:
+ begin
+ int_data <= 12'h12e;
+ state <= 6'd41;
+ end
+
+ 6'd41:
+ begin
+ int_data <= 12'h12f;
+ state <= 6'd42;
+ end
+
+ 6'd42:
+ begin
+ int_data <= 12'h0fb;
+ state <= 6'd43;
+ end
+
+ 6'd43:
+ begin
+ int_data <= 12'h07e;
+ state <= 6'd44;
+ end
+
+ 6'd44:
+ begin
+ int_data <= 12'h070;
+ state <= 6'd45;
+ end
+
+ 6'd45:
+ begin
+ int_data <= 12'h05a;
+ state <= 6'd46;
+ end
+
+ 6'd46:
+ begin
+ int_data <= 12'h045;
+ state <= 6'd47;
+ end
+
+ 6'd47:
+ begin
+ int_data <= 12'h03f;
+ state <= 6'd48;
+ end
+
+ 6'd48:
+ begin
+ int_data <= 12'h03b;
+ state <= 6'd49;
+ end
+
+ 6'd49:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd50;
+ end
+
+ 6'd50:
+ begin
+ int_data <= 12'h035;
+ state <= 6'd51;
+ end
+
+ 6'd51:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd52;
+ end
+
+ 6'd52:
+ begin
+ int_data <= 12'h034;
+ state <= 6'd53;
+ end
+
+ 6'd53:
+ begin
+ int_data <= 12'h030;
+ state <= 6'd54;
+ end
+
+ 6'd54:
+ begin
+ int_data <= 12'h030;
+ counter <= counter + 16'd1;
+ if (&counter)
+ begin
+ state <= 6'd0;
+ end
+ end
+
+ default:
+ begin
+ state <= 6'd0;
+ end
+ endcase
+ end
+
+ assign data = int_data;
+
+endmodule
Index: trunk/Octopus/trigger.v
===================================================================
--- trunk/Octopus/trigger.v (revision 102)
+++ trunk/Octopus/trigger.v (revision 102)
@@ -0,0 +1,32 @@
+module trigger
+ (
+ input wire clock, frame, reset,
+ input wire [11:0] cfg_data,
+ input wire [11:0] trg_data,
+ output wire trg_flag
+ );
+
+ reg trg_flag_reg;
+ reg [11:0] cfg_data_reg;
+ reg [11:0] trg_data_reg;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ trg_flag_reg <= 1'b0;
+ end
+ else
+ begin
+ if (frame)
+ begin
+ cfg_data_reg <= cfg_data;
+ trg_data_reg <= trg_data;
+ end
+ trg_flag_reg <= (trg_data_reg >= cfg_data_reg);
+ end
+ end
+
+ assign trg_flag = trg_flag_reg;
+
+endmodule
Index: trunk/Octopus/usb_fifo.v
===================================================================
--- trunk/Octopus/usb_fifo.v (revision 102)
+++ trunk/Octopus/usb_fifo.v (revision 102)
@@ -0,0 +1,119 @@
+module usb_fifo
+ (
+ input wire usb_clock,
+ inout wire [7:0] usb_data,
+ input wire usb_full, usb_empty,
+ output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
+ output wire [1:0] usb_addr,
+
+ input wire clock,
+ input wire tx_wrreq, rx_rdreq,
+ input wire [7:0] tx_data,
+ output wire tx_full, rx_empty,
+ output wire [7:0] rx_q
+ );
+
+ wire int_rx_full, int_tx_empty;
+ wire rx_ready, tx_ready;
+ wire int_rdreq, int_wrreq, int_pktend;
+ reg is_rx_addr_ok;
+ reg [8:0] byte_counter;
+ reg [4:0] idle_counter;
+
+ wire [7:0] int_rx_data = usb_data;
+ wire [7:0] int_tx_q;
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF")) fifo_tx (
+ .data(tx_data),
+ .rdclk(usb_clock),
+ .rdreq(int_wrreq),
+ .wrclk(clock),
+ .wrreq(tx_wrreq),
+ .q(int_tx_q),
+ .rdempty(int_tx_empty),
+ .wrfull(tx_full),
+ .aclr(),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ dcfifo #(
+ .intended_device_family("Cyclone III"),
+ .lpm_numwords(16),
+ .lpm_showahead("ON"),
+ .lpm_type("dcfifo"),
+ .lpm_width(8),
+ .lpm_widthu(4),
+ .rdsync_delaypipe(4),
+ .wrsync_delaypipe(4),
+ .overflow_checking("ON"),
+ .underflow_checking("ON"),
+ .use_eab("OFF")) fifo_rx (
+ .data(int_rx_data),
+ .rdclk(clock),
+ .rdreq(rx_rdreq),
+ .wrclk(usb_clock),
+ .wrreq(int_rdreq),
+ .q(rx_q),
+ .rdempty(rx_empty),
+ .wrfull(int_rx_full),
+ .aclr(),
+ .rdfull(),
+ .rdusedw(),
+ .wrempty(),
+ .wrusedw());
+
+ assign rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);
+ assign tx_ready = (~rx_ready) & (~usb_full) & (~int_tx_empty) & (~int_pktend);
+
+ assign int_rdreq = (rx_ready) & (is_rx_addr_ok);
+ assign int_wrreq = (tx_ready) & (~is_rx_addr_ok);
+
+ assign int_pktend = (&idle_counter);
+
+ always @ (posedge usb_clock)
+ begin
+ // respect 1 clock delay between fifo selection
+ // and data transfer operations
+ is_rx_addr_ok <= rx_ready;
+
+ // assert pktend if buffer contains unsent data
+ // and fifo_tx_unit stays empty for more than 30 clocks
+ if (int_pktend)
+ begin
+ byte_counter <= 9'd0;
+ idle_counter <= 5'd0;
+ end
+ else if (int_wrreq)
+ begin
+ byte_counter <= byte_counter + 9'd1;
+ idle_counter <= 5'd0;
+ end
+ else if ((|byte_counter) & (int_tx_empty) & (~rx_ready))
+ begin
+ byte_counter <= byte_counter;
+ idle_counter <= idle_counter + 5'd1;
+ end
+
+ end
+
+ assign usb_pktend = int_pktend;
+ assign usb_rdreq = int_rdreq;
+ assign usb_wrreq = int_wrreq;
+ assign usb_rden = int_rdreq;
+ assign usb_addr = {1'b1, ~rx_ready};
+ assign usb_data = int_wrreq ? int_tx_q : 8'bz;
+
+endmodule
Index: trunk/Octopus/uwt_bior31.v
===================================================================
--- trunk/Octopus/uwt_bior31.v (revision 102)
+++ trunk/Octopus/uwt_bior31.v (revision 102)
@@ -0,0 +1,151 @@
+module uwt_bior31
+ #(
+ parameter L = 1 // transform level
+ )
+ (
+ input wire clock, frame, reset,
+ input wire [23:0] x,
+ output wire [23:0] d,
+ output wire [23:0] a,
+ output wire [23:0] peak,
+ output wire [1:0] flag
+ );
+
+ localparam index1 = 1 << (L - 1);
+ localparam index2 = 2 << (L - 1);
+ localparam index3 = 3 << (L - 1);
+ localparam peak_index = ((index3 + 1) >> 1) + 1;
+ localparam peak_shift = ((L - 1) << 1) + (L - 1);
+ localparam zero = 24'h800000;
+
+ // Tapped delay line
+ reg [23:0] tap_reg [index3:0];
+ reg [23:0] tap_next [index3:0];
+
+ reg [23:0] d_reg, d_next;
+ reg [23:0] a_reg, a_next;
+ reg [23:0] peak_reg, peak_next;
+
+ reg [23:0] tmp1_reg, tmp1_next;
+ reg [23:0] tmp2_reg, tmp2_next;
+
+ reg less_reg, less_next;
+ reg more_reg, more_next;
+
+ reg [1:0] flag_reg, flag_next;
+
+ reg int_case_reg, int_case_next;
+
+ integer i;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ begin
+ d_reg <= 0;
+ a_reg <= 0;
+ peak_reg <= 0;
+
+ tmp1_reg <= 0;
+ tmp2_reg <= 0;
+ less_reg <= 1'b0;
+ more_reg <= 1'b0;
+ flag_reg <= 0;
+
+ int_case_reg <= 1'b0;
+
+ for(i = 0; i <= index3; i = i + 1)
+ begin
+ tap_reg[i] <= 0;
+ end
+ end
+ else
+ begin
+ d_reg <= d_next;
+ a_reg <= a_next;
+ peak_reg <= peak_next;
+
+ tmp1_reg <= tmp1_next;
+ tmp2_reg <= tmp2_next;
+ less_reg <= less_next;
+ more_reg <= more_next;
+ flag_reg <= flag_next;
+
+ int_case_reg <= int_case_next;
+
+ for(i = 0; i <= index3; i = i + 1)
+ begin
+ tap_reg[i] <= tap_next[i];
+ end
+ end
+ end
+
+ always @*
+ begin
+ d_next = d_reg;
+ a_next = a_reg;
+ peak_next = peak_reg;
+
+ tmp1_next = tmp1_reg;
+ tmp2_next = tmp2_reg;
+ less_next = less_reg;
+ more_next = more_reg;
+ flag_next = flag_reg;
+
+ int_case_next = int_case_reg;
+
+ for(i = 0; i <= index3; i = i + 1)
+ begin
+ tap_next[i] = tap_reg[i];
+ end
+
+ case (int_case_reg)
+
+ 0:
+ begin
+ if (frame)
+ begin
+ // Tapped delay line: shift one
+ for(i = 0; i < index3; i = i + 1)
+ begin
+ tap_next[i+1] = tap_reg[i];
+ end
+
+ // Input in register 0
+ tap_next[0] = x;
+
+ tmp1_next = tap_reg[index3] + {tap_reg[index2][22:0], 1'b0} + tap_reg[index2];
+ tmp2_next = {tap_reg[index1][22:0], 1'b0} + tap_reg[index1] + tap_reg[0];
+
+ more_next = (d_reg > zero);
+ less_next = (d_reg < zero);
+
+ flag_next[0] = (less_reg) & (~less_next);
+ flag_next[1] = (more_reg) & (~more_next);
+
+ peak_next = (tap_reg[peak_index] >> peak_shift);
+
+ int_case_next = 1'b1;
+ end
+ end
+
+ 1:
+ begin
+ // Compute d and a with the filter coefficients.
+ // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1]
+ d_next = zero - tmp1_reg + tmp2_reg;
+ a_next = tmp1_reg + tmp2_reg;
+ int_case_next = 1'b0;
+ end
+
+ endcase
+
+ end
+
+ // output logic
+ assign d = d_reg;
+ assign a = a_reg;
+ assign peak = peak_reg;
+ assign flag = flag_reg;
+
+endmodule