Index: trunk/MultiChannelUSB/Paella.v
===================================================================
--- trunk/MultiChannelUSB/Paella.v	(revision 90)
+++ trunk/MultiChannelUSB/Paella.v	(revision 101)
@@ -104,8 +104,11 @@
 	);
 		
+	wire			ana_dead [N-1:0];
 	wire			ana_good [N-1:0];
 	wire	[11:0]	ana_data [N-1:0];
 	wire	[11:0]	ana_base [N-1:0];
 
+	wire			cnt_good [N-1:0];
+
 	wire	[11:0]	osc_mux_data [N-1:0];
 
@@ -119,4 +122,5 @@
 	wire 	[11:0]	adc_data [N-1:0];
     wire	[11:0]	int_data [N-1:0];
+    wire	[11:0]	sys_data [N-1:0];
     wire	[11:0]	cmp_data;
 	wire	[11:0]	nowhere;
@@ -146,7 +150,8 @@
 		.adc_data(adc_data[2]));
 */
-/* 
+ 
 	wire			adc_pll_clk;
 
+/*
 	adc_pll adc_pll_unit(
 		.inclk0(ADC_FCO),
@@ -154,8 +159,12 @@
 */
 
+	sys_pll sys_pll_unit(
+		.inclk0(CLK_50MHz),
+		.c0(sys_clock));
+
 	test test_unit(
 		.clk(ADC_FCO),
-//		.data(adc_data[2]));
-		.data(nowhere));
+		.data(adc_data[2]));
+//		.data(nowhere));
 
 	adc_lvds #(
@@ -166,15 +175,17 @@
 		.lvds_fco(ADC_FCO),
 		.lvds_d(ADC_D[2:0]),
-		.adc_data({	adc_data[2],
-//		.adc_data({	nowhere,
+//		.adc_data({	adc_data[2],
+		.adc_data({	nowhere,
 					adc_data[1],
 					adc_data[0] }));
-					
+
+/*					
 	assign			cmp_data = CON_B[11:0];
 	assign			sys_clock = ADC_DCO;
 	assign			sys_frame = ADC_FCO;
-
-	wire	[15:0]	cfg_bits [15:0];
-	wire	[255:0]	int_cfg_bits;
+*/
+
+	wire	[15:0]	cfg_bits [31:0];
+	wire	[511:0]	int_cfg_bits;
 
 	wire	[31:0]	cfg_mux_selector;
@@ -182,20 +193,20 @@
 	wire 			cfg_reset;
 
-	wire 	[7:0]	bus_ssel;
+	wire 	[8:0]	bus_ssel;
 	wire			bus_wren;
 	wire	[31:0]	bus_addr;
 	wire	[15:0]	bus_mosi;
-	wire 	[15:0]	bus_miso [5:0];
-	wire 	[5:0]	bus_busy;
+	wire 	[15:0]	bus_miso [7:0];
+	wire 	[8:0]	bus_busy;
 
 	wire 	[15:0]	mrg_bus_miso;
 	wire 			mrg_bus_busy;
 
-	wire 	[79:0]	int_bus_miso;
+	wire 	[127:0]	int_bus_miso;
 
 	genvar j;
 
 	generate
-		for (j = 0; j < 16; j = j + 1)
+		for (j = 0; j < 32; j = j + 1)
 		begin : CONFIGURATION_OUTPUT
 			assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
@@ -208,5 +219,5 @@
 		.bus_ssel(bus_ssel[0]),
 		.bus_wren(bus_wren),
-		.bus_addr(bus_addr[3:0]),
+		.bus_addr(bus_addr[4:0]),
 		.bus_mosi(bus_mosi),
 		.bus_miso(bus_miso[0]),
@@ -224,9 +235,9 @@
 				uwt_a2[j][17:6],
 				uwt_a1[j][14:3],
-				adc_data[j]};
+				sys_data[j]};
 		end
 	endgenerate
 
-	assign cfg_mux_selector = {cfg_bits[11], cfg_bits[10]};
+	assign cfg_mux_selector = {cfg_bits[3], cfg_bits[2]};
 
 	lpm_mux #(
@@ -258,6 +269,6 @@
 		.clock(sys_clock),
 		.frame(sys_frame),
-		.reset(cfg_bits[12][14]),
-		.cfg_data(cfg_bits[12][11:0]),
+		.reset(cfg_bits[0][0]),
+		.cfg_data(cfg_bits[5][11:0]),
 		.trg_data(trg_mux_data),
 		.trg_flag(trg_flag));
@@ -266,6 +277,6 @@
 		.clock(sys_clock),
 		.frame(sys_frame),
-		.reset(cfg_bits[12][13]),
-		.cfg_data({cfg_bits[12][12], cfg_bits[13]}),
+		.reset(cfg_bits[0][1]),
+		.cfg_data(cfg_bits[4][0]),
 		.trg_flag(trg_flag),
 		.osc_data({cmp_data, osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
@@ -280,9 +291,18 @@
 		.bus_busy(bus_busy[1]));
 
+
+	adc_fifo #(.W(48)) adc_fifo_unit (
+		.adc_clock(ADC_FCO),
+		.adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
+		.sys_clock(sys_clock),
+		.sys_frame(sys_frame),
+		.sys_data({cmp_data, int_data[2], int_data[1], int_data[0]}));
+
+
 	generate
 		for (j = 0; j < 3; j = j + 1)
 		begin : MCA_CHAIN
 
-			assign int_data[j] = (cfg_bits[0][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
+			assign sys_data[j] = (cfg_bits[1][4*j]) ? (int_data[j] ^ 12'hfff) : (int_data[j]);
 
 			uwt_bior31 #(.L(1)) uwt_1_unit (
@@ -290,5 +310,5 @@
 				.frame(sys_frame),
 				.reset(1'b0),
-				.x({20'h00000, int_data[j]}),
+				.x({20'h00000, sys_data[j]}),
 				.d(uwt_d1[j]),
 				.a(uwt_a1[j]),
@@ -319,8 +339,9 @@
 				.clock(sys_clock),
 				.frame(sys_frame),
-				.reset(cfg_bits[2+2*j][12]),
-				.cfg_data({cfg_bits[2+2*j][11:0], cfg_bits[1+2*j][12:0]}),
+				.reset(cfg_bits[0][2+j]),
+				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
 				.uwt_flag(uwt_flag3[j]),
 				.uwt_data(uwt_peak3[j]),
+				.ana_dead(ana_dead[j]),
 				.ana_good(ana_good[j]),
 				.ana_data(ana_data[j]),
@@ -330,7 +351,6 @@
 				.clock(sys_clock),
 				.frame(sys_frame),
-				.reset(cfg_bits[7+j][13]),
-				.cfg_data(cfg_bits[7+j][12:0]),
-				.hst_good(ana_good[j]),
+				.reset(cfg_bits[0][5+j]),
+				.hst_good((ana_good[j]) & (cnt_good[j])),
 				.hst_data(ana_data[j]),
 				.bus_ssel(bus_ssel[2+j]),
@@ -341,4 +361,17 @@
 				.bus_busy(bus_busy[2+j]));
 
+			counter counter_unit (
+				.clock(sys_clock),
+				.frame((sys_frame) & (~ana_dead[j])),
+				.reset(cfg_bits[0][8+j]),
+				.cfg_data(cfg_bits[12+j]),
+				.bus_ssel(bus_ssel[5+j]),
+				.bus_wren(bus_wren),
+				.bus_addr(bus_addr[1:0]),
+				.bus_mosi(bus_mosi),
+				.bus_miso(bus_miso[5+j]),
+				.bus_busy(bus_busy[5+j]),
+				.cnt_good(cnt_good[j]));
+
 		end
 	endgenerate
@@ -357,11 +390,11 @@
 		.i2c_scl(I2C_SDA),
 		
-		.bus_ssel(bus_ssel[5]),
+		.bus_ssel(bus_ssel[8]),
 		.bus_wren(bus_wren),
 		.bus_mosi(bus_mosi),
-		.bus_busy(bus_busy[5]));
+		.bus_busy(bus_busy[8]));
 
 	generate
-		for (j = 0; j < 5; j = j + 1)
+		for (j = 0; j < 8; j = j + 1)
 		begin : BUS_OUTPUT
 			assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
@@ -370,5 +403,5 @@
 
 	lpm_mux #(
-		.lpm_size(5),
+		.lpm_size(8),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(16),
@@ -379,9 +412,9 @@
 
 	lpm_mux #(
-		.lpm_size(6),
+		.lpm_size(9),
 		.lpm_type("LPM_MUX"),
 		.lpm_width(1),
-		.lpm_widths(3)) bus_busy_mux_unit (
-		.sel(bus_addr[30:28]),
+		.lpm_widths(4)) bus_busy_mux_unit (
+		.sel(bus_addr[31:28]),
 		.data(bus_busy),
 		.result(mrg_bus_busy));
@@ -397,8 +430,8 @@
 
 	lpm_decode #(
-		.lpm_decodes(8),
+		.lpm_decodes(9),
 		.lpm_type("LPM_DECODE"),
-		.lpm_width(3)) lpm_decode_unit (
-		.data(bus_addr[30:28]),
+		.lpm_width(4)) lpm_decode_unit (
+		.data(bus_addr[31:28]),
 		.eq(bus_ssel),
 		.aclr(),
