- Timestamp:
- Mar 12, 2010, 11:58:29 AM (14 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/analyser.v
r90 r100 2 2 ( 3 3 input wire clock, frame, reset, 4 input wire [ 12:0] cfg_data,4 input wire [24:0] cfg_data, 5 5 input wire [1:0] uwt_flag, 6 6 input wire [11:0] uwt_data, 7 output wire ana_dead, 7 8 output wire ana_good, 8 9 output wire [11:0] ana_data, … … 10 11 ); 11 12 12 reg 13 reg [2:0] state_reg, state_next; 13 14 reg [4:0] counter_reg, counter_next; 15 reg dead_reg, dead_next; 14 16 reg good_reg, good_next; 15 17 reg [11:0] data_reg, data_next; 18 19 reg [19:0] sample_reg, sample_next; 16 20 17 21 reg [19:0] buffer_reg [31:0]; 18 22 reg [19:0] buffer_next [31:0]; 19 23 20 wire [19:0] sample = {8'd0, uwt_data};21 24 wire [11:0] baseline = buffer_reg[31][16:5]; 22 25 wire counter_max = (&counter_reg); … … 28 31 if (reset) 29 32 begin 30 state_reg <= 1'b0;33 state_reg <= 3'd0; 31 34 counter_reg <= 5'd0; 35 sample_reg = 20'd0; 36 dead_reg <= 1'b0; 32 37 good_reg <= 1'b0; 33 38 data_reg <= 12'd0; 34 for(i = 0; i <= 31; i = i + 1) 39 40 for (i = 0; i <= 31; i = i + 1) 35 41 begin 36 42 buffer_reg[i] <= 20'hfffff; … … 41 47 state_reg <= state_next; 42 48 counter_reg <= counter_next; 49 sample_reg <= sample_next; 50 dead_reg <= dead_next; 43 51 good_reg <= good_next; 44 52 data_reg <= data_next; 45 53 46 for (i = 0; i <= 31; i = i + 1)54 for (i = 0; i <= 31; i = i + 1) 47 55 begin 48 56 buffer_reg[i] <= buffer_next[i]; … … 55 63 state_next = state_reg; 56 64 counter_next = counter_reg; 65 sample_next = sample_reg; 66 dead_next = dead_reg; 57 67 good_next = good_reg; 58 68 data_next = data_reg; 59 69 60 for (i = 0; i <= 31; i = i + 1)70 for (i = 0; i <= 31; i = i + 1) 61 71 begin 62 72 buffer_next[i] = buffer_reg[i]; … … 71 81 if (counter_max) 72 82 begin 73 state_next = 1'b1;83 state_next = 3'd1; 74 84 end 75 85 end 76 86 end 77 87 78 1: 88 1: // skip first 32 baseline samples 89 begin 90 if (frame) 91 begin 92 for (i = 0; i < 31; i = i + 1) 93 begin 94 buffer_next[i+1] = buffer_reg[i] + {8'd0, uwt_data}; 95 end 96 buffer_next[0] = {8'd0, uwt_data}; 97 98 counter_next = counter_reg + 5'd1; 99 if (counter_max) 100 begin 101 state_next = 3'd2; 102 end 103 end 104 end 105 106 2: 79 107 begin 80 108 if (frame) 81 109 begin 82 110 83 if (cfg_data[ 12])111 if (cfg_data[24]) 84 112 begin 85 113 if (uwt_data > baseline) … … 94 122 else 95 123 begin 96 if (uwt_data > cfg_data[ 11:0])124 if (uwt_data > cfg_data[23:12]) 97 125 begin 98 data_next = uwt_data - cfg_data[ 11:0];126 data_next = uwt_data - cfg_data[23:12]; 99 127 end 100 128 else … … 103 131 end 104 132 end 133 134 sample_next = {8'd0, uwt_data}; 105 135 106 107 for(i = 0; i < 31; i = i + 1) 136 dead_next = 1'b1; 137 good_next = 1'b0; 138 139 state_next = 3'd3; 140 end 141 end 142 143 3: 144 begin 145 146 // if (sample - baseline < threshold) 147 if (data_reg < cfg_data[11:0]) 148 begin 149 for (i = 0; i < 31; i = i + 1) 108 150 begin 109 buffer_next[i+1] = buffer_reg[i] + sample ;151 buffer_next[i+1] = buffer_reg[i] + sample_reg; 110 152 end 111 buffer_next[0] = sample ;112 113 good_next = uwt_flag[0] & counter_max;153 buffer_next[0] = sample_reg; 154 dead_next = 1'b0; 155 end 114 156 115 // skip first 32 baseline samples 116 // skip 32 samples after peak 117 if (counter_max) 157 state_next = 3'd2; 158 159 // skip 32 samples after peak 160 if (counter_max) 161 begin 162 if (uwt_flag[0]) 118 163 begin 119 if (uwt_flag[0]) 120 begin 121 counter_next = 5'd0; 122 end 123 end 124 else 125 begin 126 counter_next = counter_reg + 5'd1; 164 counter_next = 5'd0; 165 state_next = 3'd4; 127 166 end 128 167 end 168 else 169 begin 170 counter_next = counter_reg + 5'd1; 171 end 129 172 end 173 174 4: 175 begin 176 good_next = dead_reg; 177 state_next = 2'd2; 178 end 130 179 endcase 131 180 end 132 181 182 assign ana_dead = dead_reg; 133 183 assign ana_good = good_reg; 134 184 assign ana_data = data_reg;
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