source: trunk/PaellaBase/Paella.v@ 15

Last change on this file since 15 was 15, checked in by demin, 15 years ago

set RAM_ADDR to all zeros
File size: 1.4 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [16:0] CON_B,
9 inout wire [11:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA,
23 input wire USB_FLAGB,
24 input wire USB_FLAGC,
25 inout wire [7:0] USB_PA,
26 inout wire [7:0] USB_PB,
27
28 output wire RAM_CLK,
29 output wire RAM_CE1,
30 output wire RAM_WE,
31 output wire [19:0] RAM_ADDR,
32 inout wire RAM_DQAP,
33 inout wire [7:0] RAM_DQA,
34 inout wire RAM_DQBP,
35 inout wire [7:0] RAM_DQB
36 );
37
38 // Turn off all output ports
39 assign USB_SLRD = 1'b0;
40 assign USB_SLWR = 1'b0;
41 assign RAM_CLK = 1'b0;
42 assign RAM_CE1 = 1'b0;
43 assign RAM_WE = 1'b0;
44 assign RAM_ADDR = 20'h00000;
45
46 // All inout ports turn to tri-state
47 assign TRG = 4'bz;
48 assign CON_A = 7'bz;
49 assign CON_B = 17'bz;
50 assign CON_C = 12'bz;
51 assign USB_PA = 8'bz;
52 assign USB_PB = 8'bz;
53 assign RAM_DQAP = 1'bz;
54 assign RAM_DQA = 8'bz;
55 assign RAM_DQBP = 1'bz;
56 assign RAM_DQB = 8'bz;
57
58 reg [31:0] counter;
59
60 assign LED = counter[25];
61
62 always @ (posedge CLK_50MHz)
63 begin
64 counter <= counter + 32'd1;
65 end
66
67endmodule
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