[102] | 1 | module uwt_bior31
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| 2 | #(
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| 3 | parameter L = 1 // transform level
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| 4 | )
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| 5 | (
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| 6 | input wire clock, frame, reset,
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| 7 | input wire [23:0] x,
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| 8 | output wire [23:0] d,
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| 9 | output wire [23:0] a,
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| 10 | output wire [23:0] peak,
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| 11 | output wire [1:0] flag
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| 12 | );
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| 13 |
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| 14 | localparam index1 = 1 << (L - 1);
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| 15 | localparam index2 = 2 << (L - 1);
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| 16 | localparam index3 = 3 << (L - 1);
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| 17 | localparam peak_index = ((index3 + 1) >> 1) + 1;
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| 18 | localparam peak_shift = ((L - 1) << 1) + (L - 1);
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| 19 | localparam zero = 24'h800000;
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| 20 |
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| 21 | // Tapped delay line
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| 22 | reg [23:0] tap_reg [index3:0];
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| 23 | reg [23:0] tap_next [index3:0];
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| 24 |
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| 25 | reg [23:0] d_reg, d_next;
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| 26 | reg [23:0] a_reg, a_next;
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| 27 | reg [23:0] peak_reg, peak_next;
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| 28 |
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| 29 | reg [23:0] tmp1_reg, tmp1_next;
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| 30 | reg [23:0] tmp2_reg, tmp2_next;
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| 31 |
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| 32 | reg less_reg, less_next;
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| 33 | reg more_reg, more_next;
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| 34 |
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| 35 | reg [1:0] flag_reg, flag_next;
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| 36 |
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| 37 | reg int_case_reg, int_case_next;
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| 38 |
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| 39 | integer i;
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| 40 |
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| 41 | always @(posedge clock)
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| 42 | begin
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| 43 | if (reset)
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| 44 | begin
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| 45 | d_reg <= 0;
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| 46 | a_reg <= 0;
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| 47 | peak_reg <= 0;
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| 48 |
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| 49 | tmp1_reg <= 0;
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| 50 | tmp2_reg <= 0;
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| 51 | less_reg <= 1'b0;
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| 52 | more_reg <= 1'b0;
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| 53 | flag_reg <= 0;
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| 54 |
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| 55 | int_case_reg <= 1'b0;
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| 56 |
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| 57 | for(i = 0; i <= index3; i = i + 1)
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| 58 | begin
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| 59 | tap_reg[i] <= 0;
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| 60 | end
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| 61 | end
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| 62 | else
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| 63 | begin
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| 64 | d_reg <= d_next;
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| 65 | a_reg <= a_next;
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| 66 | peak_reg <= peak_next;
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| 67 |
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| 68 | tmp1_reg <= tmp1_next;
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| 69 | tmp2_reg <= tmp2_next;
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| 70 | less_reg <= less_next;
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| 71 | more_reg <= more_next;
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| 72 | flag_reg <= flag_next;
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| 73 |
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| 74 | int_case_reg <= int_case_next;
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| 75 |
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| 76 | for(i = 0; i <= index3; i = i + 1)
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| 77 | begin
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| 78 | tap_reg[i] <= tap_next[i];
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| 79 | end
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| 80 | end
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| 81 | end
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| 82 |
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| 83 | always @*
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| 84 | begin
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| 85 | d_next = d_reg;
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| 86 | a_next = a_reg;
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| 87 | peak_next = peak_reg;
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| 88 |
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| 89 | tmp1_next = tmp1_reg;
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| 90 | tmp2_next = tmp2_reg;
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| 91 | less_next = less_reg;
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| 92 | more_next = more_reg;
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| 93 | flag_next = flag_reg;
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| 94 |
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| 95 | int_case_next = int_case_reg;
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| 96 |
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| 97 | for(i = 0; i <= index3; i = i + 1)
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| 98 | begin
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| 99 | tap_next[i] = tap_reg[i];
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| 100 | end
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| 101 |
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| 102 | case (int_case_reg)
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| 103 |
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| 104 | 0:
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| 105 | begin
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| 106 | if (frame)
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| 107 | begin
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| 108 | // Tapped delay line: shift one
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| 109 | for(i = 0; i < index3; i = i + 1)
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| 110 | begin
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| 111 | tap_next[i+1] = tap_reg[i];
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| 112 | end
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| 113 |
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| 114 | // Input in register 0
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| 115 | tap_next[0] = x;
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| 116 |
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| 117 | tmp1_next = tap_reg[index3] + {tap_reg[index2][22:0], 1'b0} + tap_reg[index2];
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| 118 | tmp2_next = {tap_reg[index1][22:0], 1'b0} + tap_reg[index1] + tap_reg[0];
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| 119 |
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| 120 | more_next = (d_reg > zero);
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| 121 | less_next = (d_reg < zero);
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| 122 |
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| 123 | flag_next[0] = (less_reg) & (~less_next);
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| 124 | flag_next[1] = (more_reg) & (~more_next);
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| 125 |
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| 126 | peak_next = (tap_reg[peak_index] >> peak_shift);
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| 127 |
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| 128 | int_case_next = 1'b1;
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| 129 | end
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| 130 | end
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| 131 |
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| 132 | 1:
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| 133 | begin
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| 134 | // Compute d and a with the filter coefficients.
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| 135 | // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1]
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| 136 | d_next = zero - tmp1_reg + tmp2_reg;
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| 137 | a_next = tmp1_reg + tmp2_reg;
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| 138 | int_case_next = 1'b0;
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| 139 | end
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| 140 |
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| 141 | endcase
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| 142 |
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| 143 | end
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| 144 |
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| 145 | // output logic
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| 146 | assign d = d_reg;
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| 147 | assign a = a_reg;
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| 148 | assign peak = peak_reg;
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| 149 | assign flag = flag_reg;
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| 150 |
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| 151 | endmodule
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