Rev | Line | |
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[102] | 1 | module trigger
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| 2 | (
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| 3 | input wire clock, frame, reset,
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| 4 | input wire [11:0] cfg_data,
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| 5 | input wire [11:0] trg_data,
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| 6 | output wire trg_flag
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| 7 | );
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| 8 |
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| 9 | reg trg_flag_reg;
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| 10 | reg [11:0] cfg_data_reg;
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| 11 | reg [11:0] trg_data_reg;
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| 12 |
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| 13 | always @(posedge clock)
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| 14 | begin
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| 15 | if (reset)
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| 16 | begin
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| 17 | trg_flag_reg <= 1'b0;
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| 18 | end
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| 19 | else
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| 20 | begin
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| 21 | if (frame)
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| 22 | begin
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| 23 | cfg_data_reg <= cfg_data;
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| 24 | trg_data_reg <= trg_data;
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| 25 | end
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| 26 | trg_flag_reg <= (trg_data_reg >= cfg_data_reg);
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| 27 | end
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| 28 | end
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| 29 |
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| 30 | assign trg_flag = trg_flag_reg;
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| 31 |
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| 32 | endmodule
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